awr2544_pac/dss_pcr/
pps4mstid_l.rs

1#[doc = "Register `PPS4MSTID_L` reader"]
2pub type R = crate::R<Pps4mstidLSpec>;
3#[doc = "Register `PPS4MSTID_L` writer"]
4pub type W = crate::W<Pps4mstidLSpec>;
5#[doc = "Field `PPS4_QUAD0_MSTID` reader - 15:0\\]
6There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
7pub type Pps4Quad0MstidR = crate::FieldReader<u16>;
8#[doc = "Field `PPS4_QUAD0_MSTID` writer - 15:0\\]
9There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
10pub type Pps4Quad0MstidW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
11#[doc = "Field `PPS4_QUAD1_MSTID` reader - 31:16\\]
12There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
13pub type Pps4Quad1MstidR = crate::FieldReader<u16>;
14#[doc = "Field `PPS4_QUAD1_MSTID` writer - 31:16\\]
15There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
16pub type Pps4Quad1MstidW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
17impl R {
18    #[doc = "Bits 0:15 - 15:0\\]
19There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
20    #[inline(always)]
21    pub fn pps4_quad0_mstid(&self) -> Pps4Quad0MstidR {
22        Pps4Quad0MstidR::new((self.bits & 0xffff) as u16)
23    }
24    #[doc = "Bits 16:31 - 31:16\\]
25There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
26    #[inline(always)]
27    pub fn pps4_quad1_mstid(&self) -> Pps4Quad1MstidR {
28        Pps4Quad1MstidR::new(((self.bits >> 16) & 0xffff) as u16)
29    }
30}
31impl W {
32    #[doc = "Bits 0:15 - 15:0\\]
33There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
34    #[inline(always)]
35    #[must_use]
36    pub fn pps4_quad0_mstid(&mut self) -> Pps4Quad0MstidW<Pps4mstidLSpec> {
37        Pps4Quad0MstidW::new(self, 0)
38    }
39    #[doc = "Bits 16:31 - 31:16\\]
40There are 16 bits for each quadrant in PPS frame. These bits set the permission for maximum of 16 masters to address the peripheral mapped in each of the quadrant. The scheme is similar to the one described for PS MSTID register in section 1.7.30. Readable in both user and privileged modes. 1 = The peripheral mapped in the quadrant can be addressed by master with matching Master-ID. 0 = The peripheral is locked for master with matching Master-ID. PCR responds with AERROR. Writable only in privileged mode 1 = Sets the corresponding bit. 0 = Clears the corresponding bit. Writes to unimplemented bits have no effect and reads yield 0."]
41    #[inline(always)]
42    #[must_use]
43    pub fn pps4_quad1_mstid(&mut self) -> Pps4Quad1MstidW<Pps4mstidLSpec> {
44        Pps4Quad1MstidW::new(self, 16)
45    }
46}
47#[doc = "Privileged Peripheral Frame Master-ID Protection Register4_L\n\nYou can [`read`](crate::Reg::read) this register and get [`pps4mstid_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pps4mstid_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
48pub struct Pps4mstidLSpec;
49impl crate::RegisterSpec for Pps4mstidLSpec {
50    type Ux = u32;
51}
52#[doc = "`read()` method returns [`pps4mstid_l::R`](R) reader structure"]
53impl crate::Readable for Pps4mstidLSpec {}
54#[doc = "`write(|w| ..)` method takes [`pps4mstid_l::W`](W) writer structure"]
55impl crate::Writable for Pps4mstidLSpec {
56    type Safety = crate::Unsafe;
57    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
59}
60#[doc = "`reset()` method sets PPS4MSTID_L to value 0"]
61impl crate::Resettable for Pps4mstidLSpec {
62    const RESET_VALUE: u32 = 0;
63}
awr2544_pac/dss_pcr/pps4mstid_l.rs

awr2544_pac/dss_pcr/
pps4mstid_l.rs
