awr2544-pac 0.1.0

A Peripheral Access Crate for the ti awr2544 radar devkit
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

#[doc = "Register `CRC_WDTOPLD1` reader"]
pub type R = crate::R<CrcWdtopld1Spec>;
#[doc = "Register `CRC_WDTOPLD1` writer"]
pub type W = crate::W<CrcWdtopld1Spec>;
#[doc = "Field `CRC_WDTOPLD1` reader - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
pub type CrcWdtopld1R = crate::FieldReader<u32>;
#[doc = "Field `CRC_WDTOPLD1` writer - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
pub type CrcWdtopld1W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
#[doc = "Field `Reserved1` reader - 31:24\\]
Reserved"]
pub type Reserved1R = crate::FieldReader;
#[doc = "Field `Reserved1` writer - 31:24\\]
Reserved"]
pub type Reserved1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
    #[doc = "Bits 0:23 - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
    #[inline(always)]
    pub fn crc_wdtopld1(&self) -> CrcWdtopld1R {
        CrcWdtopld1R::new(self.bits & 0x00ff_ffff)
    }
    #[doc = "Bits 24:31 - 31:24\\]
Reserved"]
    #[inline(always)]
    pub fn reserved1(&self) -> Reserved1R {
        Reserved1R::new(((self.bits >> 24) & 0xff) as u8)
    }
}
impl W {
    #[doc = "Bits 0:23 - 23:0\\]
Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns."]
    #[inline(always)]
    #[must_use]
    pub fn crc_wdtopld1(&mut self) -> CrcWdtopld1W<CrcWdtopld1Spec> {
        CrcWdtopld1W::new(self, 0)
    }
    #[doc = "Bits 24:31 - 31:24\\]
Reserved"]
    #[inline(always)]
    #[must_use]
    pub fn reserved1(&mut self) -> Reserved1W<CrcWdtopld1Spec> {
        Reserved1W::new(self, 24)
    }
}
#[doc = "Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer\n\nYou can [`read`](crate::Reg::read) this register and get [`crc_wdtopld1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crc_wdtopld1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrcWdtopld1Spec;
impl crate::RegisterSpec for CrcWdtopld1Spec {
    type Ux = u32;
}
#[doc = "`read()` method returns [`crc_wdtopld1::R`](R) reader structure"]
impl crate::Readable for CrcWdtopld1Spec {}
#[doc = "`write(|w| ..)` method takes [`crc_wdtopld1::W`](W) writer structure"]
impl crate::Writable for CrcWdtopld1Spec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CRC_WDTOPLD1 to value 0"]
impl crate::Resettable for CrcWdtopld1Spec {
    const RESET_VALUE: u32 = 0;
}