awr2544_pac/mss_ctrl/
r5_control.rs

1#[doc = "Register `R5_CONTROL` reader"]
2pub type R = crate::R<R5ControlSpec>;
3#[doc = "Register `R5_CONTROL` writer"]
4pub type W = crate::W<R5ControlSpec>;
5#[doc = "Field `lock_step` reader - 2:0\\]
6writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly."]
7pub type LockStepR = crate::FieldReader;
8#[doc = "Field `lock_step` writer - 2:0\\]
9writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly."]
10pub type LockStepW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
11#[doc = "Field `lock_step_switch_wait` reader - 10:8\\]
12writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch."]
13pub type LockStepSwitchWaitR = crate::FieldReader;
14#[doc = "Field `lock_step_switch_wait` writer - 10:8\\]
15writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch."]
16pub type LockStepSwitchWaitW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `reset_fsm_trigger` reader - 18:16\\]
18Write pulse bit field: writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit"]
19pub type ResetFsmTriggerR = crate::FieldReader;
20#[doc = "Field `reset_fsm_trigger` writer - 18:16\\]
21Write pulse bit field: writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit"]
22pub type ResetFsmTriggerW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
23#[doc = "Field `rom_wait_state` reader - 26:24\\]
24writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access. This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. (because it is a timing issue in this scenario)"]
25pub type RomWaitStateR = crate::FieldReader;
26#[doc = "Field `rom_wait_state` writer - 26:24\\]
27writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access. This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. (because it is a timing issue in this scenario)"]
28pub type RomWaitStateW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
29impl R {
30    #[doc = "Bits 0:2 - 2:0\\]
31writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly."]
32    #[inline(always)]
33    pub fn lock_step(&self) -> LockStepR {
34        LockStepR::new((self.bits & 7) as u8)
35    }
36    #[doc = "Bits 8:10 - 10:8\\]
37writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch."]
38    #[inline(always)]
39    pub fn lock_step_switch_wait(&self) -> LockStepSwitchWaitR {
40        LockStepSwitchWaitR::new(((self.bits >> 8) & 7) as u8)
41    }
42    #[doc = "Bits 16:18 - 18:16\\]
43Write pulse bit field: writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit"]
44    #[inline(always)]
45    pub fn reset_fsm_trigger(&self) -> ResetFsmTriggerR {
46        ResetFsmTriggerR::new(((self.bits >> 16) & 7) as u8)
47    }
48    #[doc = "Bits 24:26 - 26:24\\]
49writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access. This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. (because it is a timing issue in this scenario)"]
50    #[inline(always)]
51    pub fn rom_wait_state(&self) -> RomWaitStateR {
52        RomWaitStateR::new(((self.bits >> 24) & 7) as u8)
53    }
54}
55impl W {
56    #[doc = "Bits 0:2 - 2:0\\]
57writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly."]
58    #[inline(always)]
59    #[must_use]
60    pub fn lock_step(&mut self) -> LockStepW<R5ControlSpec> {
61        LockStepW::new(self, 0)
62    }
63    #[doc = "Bits 8:10 - 10:8\\]
64writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch."]
65    #[inline(always)]
66    #[must_use]
67    pub fn lock_step_switch_wait(&mut self) -> LockStepSwitchWaitW<R5ControlSpec> {
68        LockStepSwitchWaitW::new(self, 8)
69    }
70    #[doc = "Bits 16:18 - 18:16\\]
71Write pulse bit field: writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit"]
72    #[inline(always)]
73    #[must_use]
74    pub fn reset_fsm_trigger(&mut self) -> ResetFsmTriggerW<R5ControlSpec> {
75        ResetFsmTriggerW::new(self, 16)
76    }
77    #[doc = "Bits 24:26 - 26:24\\]
78writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access. This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. (because it is a timing issue in this scenario)"]
79    #[inline(always)]
80    #[must_use]
81    pub fn rom_wait_state(&mut self) -> RomWaitStateW<R5ControlSpec> {
82        RomWaitStateW::new(self, 24)
83    }
84}
85#[doc = "R5_CONTROL\n\nYou can [`read`](crate::Reg::read) this register and get [`r5_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`r5_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
86pub struct R5ControlSpec;
87impl crate::RegisterSpec for R5ControlSpec {
88    type Ux = u32;
89}
90#[doc = "`read()` method returns [`r5_control::R`](R) reader structure"]
91impl crate::Readable for R5ControlSpec {}
92#[doc = "`write(|w| ..)` method takes [`r5_control::W`](W) writer structure"]
93impl crate::Writable for R5ControlSpec {
94    type Safety = crate::Unsafe;
95    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
96    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97}
98#[doc = "`reset()` method sets R5_CONTROL to value 0"]
99impl crate::Resettable for R5ControlSpec {
100    const RESET_VALUE: u32 = 0;
101}
awr2544_pac/mss_ctrl/r5_control.rs

awr2544_pac/mss_ctrl/
r5_control.rs
