avrd/gen/atmega2564rfr2.rs
1//! The AVR ATmega2564RFR2 microcontroller
2//!
3//! # Variants
4//! | | Pinout | Mcu age | Operating temperature | Operating voltage | Max speed |
5//! |--------|--------|---------|-----------------------|-------------------|-----------|
6//! | ATmega2564RFR2-ZU | | VQFN48 | -40°C - 85°C | 1.8V - 3.6V | 16 MHz |
7//! | ATmega2564RFR2-ZUR | | VQFN48 | -40°C - 85°C | 1.8V - 3.6V | 16 MHz |
8//! | ATmega2564RFR2-ZF | | VQFN48 | -40°C - 125°C | 1.8V - 3.6V | 16 MHz |
9//! | ATmega2564RFR2-ZFR | | VQFN48 | -40°C - 125°C | 1.8V - 3.6V | 16 MHz |
10//!
11
12#![allow(non_upper_case_globals)]
13
14/// `LOW` register
15///
16/// Bitfields:
17///
18/// | Name | Mask (binary) |
19/// | ---- | ------------- |
20/// | CKOUT | 1000000 |
21/// | CKSEL_SUT | 111111 |
22/// | CKDIV8 | 10000000 |
23pub const LOW: *mut u8 = 0x0 as *mut u8;
24
25/// `LOCKBIT` register
26///
27/// Bitfields:
28///
29/// | Name | Mask (binary) |
30/// | ---- | ------------- |
31/// | LB | 11 |
32/// | BLB0 | 1100 |
33/// | BLB1 | 110000 |
34pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
35
36/// `HIGH` register
37///
38/// Bitfields:
39///
40/// | Name | Mask (binary) |
41/// | ---- | ------------- |
42/// | BOOTRST | 1 |
43/// | WDTON | 10000 |
44/// | BOOTSZ | 110 |
45/// | JTAGEN | 1000000 |
46/// | OCDEN | 10000000 |
47/// | EESAVE | 1000 |
48/// | SPIEN | 100000 |
49pub const HIGH: *mut u8 = 0x1 as *mut u8;
50
51/// `EXTENDED` register
52///
53/// Bitfields:
54///
55/// | Name | Mask (binary) |
56/// | ---- | ------------- |
57/// | BODLEVEL | 111 |
58pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
59
60/// Port A Input Pins Address.
61pub const PINA: *mut u8 = 0x20 as *mut u8;
62
63/// Port A Data Direction Register.
64pub const DDRA: *mut u8 = 0x21 as *mut u8;
65
66/// Port A Data Register.
67pub const PORTA: *mut u8 = 0x22 as *mut u8;
68
69/// Port B Input Pins Address.
70pub const PINB: *mut u8 = 0x23 as *mut u8;
71
72/// Port B Data Direction Register.
73pub const DDRB: *mut u8 = 0x24 as *mut u8;
74
75/// Port B Data Register.
76pub const PORTB: *mut u8 = 0x25 as *mut u8;
77
78/// Port C Input Pins Address.
79pub const PINC: *mut u8 = 0x26 as *mut u8;
80
81/// Port C Data Direction Register.
82pub const DDRC: *mut u8 = 0x27 as *mut u8;
83
84/// Port C Data Register.
85pub const PORTC: *mut u8 = 0x28 as *mut u8;
86
87/// Port D Input Pins Address.
88pub const PIND: *mut u8 = 0x29 as *mut u8;
89
90/// Port D Data Direction Register.
91pub const DDRD: *mut u8 = 0x2A as *mut u8;
92
93/// Port D Data Register.
94pub const PORTD: *mut u8 = 0x2B as *mut u8;
95
96/// Port E Input Pins Address.
97pub const PINE: *mut u8 = 0x2C as *mut u8;
98
99/// Port E Data Direction Register.
100pub const DDRE: *mut u8 = 0x2D as *mut u8;
101
102/// Port E Data Register.
103pub const PORTE: *mut u8 = 0x2E as *mut u8;
104
105/// Port F Input Pins Address.
106pub const PINF: *mut u8 = 0x2F as *mut u8;
107
108/// Port F Data Direction Register.
109pub const DDRF: *mut u8 = 0x30 as *mut u8;
110
111/// Port F Data Register.
112pub const PORTF: *mut u8 = 0x31 as *mut u8;
113
114/// Port G Input Pins Address.
115pub const PING: *mut u8 = 0x32 as *mut u8;
116
117/// Port G Data Direction Register.
118pub const DDRG: *mut u8 = 0x33 as *mut u8;
119
120/// Port G Data Register.
121pub const PORTG: *mut u8 = 0x34 as *mut u8;
122
123/// Timer/Counter0 Interrupt Flag Register.
124///
125/// Bitfields:
126///
127/// | Name | Mask (binary) |
128/// | ---- | ------------- |
129/// | OCF0B | 100 |
130/// | OCF0A | 10 |
131/// | TOV0 | 1 |
132pub const TIFR0: *mut u8 = 0x35 as *mut u8;
133
134/// Timer/Counter1 Interrupt Flag Register.
135///
136/// Bitfields:
137///
138/// | Name | Mask (binary) |
139/// | ---- | ------------- |
140/// | TOV1 | 1 |
141/// | OCF1A | 10 |
142/// | OCF1B | 100 |
143/// | OCF1C | 1000 |
144/// | ICF1 | 100000 |
145pub const TIFR1: *mut u8 = 0x36 as *mut u8;
146
147/// Timer/Counter Interrupt Flag Register.
148///
149/// Bitfields:
150///
151/// | Name | Mask (binary) |
152/// | ---- | ------------- |
153/// | OCF2B | 100 |
154/// | OCF2A | 10 |
155/// | TOV2 | 1 |
156pub const TIFR2: *mut u8 = 0x37 as *mut u8;
157
158/// Timer/Counter3 Interrupt Flag Register.
159///
160/// Bitfields:
161///
162/// | Name | Mask (binary) |
163/// | ---- | ------------- |
164/// | OCF3C | 1000 |
165/// | ICF3 | 100000 |
166/// | TOV3 | 1 |
167/// | OCF3A | 10 |
168/// | OCF3B | 100 |
169pub const TIFR3: *mut u8 = 0x38 as *mut u8;
170
171/// Timer/Counter4 Interrupt Flag Register.
172///
173/// Bitfields:
174///
175/// | Name | Mask (binary) |
176/// | ---- | ------------- |
177/// | ICF4 | 100000 |
178/// | OCF4A | 10 |
179/// | TOV4 | 1 |
180/// | OCF4B | 100 |
181/// | OCF4C | 1000 |
182pub const TIFR4: *mut u8 = 0x39 as *mut u8;
183
184/// Timer/Counter5 Interrupt Flag Register.
185///
186/// Bitfields:
187///
188/// | Name | Mask (binary) |
189/// | ---- | ------------- |
190/// | ICF5 | 100000 |
191/// | TOV5 | 1 |
192/// | OCF5A | 10 |
193/// | OCF5B | 100 |
194/// | OCF5C | 1000 |
195pub const TIFR5: *mut u8 = 0x3A as *mut u8;
196
197/// Pin Change Interrupt Flag Register.
198///
199/// Bitfields:
200///
201/// | Name | Mask (binary) |
202/// | ---- | ------------- |
203/// | PCIF | 111 |
204pub const PCIFR: *mut u8 = 0x3B as *mut u8;
205
206/// External Interrupt Flag Register.
207pub const EIFR: *mut u8 = 0x3C as *mut u8;
208
209/// External Interrupt Mask Register.
210pub const EIMSK: *mut u8 = 0x3D as *mut u8;
211
212/// General Purpose IO Register 0.
213///
214/// Bitfields:
215///
216/// | Name | Mask (binary) |
217/// | ---- | ------------- |
218/// | GPIOR04 | 10000 |
219/// | GPIOR06 | 1000000 |
220/// | GPIOR07 | 10000000 |
221/// | GPIOR05 | 100000 |
222/// | GPIOR01 | 10 |
223/// | GPIOR03 | 1000 |
224/// | GPIOR02 | 100 |
225/// | GPIOR00 | 1 |
226pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
227
228/// EEPROM Control Register.
229///
230/// Bitfields:
231///
232/// | Name | Mask (binary) |
233/// | ---- | ------------- |
234/// | EEMPE | 100 |
235/// | EERE | 1 |
236/// | EEPE | 10 |
237/// | EERIE | 1000 |
238/// | EEPM | 110000 |
239pub const EECR: *mut u8 = 0x3F as *mut u8;
240
241/// EEPROM Data Register.
242pub const EEDR: *mut u8 = 0x40 as *mut u8;
243
244/// EEPROM Address Register Bytes.
245pub const EEAR: *mut u16 = 0x41 as *mut u16;
246
247/// EEPROM Address Register Bytes low byte.
248pub const EEARL: *mut u8 = 0x41 as *mut u8;
249
250/// EEPROM Address Register Bytes high byte.
251pub const EEARH: *mut u8 = 0x42 as *mut u8;
252
253/// General Timer Counter Control register.
254///
255/// Bitfields:
256///
257/// | Name | Mask (binary) |
258/// | ---- | ------------- |
259/// | PSRASY | 10 |
260/// | TSM | 10000000 |
261pub const GTCCR: *mut u8 = 0x43 as *mut u8;
262
263/// Timer/Counter0 Control Register A.
264///
265/// Bitfields:
266///
267/// | Name | Mask (binary) |
268/// | ---- | ------------- |
269/// | COM0B | 110000 |
270/// | COM0A | 11000000 |
271/// | WGM0 | 11 |
272pub const TCCR0A: *mut u8 = 0x44 as *mut u8;
273
274/// Timer/Counter0 Control Register B.
275///
276/// Bitfields:
277///
278/// | Name | Mask (binary) |
279/// | ---- | ------------- |
280/// | WGM02 | 1000 |
281/// | FOC0B | 1000000 |
282/// | CS0 | 111 |
283/// | FOC0A | 10000000 |
284pub const TCCR0B: *mut u8 = 0x45 as *mut u8;
285
286/// Timer/Counter0 Register.
287pub const TCNT0: *mut u8 = 0x46 as *mut u8;
288
289/// Timer/Counter0 Output Compare Register.
290pub const OCR0A: *mut u8 = 0x47 as *mut u8;
291
292/// Timer/Counter0 Output Compare Register B.
293pub const OCR0B: *mut u8 = 0x48 as *mut u8;
294
295/// General Purpose IO Register 1.
296pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
297
298/// General Purpose I/O Register 2.
299pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
300
301/// SPI Control Register.
302///
303/// Bitfields:
304///
305/// | Name | Mask (binary) |
306/// | ---- | ------------- |
307/// | DORD | 100000 |
308/// | SPE | 1000000 |
309/// | CPHA | 100 |
310/// | SPIE | 10000000 |
311/// | MSTR | 10000 |
312/// | SPR | 11 |
313/// | CPOL | 1000 |
314pub const SPCR: *mut u8 = 0x4C as *mut u8;
315
316/// SPI Status Register.
317///
318/// Bitfields:
319///
320/// | Name | Mask (binary) |
321/// | ---- | ------------- |
322/// | SPI2X | 1 |
323/// | WCOL | 1000000 |
324/// | SPIF | 10000000 |
325pub const SPSR: *mut u8 = 0x4D as *mut u8;
326
327/// SPI Data Register.
328pub const SPDR: *mut u8 = 0x4E as *mut u8;
329
330/// Analog Comparator Control And Status Register.
331///
332/// Bitfields:
333///
334/// | Name | Mask (binary) |
335/// | ---- | ------------- |
336/// | ACIC | 100 |
337/// | ACIE | 1000 |
338/// | ACBG | 1000000 |
339/// | ACO | 100000 |
340/// | ACIS | 11 |
341/// | ACI | 10000 |
342/// | ACD | 10000000 |
343pub const ACSR: *mut u8 = 0x50 as *mut u8;
344
345/// On-Chip Debug Register.
346pub const OCDR: *mut u8 = 0x51 as *mut u8;
347
348/// Sleep Mode Control Register.
349///
350/// Bitfields:
351///
352/// | Name | Mask (binary) |
353/// | ---- | ------------- |
354/// | SE | 1 |
355/// | SM | 1110 |
356pub const SMCR: *mut u8 = 0x53 as *mut u8;
357
358/// MCU Status Register.
359///
360/// Bitfields:
361///
362/// | Name | Mask (binary) |
363/// | ---- | ------------- |
364/// | JTRF | 10000 |
365/// | WDRF | 1000 |
366/// | EXTRF | 10 |
367/// | PORF | 1 |
368/// | BORF | 100 |
369pub const MCUSR: *mut u8 = 0x54 as *mut u8;
370
371/// MCU Control Register.
372///
373/// Bitfields:
374///
375/// | Name | Mask (binary) |
376/// | ---- | ------------- |
377/// | PUD | 10000 |
378pub const MCUCR: *mut u8 = 0x55 as *mut u8;
379
380/// Store Program Memory Control Register.
381///
382/// Bitfields:
383///
384/// | Name | Mask (binary) |
385/// | ---- | ------------- |
386/// | SPMIE | 10000000 |
387/// | BLBSET | 1000 |
388/// | SPMEN | 1 |
389/// | RWWSRE | 10000 |
390/// | PGERS | 10 |
391/// | RWWSB | 1000000 |
392/// | PGWRT | 100 |
393/// | SIGRD | 100000 |
394pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
395
396/// Extended Z-pointer Register for ELPM/SPM.
397pub const RAMPZ: *mut u8 = 0x5B as *mut u8;
398
399/// Extended Indirect Register.
400pub const EIND: *mut u8 = 0x5C as *mut u8;
401
402/// Stack Pointer.
403pub const SP: *mut u16 = 0x5D as *mut u16;
404
405/// Stack Pointer low byte.
406pub const SPL: *mut u8 = 0x5D as *mut u8;
407
408/// Stack Pointer high byte.
409pub const SPH: *mut u8 = 0x5E as *mut u8;
410
411/// Status Register.
412///
413/// Bitfields:
414///
415/// | Name | Mask (binary) |
416/// | ---- | ------------- |
417/// | C | 1 |
418/// | H | 100000 |
419/// | S | 10000 |
420/// | I | 10000000 |
421/// | V | 1000 |
422/// | N | 100 |
423/// | Z | 10 |
424/// | T | 1000000 |
425pub const SREG: *mut u8 = 0x5F as *mut u8;
426
427/// Watchdog Timer Control Register.
428///
429/// Bitfields:
430///
431/// | Name | Mask (binary) |
432/// | ---- | ------------- |
433/// | WDP | 100111 |
434/// | WDE | 1000 |
435/// | WDCE | 10000 |
436/// | WDIE | 1000000 |
437/// | WDIF | 10000000 |
438pub const WDTCSR: *mut u8 = 0x60 as *mut u8;
439
440/// Clock Prescale Register.
441///
442/// Bitfields:
443///
444/// | Name | Mask (binary) |
445/// | ---- | ------------- |
446/// | CLKPS | 1111 |
447/// | CLKPCE | 10000000 |
448pub const CLKPR: *mut u8 = 0x61 as *mut u8;
449
450/// Power Reduction Register 2.
451///
452/// Bitfields:
453///
454/// | Name | Mask (binary) |
455/// | ---- | ------------- |
456/// | PRRAM2 | 100 |
457/// | PRRAM0 | 1 |
458/// | PRRAM3 | 1000 |
459/// | PRRAM1 | 10 |
460pub const PRR2: *mut u8 = 0x63 as *mut u8;
461
462/// Power Reduction Register0.
463///
464/// Bitfields:
465///
466/// | Name | Mask (binary) |
467/// | ---- | ------------- |
468/// | PRTIM2 | 1000000 |
469/// | PRTIM0 | 100000 |
470/// | PRPGA | 10000 |
471/// | PRSPI | 100 |
472/// | PRTIM1 | 1000 |
473/// | PRADC | 1 |
474/// | PRTWI | 10000000 |
475/// | PRUSART0 | 10 |
476pub const PRR0: *mut u8 = 0x64 as *mut u8;
477
478/// Power Reduction Register 1.
479///
480/// Bitfields:
481///
482/// | Name | Mask (binary) |
483/// | ---- | ------------- |
484/// | PRTIM3 | 1000 |
485/// | PRUSART1 | 1 |
486/// | PRTIM4 | 10000 |
487/// | PRTRX24 | 1000000 |
488/// | PRTIM5 | 100000 |
489pub const PRR1: *mut u8 = 0x65 as *mut u8;
490
491/// Oscillator Calibration Value.
492pub const OSCCAL: *mut u8 = 0x66 as *mut u8;
493
494/// Reference Voltage Calibration Register.
495///
496/// Bitfields:
497///
498/// | Name | Mask (binary) |
499/// | ---- | ------------- |
500/// | BGCAL_FINE | 1111000 |
501/// | BGCAL | 111 |
502pub const BGCR: *mut u8 = 0x67 as *mut u8;
503
504/// Pin Change Interrupt Control Register.
505///
506/// Bitfields:
507///
508/// | Name | Mask (binary) |
509/// | ---- | ------------- |
510/// | PCIE | 111 |
511pub const PCICR: *mut u8 = 0x68 as *mut u8;
512
513/// External Interrupt Control Register A.
514///
515/// Bitfields:
516///
517/// | Name | Mask (binary) |
518/// | ---- | ------------- |
519/// | ISC2 | 110000 |
520/// | ISC0 | 11 |
521/// | ISC1 | 1100 |
522/// | ISC3 | 11000000 |
523pub const EICRA: *mut u8 = 0x69 as *mut u8;
524
525/// External Interrupt Control Register B.
526///
527/// Bitfields:
528///
529/// | Name | Mask (binary) |
530/// | ---- | ------------- |
531/// | ISC5 | 1100 |
532/// | ISC7 | 11000000 |
533/// | ISC6 | 110000 |
534/// | ISC4 | 11 |
535pub const EICRB: *mut u8 = 0x6A as *mut u8;
536
537/// Pin Change Mask Register 0.
538pub const PCMSK0: *mut u8 = 0x6B as *mut u8;
539
540/// Pin Change Mask Register 1.
541pub const PCMSK1: *mut u8 = 0x6C as *mut u8;
542
543/// Pin Change Mask Register 2.
544pub const PCMSK2: *mut u8 = 0x6D as *mut u8;
545
546/// Timer/Counter0 Interrupt Mask Register.
547///
548/// Bitfields:
549///
550/// | Name | Mask (binary) |
551/// | ---- | ------------- |
552/// | OCIE0A | 10 |
553/// | TOIE0 | 1 |
554/// | OCIE0B | 100 |
555pub const TIMSK0: *mut u8 = 0x6E as *mut u8;
556
557/// Timer/Counter1 Interrupt Mask Register.
558///
559/// Bitfields:
560///
561/// | Name | Mask (binary) |
562/// | ---- | ------------- |
563/// | OCIE1C | 1000 |
564/// | OCIE1A | 10 |
565/// | TOIE1 | 1 |
566/// | ICIE1 | 100000 |
567/// | OCIE1B | 100 |
568pub const TIMSK1: *mut u8 = 0x6F as *mut u8;
569
570/// Timer/Counter Interrupt Mask register.
571///
572/// Bitfields:
573///
574/// | Name | Mask (binary) |
575/// | ---- | ------------- |
576/// | TOIE2 | 1 |
577/// | OCIE2B | 100 |
578/// | OCIE2A | 10 |
579pub const TIMSK2: *mut u8 = 0x70 as *mut u8;
580
581/// Timer/Counter3 Interrupt Mask Register.
582///
583/// Bitfields:
584///
585/// | Name | Mask (binary) |
586/// | ---- | ------------- |
587/// | ICIE3 | 100000 |
588/// | OCIE3C | 1000 |
589/// | OCIE3B | 100 |
590/// | OCIE3A | 10 |
591/// | TOIE3 | 1 |
592pub const TIMSK3: *mut u8 = 0x71 as *mut u8;
593
594/// Timer/Counter4 Interrupt Mask Register.
595///
596/// Bitfields:
597///
598/// | Name | Mask (binary) |
599/// | ---- | ------------- |
600/// | OCIE4B | 100 |
601/// | ICIE4 | 100000 |
602/// | TOIE4 | 1 |
603/// | OCIE4A | 10 |
604/// | OCIE4C | 1000 |
605pub const TIMSK4: *mut u8 = 0x72 as *mut u8;
606
607/// Timer/Counter5 Interrupt Mask Register.
608///
609/// Bitfields:
610///
611/// | Name | Mask (binary) |
612/// | ---- | ------------- |
613/// | TOIE5 | 1 |
614/// | OCIE5A | 10 |
615/// | OCIE5C | 1000 |
616/// | OCIE5B | 100 |
617/// | ICIE5 | 100000 |
618pub const TIMSK5: *mut u8 = 0x73 as *mut u8;
619
620/// Flash Extended-Mode Control-Register.
621///
622/// Bitfields:
623///
624/// | Name | Mask (binary) |
625/// | ---- | ------------- |
626/// | AEAM | 110000 |
627/// | ENEAM | 1000000 |
628pub const NEMCR: *mut u8 = 0x75 as *mut u8;
629
630/// The ADC Control and Status Register C.
631///
632/// Bitfields:
633///
634/// | Name | Mask (binary) |
635/// | ---- | ------------- |
636/// | ADTHT | 11000000 |
637/// | ADSUT | 11111 |
638pub const ADCSRC: *mut u8 = 0x77 as *mut u8;
639
640/// ADC Data Register Bytes low byte.
641pub const ADCL: *mut u8 = 0x78 as *mut u8;
642
643/// ADC Data Register Bytes.
644pub const ADC: *mut u16 = 0x78 as *mut u16;
645
646/// ADC Data Register Bytes high byte.
647pub const ADCH: *mut u8 = 0x79 as *mut u8;
648
649/// The ADC Control and Status Register A.
650///
651/// Bitfields:
652///
653/// | Name | Mask (binary) |
654/// | ---- | ------------- |
655/// | ADIF | 10000 |
656/// | ADSC | 1000000 |
657/// | ADPS | 111 |
658/// | ADATE | 100000 |
659/// | ADIE | 1000 |
660/// | ADEN | 10000000 |
661pub const ADCSRA: *mut u8 = 0x7A as *mut u8;
662
663/// The ADC Control and Status Register B.
664///
665/// Bitfields:
666///
667/// | Name | Mask (binary) |
668/// | ---- | ------------- |
669/// | AVDDOK | 10000000 |
670/// | MUX5 | 1000 |
671/// | ACCH | 10000 |
672/// | REFOK | 100000 |
673/// | ACME | 1000000 |
674/// | ADTS | 111 |
675pub const ADCSRB: *mut u8 = 0x7B as *mut u8;
676
677/// The ADC Multiplexer Selection Register.
678///
679/// Bitfields:
680///
681/// | Name | Mask (binary) |
682/// | ---- | ------------- |
683/// | MUX | 11111 |
684/// | ADLAR | 100000 |
685/// | REFS | 11000000 |
686pub const ADMUX: *mut u8 = 0x7C as *mut u8;
687
688/// Digital Input Disable Register 2.
689///
690/// Bitfields:
691///
692/// | Name | Mask (binary) |
693/// | ---- | ------------- |
694/// | ADC15D | 10000000 |
695/// | ADC8D | 1 |
696/// | ADC9D | 10 |
697/// | ADC10D | 100 |
698/// | ADC11D | 1000 |
699/// | ADC14D | 1000000 |
700/// | ADC13D | 100000 |
701/// | ADC12D | 10000 |
702pub const DIDR2: *mut u8 = 0x7D as *mut u8;
703
704/// Digital Input Disable Register 0.
705///
706/// Bitfields:
707///
708/// | Name | Mask (binary) |
709/// | ---- | ------------- |
710/// | ADC3D | 1000 |
711/// | ADC5D | 100000 |
712/// | ADC0D | 1 |
713/// | ADC2D | 100 |
714/// | ADC7D | 10000000 |
715/// | ADC6D | 1000000 |
716/// | ADC4D | 10000 |
717/// | ADC1D | 10 |
718pub const DIDR0: *mut u8 = 0x7E as *mut u8;
719
720/// Digital Input Disable Register 1.
721///
722/// Bitfields:
723///
724/// | Name | Mask (binary) |
725/// | ---- | ------------- |
726/// | AIN0D | 1 |
727/// | AIN1D | 10 |
728pub const DIDR1: *mut u8 = 0x7F as *mut u8;
729
730/// Timer/Counter1 Control Register A.
731///
732/// Bitfields:
733///
734/// | Name | Mask (binary) |
735/// | ---- | ------------- |
736/// | COM1C | 1100 |
737/// | COM1A | 11000000 |
738/// | COM1B | 110000 |
739pub const TCCR1A: *mut u8 = 0x80 as *mut u8;
740
741/// Timer/Counter1 Control Register B.
742///
743/// Bitfields:
744///
745/// | Name | Mask (binary) |
746/// | ---- | ------------- |
747/// | ICNC1 | 10000000 |
748/// | CS1 | 111 |
749/// | ICES1 | 1000000 |
750pub const TCCR1B: *mut u8 = 0x81 as *mut u8;
751
752/// Timer/Counter1 Control Register C.
753///
754/// Bitfields:
755///
756/// | Name | Mask (binary) |
757/// | ---- | ------------- |
758/// | FOC1B | 1000000 |
759/// | FOC1C | 100000 |
760/// | FOC1A | 10000000 |
761pub const TCCR1C: *mut u8 = 0x82 as *mut u8;
762
763/// Timer/Counter1 Bytes.
764pub const TCNT1: *mut u16 = 0x84 as *mut u16;
765
766/// Timer/Counter1 Bytes low byte.
767pub const TCNT1L: *mut u8 = 0x84 as *mut u8;
768
769/// Timer/Counter1 Bytes high byte.
770pub const TCNT1H: *mut u8 = 0x85 as *mut u8;
771
772/// Timer/Counter1 Input Capture Register Bytes.
773pub const ICR1: *mut u16 = 0x86 as *mut u16;
774
775/// Timer/Counter1 Input Capture Register Bytes low byte.
776pub const ICR1L: *mut u8 = 0x86 as *mut u8;
777
778/// Timer/Counter1 Input Capture Register Bytes high byte.
779pub const ICR1H: *mut u8 = 0x87 as *mut u8;
780
781/// Timer/Counter1 Output Compare Register A Bytes low byte.
782pub const OCR1AL: *mut u8 = 0x88 as *mut u8;
783
784/// Timer/Counter1 Output Compare Register A Bytes.
785pub const OCR1A: *mut u16 = 0x88 as *mut u16;
786
787/// Timer/Counter1 Output Compare Register A Bytes high byte.
788pub const OCR1AH: *mut u8 = 0x89 as *mut u8;
789
790/// Timer/Counter1 Output Compare Register B Bytes low byte.
791pub const OCR1BL: *mut u8 = 0x8A as *mut u8;
792
793/// Timer/Counter1 Output Compare Register B Bytes.
794pub const OCR1B: *mut u16 = 0x8A as *mut u16;
795
796/// Timer/Counter1 Output Compare Register B Bytes high byte.
797pub const OCR1BH: *mut u8 = 0x8B as *mut u8;
798
799/// Timer/Counter1 Output Compare Register C Bytes low byte.
800pub const OCR1CL: *mut u8 = 0x8C as *mut u8;
801
802/// Timer/Counter1 Output Compare Register C Bytes.
803pub const OCR1C: *mut u16 = 0x8C as *mut u16;
804
805/// Timer/Counter1 Output Compare Register C Bytes high byte.
806pub const OCR1CH: *mut u8 = 0x8D as *mut u8;
807
808/// Timer/Counter3 Control Register A.
809///
810/// Bitfields:
811///
812/// | Name | Mask (binary) |
813/// | ---- | ------------- |
814/// | COM3B | 110000 |
815/// | COM3C | 1100 |
816/// | COM3A | 11000000 |
817pub const TCCR3A: *mut u8 = 0x90 as *mut u8;
818
819/// Timer/Counter3 Control Register B.
820///
821/// Bitfields:
822///
823/// | Name | Mask (binary) |
824/// | ---- | ------------- |
825/// | ICNC3 | 10000000 |
826/// | CS3 | 111 |
827/// | ICES3 | 1000000 |
828pub const TCCR3B: *mut u8 = 0x91 as *mut u8;
829
830/// Timer/Counter3 Control Register C.
831///
832/// Bitfields:
833///
834/// | Name | Mask (binary) |
835/// | ---- | ------------- |
836/// | FOC3C | 100000 |
837/// | FOC3B | 1000000 |
838/// | FOC3A | 10000000 |
839pub const TCCR3C: *mut u8 = 0x92 as *mut u8;
840
841/// Timer/Counter3 Bytes.
842pub const TCNT3: *mut u16 = 0x94 as *mut u16;
843
844/// Timer/Counter3 Bytes low byte.
845pub const TCNT3L: *mut u8 = 0x94 as *mut u8;
846
847/// Timer/Counter3 Bytes high byte.
848pub const TCNT3H: *mut u8 = 0x95 as *mut u8;
849
850/// Timer/Counter3 Input Capture Register Bytes low byte.
851pub const ICR3L: *mut u8 = 0x96 as *mut u8;
852
853/// Timer/Counter3 Input Capture Register Bytes.
854pub const ICR3: *mut u16 = 0x96 as *mut u16;
855
856/// Timer/Counter3 Input Capture Register Bytes high byte.
857pub const ICR3H: *mut u8 = 0x97 as *mut u8;
858
859/// Timer/Counter3 Output Compare Register A Bytes.
860pub const OCR3A: *mut u16 = 0x98 as *mut u16;
861
862/// Timer/Counter3 Output Compare Register A Bytes low byte.
863pub const OCR3AL: *mut u8 = 0x98 as *mut u8;
864
865/// Timer/Counter3 Output Compare Register A Bytes high byte.
866pub const OCR3AH: *mut u8 = 0x99 as *mut u8;
867
868/// Timer/Counter3 Output Compare Register B Bytes.
869pub const OCR3B: *mut u16 = 0x9A as *mut u16;
870
871/// Timer/Counter3 Output Compare Register B Bytes low byte.
872pub const OCR3BL: *mut u8 = 0x9A as *mut u8;
873
874/// Timer/Counter3 Output Compare Register B Bytes high byte.
875pub const OCR3BH: *mut u8 = 0x9B as *mut u8;
876
877/// Timer/Counter3 Output Compare Register C Bytes.
878pub const OCR3C: *mut u16 = 0x9C as *mut u16;
879
880/// Timer/Counter3 Output Compare Register C Bytes low byte.
881pub const OCR3CL: *mut u8 = 0x9C as *mut u8;
882
883/// Timer/Counter3 Output Compare Register C Bytes high byte.
884pub const OCR3CH: *mut u8 = 0x9D as *mut u8;
885
886/// Timer/Counter4 Control Register A.
887///
888/// Bitfields:
889///
890/// | Name | Mask (binary) |
891/// | ---- | ------------- |
892/// | COM4C | 1100 |
893/// | COM4A | 11000000 |
894/// | COM4B | 110000 |
895pub const TCCR4A: *mut u8 = 0xA0 as *mut u8;
896
897/// Timer/Counter4 Control Register B.
898///
899/// Bitfields:
900///
901/// | Name | Mask (binary) |
902/// | ---- | ------------- |
903/// | CS4 | 111 |
904/// | ICES4 | 1000000 |
905/// | ICNC4 | 10000000 |
906pub const TCCR4B: *mut u8 = 0xA1 as *mut u8;
907
908/// Timer/Counter4 Control Register C.
909///
910/// Bitfields:
911///
912/// | Name | Mask (binary) |
913/// | ---- | ------------- |
914/// | FOC4A | 10000000 |
915/// | FOC4B | 1000000 |
916/// | FOC4C | 100000 |
917pub const TCCR4C: *mut u8 = 0xA2 as *mut u8;
918
919/// Timer/Counter4 Bytes low byte.
920pub const TCNT4L: *mut u8 = 0xA4 as *mut u8;
921
922/// Timer/Counter4 Bytes.
923pub const TCNT4: *mut u16 = 0xA4 as *mut u16;
924
925/// Timer/Counter4 Bytes high byte.
926pub const TCNT4H: *mut u8 = 0xA5 as *mut u8;
927
928/// Timer/Counter4 Input Capture Register Bytes.
929pub const ICR4: *mut u16 = 0xA6 as *mut u16;
930
931/// Timer/Counter4 Input Capture Register Bytes low byte.
932pub const ICR4L: *mut u8 = 0xA6 as *mut u8;
933
934/// Timer/Counter4 Input Capture Register Bytes high byte.
935pub const ICR4H: *mut u8 = 0xA7 as *mut u8;
936
937/// Timer/Counter4 Output Compare Register A Bytes.
938pub const OCR4A: *mut u16 = 0xA8 as *mut u16;
939
940/// Timer/Counter4 Output Compare Register A Bytes low byte.
941pub const OCR4AL: *mut u8 = 0xA8 as *mut u8;
942
943/// Timer/Counter4 Output Compare Register A Bytes high byte.
944pub const OCR4AH: *mut u8 = 0xA9 as *mut u8;
945
946/// Timer/Counter4 Output Compare Register B Bytes low byte.
947pub const OCR4BL: *mut u8 = 0xAA as *mut u8;
948
949/// Timer/Counter4 Output Compare Register B Bytes.
950pub const OCR4B: *mut u16 = 0xAA as *mut u16;
951
952/// Timer/Counter4 Output Compare Register B Bytes high byte.
953pub const OCR4BH: *mut u8 = 0xAB as *mut u8;
954
955/// Timer/Counter4 Output Compare Register C Bytes low byte.
956pub const OCR4CL: *mut u8 = 0xAC as *mut u8;
957
958/// Timer/Counter4 Output Compare Register C Bytes.
959pub const OCR4C: *mut u16 = 0xAC as *mut u16;
960
961/// Timer/Counter4 Output Compare Register C Bytes high byte.
962pub const OCR4CH: *mut u8 = 0xAD as *mut u8;
963
964/// Timer/Counter2 Control Register A.
965///
966/// Bitfields:
967///
968/// | Name | Mask (binary) |
969/// | ---- | ------------- |
970/// | COM2B | 110000 |
971/// | WGM2 | 11 |
972/// | COM2A | 11000000 |
973pub const TCCR2A: *mut u8 = 0xB0 as *mut u8;
974
975/// Timer/Counter2 Control Register B.
976///
977/// Bitfields:
978///
979/// | Name | Mask (binary) |
980/// | ---- | ------------- |
981/// | CS2 | 111 |
982/// | FOC2A | 10000000 |
983/// | WGM22 | 1000 |
984/// | FOC2B | 1000000 |
985pub const TCCR2B: *mut u8 = 0xB1 as *mut u8;
986
987/// Timer/Counter2.
988pub const TCNT2: *mut u8 = 0xB2 as *mut u8;
989
990/// Timer/Counter2 Output Compare Register A.
991pub const OCR2A: *mut u8 = 0xB3 as *mut u8;
992
993/// Timer/Counter2 Output Compare Register B.
994pub const OCR2B: *mut u8 = 0xB4 as *mut u8;
995
996/// Asynchronous Status Register.
997///
998/// Bitfields:
999///
1000/// | Name | Mask (binary) |
1001/// | ---- | ------------- |
1002/// | OCR2AUB | 1000 |
1003/// | OCR2BUB | 100 |
1004/// | AS2 | 100000 |
1005/// | EXCLK | 1000000 |
1006/// | TCR2AUB | 10 |
1007/// | TCN2UB | 10000 |
1008/// | TCR2BUB | 1 |
1009/// | EXCLKAMR | 10000000 |
1010pub const ASSR: *mut u8 = 0xB6 as *mut u8;
1011
1012/// TWI Bit Rate Register.
1013pub const TWBR: *mut u8 = 0xB8 as *mut u8;
1014
1015/// TWI Status Register.
1016///
1017/// Bitfields:
1018///
1019/// | Name | Mask (binary) |
1020/// | ---- | ------------- |
1021/// | TWPS | 11 |
1022/// | TWS | 11111000 |
1023pub const TWSR: *mut u8 = 0xB9 as *mut u8;
1024
1025/// TWI (Slave) Address Register.
1026///
1027/// Bitfields:
1028///
1029/// | Name | Mask (binary) |
1030/// | ---- | ------------- |
1031/// | TWA | 11111110 |
1032/// | TWGCE | 1 |
1033pub const TWAR: *mut u8 = 0xBA as *mut u8;
1034
1035/// TWI Data Register.
1036pub const TWDR: *mut u8 = 0xBB as *mut u8;
1037
1038/// TWI Control Register.
1039///
1040/// Bitfields:
1041///
1042/// | Name | Mask (binary) |
1043/// | ---- | ------------- |
1044/// | TWIE | 1 |
1045/// | TWINT | 10000000 |
1046/// | TWWC | 1000 |
1047/// | TWSTA | 100000 |
1048/// | TWSTO | 10000 |
1049/// | TWEN | 100 |
1050/// | TWEA | 1000000 |
1051pub const TWCR: *mut u8 = 0xBC as *mut u8;
1052
1053/// TWI (Slave) Address Mask Register.
1054///
1055/// Bitfields:
1056///
1057/// | Name | Mask (binary) |
1058/// | ---- | ------------- |
1059/// | TWAM | 11111110 |
1060pub const TWAMR: *mut u8 = 0xBD as *mut u8;
1061
1062/// Transceiver Interrupt Enable Register 1.
1063///
1064/// Bitfields:
1065///
1066/// | Name | Mask (binary) |
1067/// | ---- | ------------- |
1068/// | MAF_1_AMI_EN | 100 |
1069/// | MAF_3_AMI_EN | 10000 |
1070/// | TX_START_EN | 1 |
1071/// | MAF_2_AMI_EN | 1000 |
1072/// | MAF_0_AMI_EN | 10 |
1073pub const IRQ_MASK1: *mut u8 = 0xBE as *mut u8;
1074
1075/// Transceiver Interrupt Status Register 1.
1076///
1077/// Bitfields:
1078///
1079/// | Name | Mask (binary) |
1080/// | ---- | ------------- |
1081/// | MAF_1_AMI | 100 |
1082/// | MAF_2_AMI | 1000 |
1083/// | TX_START | 1 |
1084/// | MAF_0_AMI | 10 |
1085/// | MAF_3_AMI | 10000 |
1086pub const IRQ_STATUS1: *mut u8 = 0xBF as *mut u8;
1087
1088/// USART0 MSPIM Control and Status Register A.
1089///
1090/// Bitfields:
1091///
1092/// | Name | Mask (binary) |
1093/// | ---- | ------------- |
1094/// | UDRE0 | 100000 |
1095/// | TXC0 | 1000000 |
1096/// | RXC0 | 10000000 |
1097pub const UCSR0A: *mut u8 = 0xC0 as *mut u8;
1098
1099/// USART0 MSPIM Control and Status Register B.
1100///
1101/// Bitfields:
1102///
1103/// | Name | Mask (binary) |
1104/// | ---- | ------------- |
1105/// | TXEN0 | 1000 |
1106/// | RXCIE0 | 10000000 |
1107/// | TXCIE0 | 1000000 |
1108/// | RXEN0 | 10000 |
1109/// | UDRIE0 | 100000 |
1110pub const UCSR0B: *mut u8 = 0xC1 as *mut u8;
1111
1112/// USART0 MSPIM Control and Status Register C.
1113///
1114/// Bitfields:
1115///
1116/// | Name | Mask (binary) |
1117/// | ---- | ------------- |
1118/// | UCPOL0 | 1 |
1119/// | UCPHA0 | 10 |
1120/// | UDORD0 | 100 |
1121pub const UCSR0C: *mut u8 = 0xC2 as *mut u8;
1122
1123/// USART0 Baud Rate Register Bytes low byte.
1124pub const UBRR0L: *mut u8 = 0xC4 as *mut u8;
1125
1126/// USART0 Baud Rate Register Bytes.
1127pub const UBRR0: *mut u16 = 0xC4 as *mut u16;
1128
1129/// USART0 Baud Rate Register Bytes high byte.
1130pub const UBRR0H: *mut u8 = 0xC5 as *mut u8;
1131
1132/// USART0 I/O Data Register.
1133pub const UDR0: *mut u8 = 0xC6 as *mut u8;
1134
1135/// USART1 MSPIM Control and Status Register A.
1136///
1137/// Bitfields:
1138///
1139/// | Name | Mask (binary) |
1140/// | ---- | ------------- |
1141/// | UDRE1 | 100000 |
1142/// | TXC1 | 1000000 |
1143/// | RXC1 | 10000000 |
1144pub const UCSR1A: *mut u8 = 0xC8 as *mut u8;
1145
1146/// USART1 MSPIM Control and Status Register B.
1147///
1148/// Bitfields:
1149///
1150/// | Name | Mask (binary) |
1151/// | ---- | ------------- |
1152/// | UDRIE1 | 100000 |
1153/// | RXCIE1 | 10000000 |
1154/// | TXCIE1 | 1000000 |
1155/// | RXEN1 | 10000 |
1156/// | TXEN1 | 1000 |
1157pub const UCSR1B: *mut u8 = 0xC9 as *mut u8;
1158
1159/// USART1 MSPIM Control and Status Register C.
1160///
1161/// Bitfields:
1162///
1163/// | Name | Mask (binary) |
1164/// | ---- | ------------- |
1165/// | UCPOL1 | 1 |
1166/// | UDORD1 | 100 |
1167/// | UCPHA1 | 10 |
1168pub const UCSR1C: *mut u8 = 0xCA as *mut u8;
1169
1170/// USART1 Baud Rate Register Bytes low byte.
1171pub const UBRR1L: *mut u8 = 0xCC as *mut u8;
1172
1173/// USART1 Baud Rate Register Bytes.
1174pub const UBRR1: *mut u16 = 0xCC as *mut u16;
1175
1176/// USART1 Baud Rate Register Bytes high byte.
1177pub const UBRR1H: *mut u8 = 0xCD as *mut u8;
1178
1179/// USART1 I/O Data Register.
1180pub const UDR1: *mut u8 = 0xCE as *mut u8;
1181
1182/// Symbol Counter Received Frame Timestamp Register LL-Byte.
1183pub const SCRSTRLL: *mut u8 = 0xD7 as *mut u8;
1184
1185/// Symbol Counter Received Frame Timestamp Register LH-Byte.
1186pub const SCRSTRLH: *mut u8 = 0xD8 as *mut u8;
1187
1188/// Symbol Counter Received Frame Timestamp Register HL-Byte.
1189pub const SCRSTRHL: *mut u8 = 0xD9 as *mut u8;
1190
1191/// Symbol Counter Received Frame Timestamp Register HH-Byte.
1192pub const SCRSTRHH: *mut u8 = 0xDA as *mut u8;
1193
1194/// Symbol Counter Compare Source Register.
1195///
1196/// Bitfields:
1197///
1198/// | Name | Mask (binary) |
1199/// | ---- | ------------- |
1200/// | SCCS1 | 11 |
1201/// | SCCS2 | 1100 |
1202/// | SCCS3 | 110000 |
1203pub const SCCSR: *mut u8 = 0xDB as *mut u8;
1204
1205/// Symbol Counter Control Register 0.
1206///
1207/// Bitfields:
1208///
1209/// | Name | Mask (binary) |
1210/// | ---- | ------------- |
1211/// | SCMBTS | 1000000 |
1212/// | SCEN | 100000 |
1213/// | SCTSE | 1000 |
1214/// | SCRES | 10000000 |
1215/// | SCCKSEL | 10000 |
1216/// | SCCMP | 111 |
1217pub const SCCR0: *mut u8 = 0xDC as *mut u8;
1218
1219/// Symbol Counter Control Register 1.
1220///
1221/// Bitfields:
1222///
1223/// | Name | Mask (binary) |
1224/// | ---- | ------------- |
1225/// | SCEECLK | 10 |
1226/// | SCCKDIV | 11100 |
1227/// | SCBTSM | 100000 |
1228/// | SCENBO | 1 |
1229pub const SCCR1: *mut u8 = 0xDD as *mut u8;
1230
1231/// Symbol Counter Status Register.
1232///
1233/// Bitfields:
1234///
1235/// | Name | Mask (binary) |
1236/// | ---- | ------------- |
1237/// | SCBSY | 1 |
1238pub const SCSR: *mut u8 = 0xDE as *mut u8;
1239
1240/// Symbol Counter Interrupt Mask Register.
1241///
1242/// Bitfields:
1243///
1244/// | Name | Mask (binary) |
1245/// | ---- | ------------- |
1246/// | IRQMBO | 10000 |
1247/// | IRQMOF | 1000 |
1248/// | IRQMCP | 111 |
1249pub const SCIRQM: *mut u8 = 0xDF as *mut u8;
1250
1251/// Symbol Counter Interrupt Status Register.
1252///
1253/// Bitfields:
1254///
1255/// | Name | Mask (binary) |
1256/// | ---- | ------------- |
1257/// | IRQSCP | 111 |
1258/// | IRQSOF | 1000 |
1259/// | IRQSBO | 10000 |
1260pub const SCIRQS: *mut u8 = 0xE0 as *mut u8;
1261
1262/// Symbol Counter Register LL-Byte.
1263pub const SCCNTLL: *mut u8 = 0xE1 as *mut u8;
1264
1265/// Symbol Counter Register LH-Byte.
1266pub const SCCNTLH: *mut u8 = 0xE2 as *mut u8;
1267
1268/// Symbol Counter Register HL-Byte.
1269pub const SCCNTHL: *mut u8 = 0xE3 as *mut u8;
1270
1271/// Symbol Counter Register HH-Byte.
1272pub const SCCNTHH: *mut u8 = 0xE4 as *mut u8;
1273
1274/// Symbol Counter Beacon Timestamp Register LL-Byte.
1275pub const SCBTSRLL: *mut u8 = 0xE5 as *mut u8;
1276
1277/// Symbol Counter Beacon Timestamp Register LH-Byte.
1278pub const SCBTSRLH: *mut u8 = 0xE6 as *mut u8;
1279
1280/// Symbol Counter Beacon Timestamp Register HL-Byte.
1281pub const SCBTSRHL: *mut u8 = 0xE7 as *mut u8;
1282
1283/// Symbol Counter Beacon Timestamp Register HH-Byte.
1284pub const SCBTSRHH: *mut u8 = 0xE8 as *mut u8;
1285
1286/// Symbol Counter Frame Timestamp Register LL-Byte.
1287pub const SCTSRLL: *mut u8 = 0xE9 as *mut u8;
1288
1289/// Symbol Counter Frame Timestamp Register LH-Byte.
1290pub const SCTSRLH: *mut u8 = 0xEA as *mut u8;
1291
1292/// Symbol Counter Frame Timestamp Register HL-Byte.
1293pub const SCTSRHL: *mut u8 = 0xEB as *mut u8;
1294
1295/// Symbol Counter Frame Timestamp Register HH-Byte.
1296pub const SCTSRHH: *mut u8 = 0xEC as *mut u8;
1297
1298/// Symbol Counter Output Compare Register 3 LL-Byte.
1299pub const SCOCR3LL: *mut u8 = 0xED as *mut u8;
1300
1301/// Symbol Counter Output Compare Register 3 LH-Byte.
1302pub const SCOCR3LH: *mut u8 = 0xEE as *mut u8;
1303
1304/// Symbol Counter Output Compare Register 3 HL-Byte.
1305pub const SCOCR3HL: *mut u8 = 0xEF as *mut u8;
1306
1307/// Symbol Counter Output Compare Register 3 HH-Byte.
1308pub const SCOCR3HH: *mut u8 = 0xF0 as *mut u8;
1309
1310/// Symbol Counter Output Compare Register 2 LL-Byte.
1311pub const SCOCR2LL: *mut u8 = 0xF1 as *mut u8;
1312
1313/// Symbol Counter Output Compare Register 2 LH-Byte.
1314pub const SCOCR2LH: *mut u8 = 0xF2 as *mut u8;
1315
1316/// Symbol Counter Output Compare Register 2 HL-Byte.
1317pub const SCOCR2HL: *mut u8 = 0xF3 as *mut u8;
1318
1319/// Symbol Counter Output Compare Register 2 HH-Byte.
1320pub const SCOCR2HH: *mut u8 = 0xF4 as *mut u8;
1321
1322/// Symbol Counter Output Compare Register 1 LL-Byte.
1323pub const SCOCR1LL: *mut u8 = 0xF5 as *mut u8;
1324
1325/// Symbol Counter Output Compare Register 1 LH-Byte.
1326pub const SCOCR1LH: *mut u8 = 0xF6 as *mut u8;
1327
1328/// Symbol Counter Output Compare Register 1 HL-Byte.
1329pub const SCOCR1HL: *mut u8 = 0xF7 as *mut u8;
1330
1331/// Symbol Counter Output Compare Register 1 HH-Byte.
1332pub const SCOCR1HH: *mut u8 = 0xF8 as *mut u8;
1333
1334/// Symbol Counter Transmit Frame Timestamp Register LL-Byte.
1335pub const SCTSTRLL: *mut u8 = 0xF9 as *mut u8;
1336
1337/// Symbol Counter Transmit Frame Timestamp Register LH-Byte.
1338pub const SCTSTRLH: *mut u8 = 0xFA as *mut u8;
1339
1340/// Symbol Counter Transmit Frame Timestamp Register HL-Byte.
1341pub const SCTSTRHL: *mut u8 = 0xFB as *mut u8;
1342
1343/// Symbol Counter Transmit Frame Timestamp Register HH-Byte.
1344pub const SCTSTRHH: *mut u8 = 0xFC as *mut u8;
1345
1346/// Multiple Address Filter Configuration Register 0.
1347///
1348/// Bitfields:
1349///
1350/// | Name | Mask (binary) |
1351/// | ---- | ------------- |
1352/// | MAF1EN | 10 |
1353/// | MAF3EN | 1000 |
1354/// | MAF0EN | 1 |
1355/// | MAF2EN | 100 |
1356pub const MAFCR0: *mut u8 = 0x10C as *mut u8;
1357
1358/// Multiple Address Filter Configuration Register 1.
1359///
1360/// Bitfields:
1361///
1362/// | Name | Mask (binary) |
1363/// | ---- | ------------- |
1364/// | AACK_2_SET_PD | 100000 |
1365/// | AACK_0_SET_PD | 10 |
1366/// | AACK_3_I_AM_COORD | 1000000 |
1367/// | AACK_1_I_AM_COORD | 100 |
1368/// | AACK_2_I_AM_COORD | 10000 |
1369/// | AACK_0_I_AM_COORD | 1 |
1370/// | AACK_1_SET_PD | 1000 |
1371/// | AACK_3_SET_PD | 10000000 |
1372pub const MAFCR1: *mut u8 = 0x10D as *mut u8;
1373
1374/// Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte).
1375pub const MAFSA0L: *mut u8 = 0x10E as *mut u8;
1376
1377/// Transceiver MAC Short Address Register for Frame Filter 0 (High Byte).
1378pub const MAFSA0H: *mut u8 = 0x10F as *mut u8;
1379
1380/// Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte).
1381pub const MAFPA0L: *mut u8 = 0x110 as *mut u8;
1382
1383/// Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte).
1384pub const MAFPA0H: *mut u8 = 0x111 as *mut u8;
1385
1386/// Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte).
1387pub const MAFSA1L: *mut u8 = 0x112 as *mut u8;
1388
1389/// Transceiver MAC Short Address Register for Frame Filter 1 (High Byte).
1390pub const MAFSA1H: *mut u8 = 0x113 as *mut u8;
1391
1392/// Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte).
1393pub const MAFPA1L: *mut u8 = 0x114 as *mut u8;
1394
1395/// Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte).
1396pub const MAFPA1H: *mut u8 = 0x115 as *mut u8;
1397
1398/// Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte).
1399pub const MAFSA2L: *mut u8 = 0x116 as *mut u8;
1400
1401/// Transceiver MAC Short Address Register for Frame Filter 2 (High Byte).
1402pub const MAFSA2H: *mut u8 = 0x117 as *mut u8;
1403
1404/// Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte).
1405pub const MAFPA2L: *mut u8 = 0x118 as *mut u8;
1406
1407/// Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte).
1408pub const MAFPA2H: *mut u8 = 0x119 as *mut u8;
1409
1410/// Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte).
1411pub const MAFSA3L: *mut u8 = 0x11A as *mut u8;
1412
1413/// Transceiver MAC Short Address Register for Frame Filter 3 (High Byte).
1414pub const MAFSA3H: *mut u8 = 0x11B as *mut u8;
1415
1416/// Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte).
1417pub const MAFPA3L: *mut u8 = 0x11C as *mut u8;
1418
1419/// Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte).
1420pub const MAFPA3H: *mut u8 = 0x11D as *mut u8;
1421
1422/// Timer/Counter5 Control Register A.
1423///
1424/// Bitfields:
1425///
1426/// | Name | Mask (binary) |
1427/// | ---- | ------------- |
1428/// | COM5C | 1100 |
1429/// | COM5A | 11000000 |
1430/// | COM5B | 110000 |
1431pub const TCCR5A: *mut u8 = 0x120 as *mut u8;
1432
1433/// Timer/Counter5 Control Register B.
1434///
1435/// Bitfields:
1436///
1437/// | Name | Mask (binary) |
1438/// | ---- | ------------- |
1439/// | CS5 | 111 |
1440/// | ICNC5 | 10000000 |
1441/// | ICES5 | 1000000 |
1442pub const TCCR5B: *mut u8 = 0x121 as *mut u8;
1443
1444/// Timer/Counter5 Control Register C.
1445///
1446/// Bitfields:
1447///
1448/// | Name | Mask (binary) |
1449/// | ---- | ------------- |
1450/// | FOC5A | 10000000 |
1451/// | FOC5B | 1000000 |
1452/// | FOC5C | 100000 |
1453pub const TCCR5C: *mut u8 = 0x122 as *mut u8;
1454
1455/// Timer/Counter5 Bytes low byte.
1456pub const TCNT5L: *mut u8 = 0x124 as *mut u8;
1457
1458/// Timer/Counter5 Bytes.
1459pub const TCNT5: *mut u16 = 0x124 as *mut u16;
1460
1461/// Timer/Counter5 Bytes high byte.
1462pub const TCNT5H: *mut u8 = 0x125 as *mut u8;
1463
1464/// Timer/Counter5 Input Capture Register Bytes.
1465pub const ICR5: *mut u16 = 0x126 as *mut u16;
1466
1467/// Timer/Counter5 Input Capture Register Bytes low byte.
1468pub const ICR5L: *mut u8 = 0x126 as *mut u8;
1469
1470/// Timer/Counter5 Input Capture Register Bytes high byte.
1471pub const ICR5H: *mut u8 = 0x127 as *mut u8;
1472
1473/// Timer/Counter5 Output Compare Register A Bytes.
1474pub const OCR5A: *mut u16 = 0x128 as *mut u16;
1475
1476/// Timer/Counter5 Output Compare Register A Bytes low byte.
1477pub const OCR5AL: *mut u8 = 0x128 as *mut u8;
1478
1479/// Timer/Counter5 Output Compare Register A Bytes high byte.
1480pub const OCR5AH: *mut u8 = 0x129 as *mut u8;
1481
1482/// Timer/Counter5 Output Compare Register B Bytes.
1483pub const OCR5B: *mut u16 = 0x12A as *mut u16;
1484
1485/// Timer/Counter5 Output Compare Register B Bytes low byte.
1486pub const OCR5BL: *mut u8 = 0x12A as *mut u8;
1487
1488/// Timer/Counter5 Output Compare Register B Bytes high byte.
1489pub const OCR5BH: *mut u8 = 0x12B as *mut u8;
1490
1491/// Timer/Counter5 Output Compare Register C Bytes low byte.
1492pub const OCR5CL: *mut u8 = 0x12C as *mut u8;
1493
1494/// Timer/Counter5 Output Compare Register C Bytes.
1495pub const OCR5C: *mut u16 = 0x12C as *mut u16;
1496
1497/// Timer/Counter5 Output Compare Register C Bytes high byte.
1498pub const OCR5CH: *mut u8 = 0x12D as *mut u8;
1499
1500/// Low Leakage Voltage Regulator Control Register.
1501///
1502/// Bitfields:
1503///
1504/// | Name | Mask (binary) |
1505/// | ---- | ------------- |
1506/// | LLDONE | 100000 |
1507/// | LLENCAL | 1 |
1508/// | LLCAL | 1000 |
1509/// | LLCOMP | 10000 |
1510/// | LLSHORT | 10 |
1511/// | LLTCO | 100 |
1512pub const LLCR: *mut u8 = 0x12F as *mut u8;
1513
1514/// Low Leakage Voltage Regulator Data Register (Low-Byte).
1515pub const LLDRL: *mut u8 = 0x130 as *mut u8;
1516
1517/// Low Leakage Voltage Regulator Data Register (High-Byte).
1518pub const LLDRH: *mut u8 = 0x131 as *mut u8;
1519
1520/// Data Retention Configuration Register #3.
1521pub const DRTRAM3: *mut u8 = 0x132 as *mut u8;
1522
1523/// Data Retention Configuration Register #2.
1524pub const DRTRAM2: *mut u8 = 0x133 as *mut u8;
1525
1526/// Data Retention Configuration Register #1.
1527pub const DRTRAM1: *mut u8 = 0x134 as *mut u8;
1528
1529/// Data Retention Configuration Register #0.
1530pub const DRTRAM0: *mut u8 = 0x135 as *mut u8;
1531
1532/// Port Driver Strength Register 0.
1533///
1534/// Bitfields:
1535///
1536/// | Name | Mask (binary) |
1537/// | ---- | ------------- |
1538/// | PFDRV | 11000000 |
1539/// | PBDRV | 11 |
1540/// | PEDRV | 110000 |
1541/// | PDDRV | 1100 |
1542pub const DPDS0: *mut u8 = 0x136 as *mut u8;
1543
1544/// Port Driver Strength Register 1.
1545///
1546/// Bitfields:
1547///
1548/// | Name | Mask (binary) |
1549/// | ---- | ------------- |
1550/// | PGDRV | 11 |
1551pub const DPDS1: *mut u8 = 0x137 as *mut u8;
1552
1553/// Power Amplifier Ramp up/down Control Register.
1554///
1555/// Bitfields:
1556///
1557/// | Name | Mask (binary) |
1558/// | ---- | ------------- |
1559/// | PARDFI | 10 |
1560/// | PARUFI | 1 |
1561/// | PALTD | 11100000 |
1562/// | PALTU | 11100 |
1563pub const PARCR: *mut u8 = 0x138 as *mut u8;
1564
1565/// Transceiver Pin Register.
1566///
1567/// Bitfields:
1568///
1569/// | Name | Mask (binary) |
1570/// | ---- | ------------- |
1571/// | SLPTR | 10 |
1572/// | TRXRST | 1 |
1573pub const TRXPR: *mut u8 = 0x139 as *mut u8;
1574
1575/// AES Control Register.
1576///
1577/// Bitfields:
1578///
1579/// | Name | Mask (binary) |
1580/// | ---- | ------------- |
1581/// | AES_REQUEST | 10000000 |
1582/// | AES_DIR | 1000 |
1583/// | AES_IM | 100 |
1584/// | AES_MODE | 100000 |
1585pub const AES_CTRL: *mut u8 = 0x13C as *mut u8;
1586
1587/// AES Status Register.
1588///
1589/// Bitfields:
1590///
1591/// | Name | Mask (binary) |
1592/// | ---- | ------------- |
1593/// | AES_ER | 10000000 |
1594/// | AES_DONE | 1 |
1595pub const AES_STATUS: *mut u8 = 0x13D as *mut u8;
1596
1597/// AES Plain and Cipher Text Buffer Register.
1598pub const AES_STATE: *mut u8 = 0x13E as *mut u8;
1599
1600/// AES Encryption and Decryption Key Buffer Register.
1601pub const AES_KEY: *mut u8 = 0x13F as *mut u8;
1602
1603/// Transceiver Status Register.
1604///
1605/// Bitfields:
1606///
1607/// | Name | Mask (binary) |
1608/// | ---- | ------------- |
1609/// | CCA_DONE | 10000000 |
1610/// | CCA_STATUS | 1000000 |
1611/// | TST_STATUS | 100000 |
1612pub const TRX_STATUS: *mut u8 = 0x141 as *mut u8;
1613
1614/// Transceiver State Control Register.
1615///
1616/// Bitfields:
1617///
1618/// | Name | Mask (binary) |
1619/// | ---- | ------------- |
1620/// | TRAC_STATUS | 11100000 |
1621/// | TRX_CMD | 11111 |
1622pub const TRX_STATE: *mut u8 = 0x142 as *mut u8;
1623
1624/// Reserved.
1625///
1626/// Bitfields:
1627///
1628/// | Name | Mask (binary) |
1629/// | ---- | ------------- |
1630/// | PMU_IF_INV | 10000 |
1631/// | PMU_START | 100000 |
1632/// | PMU_EN | 1000000 |
1633/// | Res7 | 10000000 |
1634pub const TRX_CTRL_0: *mut u8 = 0x143 as *mut u8;
1635
1636/// Transceiver Control Register 1.
1637///
1638/// Bitfields:
1639///
1640/// | Name | Mask (binary) |
1641/// | ---- | ------------- |
1642/// | TX_AUTO_CRC_ON | 100000 |
1643/// | PLL_TX_FLT | 10000 |
1644/// | PA_EXT_EN | 10000000 |
1645/// | IRQ_2_EXT_EN | 1000000 |
1646pub const TRX_CTRL_1: *mut u8 = 0x144 as *mut u8;
1647
1648/// Transceiver Transmit Power Control Register.
1649///
1650/// Bitfields:
1651///
1652/// | Name | Mask (binary) |
1653/// | ---- | ------------- |
1654/// | TX_PWR | 1111 |
1655pub const PHY_TX_PWR: *mut u8 = 0x145 as *mut u8;
1656
1657/// Receiver Signal Strength Indicator Register.
1658///
1659/// Bitfields:
1660///
1661/// | Name | Mask (binary) |
1662/// | ---- | ------------- |
1663/// | RSSI | 11111 |
1664/// | RX_CRC_VALID | 10000000 |
1665/// | RND_VALUE | 1100000 |
1666pub const PHY_RSSI: *mut u8 = 0x146 as *mut u8;
1667
1668/// Transceiver Energy Detection Level Register.
1669pub const PHY_ED_LEVEL: *mut u8 = 0x147 as *mut u8;
1670
1671/// Transceiver Clear Channel Assessment (CCA) Control Register.
1672///
1673/// Bitfields:
1674///
1675/// | Name | Mask (binary) |
1676/// | ---- | ------------- |
1677/// | CCA_MODE | 1100000 |
1678/// | CHANNEL | 11111 |
1679/// | CCA_REQUEST | 10000000 |
1680pub const PHY_CC_CCA: *mut u8 = 0x148 as *mut u8;
1681
1682/// Transceiver CCA Threshold Setting Register.
1683///
1684/// Bitfields:
1685///
1686/// | Name | Mask (binary) |
1687/// | ---- | ------------- |
1688/// | CCA_CS_THRES | 11110000 |
1689/// | CCA_ED_THRES | 1111 |
1690pub const CCA_THRES: *mut u8 = 0x149 as *mut u8;
1691
1692/// Transceiver Receive Control Register.
1693///
1694/// Bitfields:
1695///
1696/// | Name | Mask (binary) |
1697/// | ---- | ------------- |
1698/// | PDT_THRES | 1111 |
1699pub const RX_CTRL: *mut u8 = 0x14A as *mut u8;
1700
1701/// Start of Frame Delimiter Value Register.
1702pub const SFD_VALUE: *mut u8 = 0x14B as *mut u8;
1703
1704/// Transceiver Control Register 2.
1705///
1706/// Bitfields:
1707///
1708/// | Name | Mask (binary) |
1709/// | ---- | ------------- |
1710/// | RX_SAFE_MODE | 10000000 |
1711/// | OQPSK_DATA_RATE | 11 |
1712pub const TRX_CTRL_2: *mut u8 = 0x14C as *mut u8;
1713
1714/// Antenna Diversity Control Register.
1715///
1716/// Bitfields:
1717///
1718/// | Name | Mask (binary) |
1719/// | ---- | ------------- |
1720/// | ANT_DIV_EN | 1000 |
1721/// | ANT_SEL | 10000000 |
1722/// | ANT_EXT_SW_EN | 100 |
1723/// | ANT_CTRL | 11 |
1724pub const ANT_DIV: *mut u8 = 0x14D as *mut u8;
1725
1726/// Transceiver Interrupt Enable Register.
1727///
1728/// Bitfields:
1729///
1730/// | Name | Mask (binary) |
1731/// | ---- | ------------- |
1732/// | AWAKE_EN | 10000000 |
1733/// | RX_START_EN | 100 |
1734/// | TX_END_EN | 1000000 |
1735/// | PLL_UNLOCK_EN | 10 |
1736/// | PLL_LOCK_EN | 1 |
1737/// | RX_END_EN | 1000 |
1738/// | CCA_ED_DONE_EN | 10000 |
1739/// | AMI_EN | 100000 |
1740pub const IRQ_MASK: *mut u8 = 0x14E as *mut u8;
1741
1742/// Transceiver Interrupt Status Register.
1743///
1744/// Bitfields:
1745///
1746/// | Name | Mask (binary) |
1747/// | ---- | ------------- |
1748/// | CCA_ED_DONE | 10000 |
1749/// | TX_END | 1000000 |
1750/// | RX_END | 1000 |
1751/// | PLL_LOCK | 1 |
1752/// | AMI | 100000 |
1753/// | RX_START | 100 |
1754/// | AWAKE | 10000000 |
1755/// | PLL_UNLOCK | 10 |
1756pub const IRQ_STATUS: *mut u8 = 0x14F as *mut u8;
1757
1758/// Voltage Regulator Control and Status Register.
1759///
1760/// Bitfields:
1761///
1762/// | Name | Mask (binary) |
1763/// | ---- | ------------- |
1764/// | AVDD_OK | 1000000 |
1765/// | AVREG_EXT | 10000000 |
1766/// | DVDD_OK | 100 |
1767/// | DVREG_EXT | 1000 |
1768pub const VREG_CTRL: *mut u8 = 0x150 as *mut u8;
1769
1770/// Battery Monitor Control and Status Register.
1771///
1772/// Bitfields:
1773///
1774/// | Name | Mask (binary) |
1775/// | ---- | ------------- |
1776/// | BAT_LOW_EN | 1000000 |
1777/// | BATMON_OK | 100000 |
1778/// | BAT_LOW | 10000000 |
1779/// | BATMON_HR | 10000 |
1780/// | BATMON_VTH | 1111 |
1781pub const BATMON: *mut u8 = 0x151 as *mut u8;
1782
1783/// Crystal Oscillator Control Register.
1784///
1785/// Bitfields:
1786///
1787/// | Name | Mask (binary) |
1788/// | ---- | ------------- |
1789/// | XTAL_TRIM | 1111 |
1790/// | XTAL_MODE | 11110000 |
1791pub const XOSC_CTRL: *mut u8 = 0x152 as *mut u8;
1792
1793/// Channel Control Register 0.
1794pub const CC_CTRL_0: *mut u8 = 0x153 as *mut u8;
1795
1796/// Channel Control Register 1.
1797///
1798/// Bitfields:
1799///
1800/// | Name | Mask (binary) |
1801/// | ---- | ------------- |
1802/// | CC_BAND | 1111 |
1803pub const CC_CTRL_1: *mut u8 = 0x154 as *mut u8;
1804
1805/// Transceiver Receiver Sensitivity Control Register.
1806///
1807/// Bitfields:
1808///
1809/// | Name | Mask (binary) |
1810/// | ---- | ------------- |
1811/// | RX_PDT_DIS | 10000000 |
1812/// | RX_OVERRIDE | 1000000 |
1813/// | RX_PDT_LEVEL | 1111 |
1814pub const RX_SYN: *mut u8 = 0x155 as *mut u8;
1815
1816/// Transceiver Reduced Power Consumption Control.
1817///
1818/// Bitfields:
1819///
1820/// | Name | Mask (binary) |
1821/// | ---- | ------------- |
1822/// | PDT_RPC_EN | 10000 |
1823/// | IPAN_RPC_EN | 10 |
1824/// | XAH_RPC_EN | 1 |
1825/// | PLL_RPC_EN | 1000 |
1826/// | RX_RPC_EN | 100000 |
1827/// | RX_RPC_CTRL | 11000000 |
1828pub const TRX_RPC: *mut u8 = 0x156 as *mut u8;
1829
1830/// Transceiver Acknowledgment Frame Control Register 1.
1831///
1832/// Bitfields:
1833///
1834/// | Name | Mask (binary) |
1835/// | ---- | ------------- |
1836/// | AACK_FLTR_RES_FT | 100000 |
1837/// | AACK_PROM_MODE | 10 |
1838/// | AACK_ACK_TIME | 100 |
1839/// | AACK_UPLD_RES_FT | 10000 |
1840pub const XAH_CTRL_1: *mut u8 = 0x157 as *mut u8;
1841
1842/// Transceiver Filter Tuning Control Register.
1843///
1844/// Bitfields:
1845///
1846/// | Name | Mask (binary) |
1847/// | ---- | ------------- |
1848/// | FTN_START | 10000000 |
1849pub const FTN_CTRL: *mut u8 = 0x158 as *mut u8;
1850
1851/// Transceiver Center Frequency Calibration Control Register.
1852///
1853/// Bitfields:
1854///
1855/// | Name | Mask (binary) |
1856/// | ---- | ------------- |
1857/// | PLL_CF_START | 10000000 |
1858pub const PLL_CF: *mut u8 = 0x15A as *mut u8;
1859
1860/// Transceiver Delay Cell Calibration Control Register.
1861///
1862/// Bitfields:
1863///
1864/// | Name | Mask (binary) |
1865/// | ---- | ------------- |
1866/// | PLL_DCU_START | 10000000 |
1867pub const PLL_DCU: *mut u8 = 0x15B as *mut u8;
1868
1869/// Device Identification Register (Part Number).
1870pub const PART_NUM: *mut u8 = 0x15C as *mut u8;
1871
1872/// Device Identification Register (Version Number).
1873pub const VERSION_NUM: *mut u8 = 0x15D as *mut u8;
1874
1875/// Device Identification Register (Manufacture ID Low Byte).
1876///
1877/// Bitfields:
1878///
1879/// | Name | Mask (binary) |
1880/// | ---- | ------------- |
1881/// | MAN_ID_06 | 1000000 |
1882/// | MAN_ID_00 | 1 |
1883/// | MAN_ID_02 | 100 |
1884/// | MAN_ID_01 | 10 |
1885/// | MAN_ID_03 | 1000 |
1886/// | MAN_ID_04 | 10000 |
1887/// | MAN_ID_05 | 100000 |
1888/// | MAN_ID_07 | 10000000 |
1889pub const MAN_ID_0: *mut u8 = 0x15E as *mut u8;
1890
1891/// Device Identification Register (Manufacture ID High Byte).
1892pub const MAN_ID_1: *mut u8 = 0x15F as *mut u8;
1893
1894/// Transceiver MAC Short Address Register (Low Byte).
1895///
1896/// Bitfields:
1897///
1898/// | Name | Mask (binary) |
1899/// | ---- | ------------- |
1900/// | SHORT_ADDR_07 | 10000000 |
1901/// | SHORT_ADDR_04 | 10000 |
1902/// | SHORT_ADDR_02 | 100 |
1903/// | SHORT_ADDR_05 | 100000 |
1904/// | SHORT_ADDR_06 | 1000000 |
1905/// | SHORT_ADDR_01 | 10 |
1906/// | SHORT_ADDR_00 | 1 |
1907/// | SHORT_ADDR_03 | 1000 |
1908pub const SHORT_ADDR_0: *mut u8 = 0x160 as *mut u8;
1909
1910/// Transceiver MAC Short Address Register (High Byte).
1911pub const SHORT_ADDR_1: *mut u8 = 0x161 as *mut u8;
1912
1913/// Transceiver Personal Area Network ID Register (Low Byte).
1914///
1915/// Bitfields:
1916///
1917/// | Name | Mask (binary) |
1918/// | ---- | ------------- |
1919/// | PAN_ID_05 | 100000 |
1920/// | PAN_ID_07 | 10000000 |
1921/// | PAN_ID_00 | 1 |
1922/// | PAN_ID_04 | 10000 |
1923/// | PAN_ID_03 | 1000 |
1924/// | PAN_ID_02 | 100 |
1925/// | PAN_ID_06 | 1000000 |
1926/// | PAN_ID_01 | 10 |
1927pub const PAN_ID_0: *mut u8 = 0x162 as *mut u8;
1928
1929/// Transceiver Personal Area Network ID Register (High Byte).
1930pub const PAN_ID_1: *mut u8 = 0x163 as *mut u8;
1931
1932/// Transceiver MAC IEEE Address Register 0.
1933///
1934/// Bitfields:
1935///
1936/// | Name | Mask (binary) |
1937/// | ---- | ------------- |
1938/// | IEEE_ADDR_02 | 100 |
1939/// | IEEE_ADDR_05 | 100000 |
1940/// | IEEE_ADDR_03 | 1000 |
1941/// | IEEE_ADDR_04 | 10000 |
1942/// | IEEE_ADDR_01 | 10 |
1943/// | IEEE_ADDR_00 | 1 |
1944/// | IEEE_ADDR_06 | 1000000 |
1945/// | IEEE_ADDR_07 | 10000000 |
1946pub const IEEE_ADDR_0: *mut u8 = 0x164 as *mut u8;
1947
1948/// Transceiver MAC IEEE Address Register 1.
1949pub const IEEE_ADDR_1: *mut u8 = 0x165 as *mut u8;
1950
1951/// Transceiver MAC IEEE Address Register 2.
1952pub const IEEE_ADDR_2: *mut u8 = 0x166 as *mut u8;
1953
1954/// Transceiver MAC IEEE Address Register 3.
1955pub const IEEE_ADDR_3: *mut u8 = 0x167 as *mut u8;
1956
1957/// Transceiver MAC IEEE Address Register 4.
1958pub const IEEE_ADDR_4: *mut u8 = 0x168 as *mut u8;
1959
1960/// Transceiver MAC IEEE Address Register 5.
1961pub const IEEE_ADDR_5: *mut u8 = 0x169 as *mut u8;
1962
1963/// Transceiver MAC IEEE Address Register 6.
1964pub const IEEE_ADDR_6: *mut u8 = 0x16A as *mut u8;
1965
1966/// Transceiver MAC IEEE Address Register 7.
1967pub const IEEE_ADDR_7: *mut u8 = 0x16B as *mut u8;
1968
1969/// Transceiver Extended Operating Mode Control Register.
1970///
1971/// Bitfields:
1972///
1973/// | Name | Mask (binary) |
1974/// | ---- | ------------- |
1975/// | SLOTTED_OPERATION | 1 |
1976/// | MAX_FRAME_RETRIES | 11110000 |
1977/// | MAX_CSMA_RETRIES | 1110 |
1978pub const XAH_CTRL_0: *mut u8 = 0x16C as *mut u8;
1979
1980/// Transceiver CSMA-CA Random Number Generator Seed Register.
1981///
1982/// Bitfields:
1983///
1984/// | Name | Mask (binary) |
1985/// | ---- | ------------- |
1986/// | CSMA_SEED_05 | 100000 |
1987/// | CSMA_SEED_00 | 1 |
1988/// | CSMA_SEED_03 | 1000 |
1989/// | CSMA_SEED_07 | 10000000 |
1990/// | CSMA_SEED_01 | 10 |
1991/// | CSMA_SEED_04 | 10000 |
1992/// | CSMA_SEED_02 | 100 |
1993/// | CSMA_SEED_06 | 1000000 |
1994pub const CSMA_SEED_0: *mut u8 = 0x16D as *mut u8;
1995
1996/// Transceiver Acknowledgment Frame Control Register 2.
1997///
1998/// Bitfields:
1999///
2000/// | Name | Mask (binary) |
2001/// | ---- | ------------- |
2002/// | AACK_SET_PD | 100000 |
2003/// | AACK_DIS_ACK | 10000 |
2004/// | AACK_FVN_MODE | 11000000 |
2005/// | AACK_I_AM_COORD | 1000 |
2006pub const CSMA_SEED_1: *mut u8 = 0x16E as *mut u8;
2007
2008/// Transceiver CSMA-CA Back-off Exponent Control Register.
2009///
2010/// Bitfields:
2011///
2012/// | Name | Mask (binary) |
2013/// | ---- | ------------- |
2014/// | MIN_BE | 1111 |
2015/// | MAX_BE | 11110000 |
2016pub const CSMA_BE: *mut u8 = 0x16F as *mut u8;
2017
2018/// Transceiver Digital Test Control Register.
2019///
2020/// Bitfields:
2021///
2022/// | Name | Mask (binary) |
2023/// | ---- | ------------- |
2024/// | TST_CTRL_DIG | 1111 |
2025pub const TST_CTRL_DIGI: *mut u8 = 0x176 as *mut u8;
2026
2027/// Transceiver Received Frame Length Register.
2028pub const TST_RX_LENGTH: *mut u8 = 0x17B as *mut u8;
2029
2030/// Start of frame buffer.
2031pub const TRXFBST: *mut u8 = 0x180 as *mut u8;
2032
2033/// End of frame buffer.
2034pub const TRXFBEND: *mut u8 = 0x1FF as *mut u8;
2035
2036/// Bitfield on register `ACSR`
2037pub const ACIC: *mut u8 = 0x4 as *mut u8;
2038
2039/// Bitfield on register `ACSR`
2040pub const ACIE: *mut u8 = 0x8 as *mut u8;
2041
2042/// Bitfield on register `ACSR`
2043pub const ACBG: *mut u8 = 0x40 as *mut u8;
2044
2045/// Bitfield on register `ACSR`
2046pub const ACO: *mut u8 = 0x20 as *mut u8;
2047
2048/// Bitfield on register `ACSR`
2049pub const ACIS: *mut u8 = 0x3 as *mut u8;
2050
2051/// Bitfield on register `ACSR`
2052pub const ACI: *mut u8 = 0x10 as *mut u8;
2053
2054/// Bitfield on register `ACSR`
2055pub const ACD: *mut u8 = 0x80 as *mut u8;
2056
2057/// Bitfield on register `ADCSRA`
2058pub const ADIF: *mut u8 = 0x10 as *mut u8;
2059
2060/// Bitfield on register `ADCSRA`
2061pub const ADSC: *mut u8 = 0x40 as *mut u8;
2062
2063/// Bitfield on register `ADCSRA`
2064pub const ADPS: *mut u8 = 0x7 as *mut u8;
2065
2066/// Bitfield on register `ADCSRA`
2067pub const ADATE: *mut u8 = 0x20 as *mut u8;
2068
2069/// Bitfield on register `ADCSRA`
2070pub const ADIE: *mut u8 = 0x8 as *mut u8;
2071
2072/// Bitfield on register `ADCSRA`
2073pub const ADEN: *mut u8 = 0x80 as *mut u8;
2074
2075/// Bitfield on register `ADCSRB`
2076pub const AVDDOK: *mut u8 = 0x80 as *mut u8;
2077
2078/// Bitfield on register `ADCSRB`
2079pub const MUX5: *mut u8 = 0x8 as *mut u8;
2080
2081/// Bitfield on register `ADCSRB`
2082pub const ACCH: *mut u8 = 0x10 as *mut u8;
2083
2084/// Bitfield on register `ADCSRB`
2085pub const REFOK: *mut u8 = 0x20 as *mut u8;
2086
2087/// Bitfield on register `ADCSRB`
2088pub const ACME: *mut u8 = 0x40 as *mut u8;
2089
2090/// Bitfield on register `ADCSRB`
2091pub const ADTS: *mut u8 = 0x7 as *mut u8;
2092
2093/// Bitfield on register `ADCSRC`
2094pub const ADTHT: *mut u8 = 0xC0 as *mut u8;
2095
2096/// Bitfield on register `ADCSRC`
2097pub const ADSUT: *mut u8 = 0x1F as *mut u8;
2098
2099/// Bitfield on register `ADMUX`
2100pub const MUX: *mut u8 = 0x1F as *mut u8;
2101
2102/// Bitfield on register `ADMUX`
2103pub const ADLAR: *mut u8 = 0x20 as *mut u8;
2104
2105/// Bitfield on register `ADMUX`
2106pub const REFS: *mut u8 = 0xC0 as *mut u8;
2107
2108/// Bitfield on register `AES_CTRL`
2109pub const AES_REQUEST: *mut u8 = 0x80 as *mut u8;
2110
2111/// Bitfield on register `AES_CTRL`
2112pub const AES_DIR: *mut u8 = 0x8 as *mut u8;
2113
2114/// Bitfield on register `AES_CTRL`
2115pub const AES_IM: *mut u8 = 0x4 as *mut u8;
2116
2117/// Bitfield on register `AES_CTRL`
2118pub const AES_MODE: *mut u8 = 0x20 as *mut u8;
2119
2120/// Bitfield on register `AES_STATUS`
2121pub const AES_ER: *mut u8 = 0x80 as *mut u8;
2122
2123/// Bitfield on register `AES_STATUS`
2124pub const AES_DONE: *mut u8 = 0x1 as *mut u8;
2125
2126/// Bitfield on register `ANT_DIV`
2127pub const ANT_DIV_EN: *mut u8 = 0x8 as *mut u8;
2128
2129/// Bitfield on register `ANT_DIV`
2130pub const ANT_SEL: *mut u8 = 0x80 as *mut u8;
2131
2132/// Bitfield on register `ANT_DIV`
2133pub const ANT_EXT_SW_EN: *mut u8 = 0x4 as *mut u8;
2134
2135/// Bitfield on register `ANT_DIV`
2136pub const ANT_CTRL: *mut u8 = 0x3 as *mut u8;
2137
2138/// Bitfield on register `ASSR`
2139pub const OCR2AUB: *mut u8 = 0x8 as *mut u8;
2140
2141/// Bitfield on register `ASSR`
2142pub const OCR2BUB: *mut u8 = 0x4 as *mut u8;
2143
2144/// Bitfield on register `ASSR`
2145pub const AS2: *mut u8 = 0x20 as *mut u8;
2146
2147/// Bitfield on register `ASSR`
2148pub const EXCLK: *mut u8 = 0x40 as *mut u8;
2149
2150/// Bitfield on register `ASSR`
2151pub const TCR2AUB: *mut u8 = 0x2 as *mut u8;
2152
2153/// Bitfield on register `ASSR`
2154pub const TCN2UB: *mut u8 = 0x10 as *mut u8;
2155
2156/// Bitfield on register `ASSR`
2157pub const TCR2BUB: *mut u8 = 0x1 as *mut u8;
2158
2159/// Bitfield on register `ASSR`
2160pub const EXCLKAMR: *mut u8 = 0x80 as *mut u8;
2161
2162/// Bitfield on register `BATMON`
2163pub const BAT_LOW_EN: *mut u8 = 0x40 as *mut u8;
2164
2165/// Bitfield on register `BATMON`
2166pub const BATMON_OK: *mut u8 = 0x20 as *mut u8;
2167
2168/// Bitfield on register `BATMON`
2169pub const BAT_LOW: *mut u8 = 0x80 as *mut u8;
2170
2171/// Bitfield on register `BATMON`
2172pub const BATMON_HR: *mut u8 = 0x10 as *mut u8;
2173
2174/// Bitfield on register `BATMON`
2175pub const BATMON_VTH: *mut u8 = 0xF as *mut u8;
2176
2177/// Bitfield on register `BGCR`
2178pub const BGCAL_FINE: *mut u8 = 0x78 as *mut u8;
2179
2180/// Bitfield on register `BGCR`
2181pub const BGCAL: *mut u8 = 0x7 as *mut u8;
2182
2183/// Bitfield on register `CCA_THRES`
2184pub const CCA_CS_THRES: *mut u8 = 0xF0 as *mut u8;
2185
2186/// Bitfield on register `CCA_THRES`
2187pub const CCA_ED_THRES: *mut u8 = 0xF as *mut u8;
2188
2189/// Bitfield on register `CC_CTRL_1`
2190pub const CC_BAND: *mut u8 = 0xF as *mut u8;
2191
2192/// Bitfield on register `CLKPR`
2193pub const CLKPS: *mut u8 = 0xF as *mut u8;
2194
2195/// Bitfield on register `CLKPR`
2196pub const CLKPCE: *mut u8 = 0x80 as *mut u8;
2197
2198/// Bitfield on register `CSMA_BE`
2199pub const MIN_BE: *mut u8 = 0xF as *mut u8;
2200
2201/// Bitfield on register `CSMA_BE`
2202pub const MAX_BE: *mut u8 = 0xF0 as *mut u8;
2203
2204/// Bitfield on register `CSMA_SEED_0`
2205pub const CSMA_SEED_05: *mut u8 = 0x20 as *mut u8;
2206
2207/// Bitfield on register `CSMA_SEED_0`
2208pub const CSMA_SEED_00: *mut u8 = 0x1 as *mut u8;
2209
2210/// Bitfield on register `CSMA_SEED_0`
2211pub const CSMA_SEED_03: *mut u8 = 0x8 as *mut u8;
2212
2213/// Bitfield on register `CSMA_SEED_0`
2214pub const CSMA_SEED_07: *mut u8 = 0x80 as *mut u8;
2215
2216/// Bitfield on register `CSMA_SEED_0`
2217pub const CSMA_SEED_01: *mut u8 = 0x2 as *mut u8;
2218
2219/// Bitfield on register `CSMA_SEED_0`
2220pub const CSMA_SEED_04: *mut u8 = 0x10 as *mut u8;
2221
2222/// Bitfield on register `CSMA_SEED_0`
2223pub const CSMA_SEED_02: *mut u8 = 0x4 as *mut u8;
2224
2225/// Bitfield on register `CSMA_SEED_0`
2226pub const CSMA_SEED_06: *mut u8 = 0x40 as *mut u8;
2227
2228/// Bitfield on register `CSMA_SEED_1`
2229pub const AACK_SET_PD: *mut u8 = 0x20 as *mut u8;
2230
2231/// Bitfield on register `CSMA_SEED_1`
2232pub const AACK_DIS_ACK: *mut u8 = 0x10 as *mut u8;
2233
2234/// Bitfield on register `CSMA_SEED_1`
2235pub const AACK_FVN_MODE: *mut u8 = 0xC0 as *mut u8;
2236
2237/// Bitfield on register `CSMA_SEED_1`
2238pub const AACK_I_AM_COORD: *mut u8 = 0x8 as *mut u8;
2239
2240/// Bitfield on register `DIDR0`
2241pub const ADC3D: *mut u8 = 0x8 as *mut u8;
2242
2243/// Bitfield on register `DIDR0`
2244pub const ADC5D: *mut u8 = 0x20 as *mut u8;
2245
2246/// Bitfield on register `DIDR0`
2247pub const ADC0D: *mut u8 = 0x1 as *mut u8;
2248
2249/// Bitfield on register `DIDR0`
2250pub const ADC2D: *mut u8 = 0x4 as *mut u8;
2251
2252/// Bitfield on register `DIDR0`
2253pub const ADC7D: *mut u8 = 0x80 as *mut u8;
2254
2255/// Bitfield on register `DIDR0`
2256pub const ADC6D: *mut u8 = 0x40 as *mut u8;
2257
2258/// Bitfield on register `DIDR0`
2259pub const ADC4D: *mut u8 = 0x10 as *mut u8;
2260
2261/// Bitfield on register `DIDR0`
2262pub const ADC1D: *mut u8 = 0x2 as *mut u8;
2263
2264/// Bitfield on register `DIDR1`
2265pub const AIN0D: *mut u8 = 0x1 as *mut u8;
2266
2267/// Bitfield on register `DIDR1`
2268pub const AIN1D: *mut u8 = 0x2 as *mut u8;
2269
2270/// Bitfield on register `DIDR2`
2271pub const ADC15D: *mut u8 = 0x80 as *mut u8;
2272
2273/// Bitfield on register `DIDR2`
2274pub const ADC8D: *mut u8 = 0x1 as *mut u8;
2275
2276/// Bitfield on register `DIDR2`
2277pub const ADC9D: *mut u8 = 0x2 as *mut u8;
2278
2279/// Bitfield on register `DIDR2`
2280pub const ADC10D: *mut u8 = 0x4 as *mut u8;
2281
2282/// Bitfield on register `DIDR2`
2283pub const ADC11D: *mut u8 = 0x8 as *mut u8;
2284
2285/// Bitfield on register `DIDR2`
2286pub const ADC14D: *mut u8 = 0x40 as *mut u8;
2287
2288/// Bitfield on register `DIDR2`
2289pub const ADC13D: *mut u8 = 0x20 as *mut u8;
2290
2291/// Bitfield on register `DIDR2`
2292pub const ADC12D: *mut u8 = 0x10 as *mut u8;
2293
2294/// Bitfield on register `DPDS0`
2295pub const PFDRV: *mut u8 = 0xC0 as *mut u8;
2296
2297/// Bitfield on register `DPDS0`
2298pub const PBDRV: *mut u8 = 0x3 as *mut u8;
2299
2300/// Bitfield on register `DPDS0`
2301pub const PEDRV: *mut u8 = 0x30 as *mut u8;
2302
2303/// Bitfield on register `DPDS0`
2304pub const PDDRV: *mut u8 = 0xC as *mut u8;
2305
2306/// Bitfield on register `DPDS1`
2307pub const PGDRV: *mut u8 = 0x3 as *mut u8;
2308
2309/// Bitfield on register `EECR`
2310pub const EEMPE: *mut u8 = 0x4 as *mut u8;
2311
2312/// Bitfield on register `EECR`
2313pub const EERE: *mut u8 = 0x1 as *mut u8;
2314
2315/// Bitfield on register `EECR`
2316pub const EEPE: *mut u8 = 0x2 as *mut u8;
2317
2318/// Bitfield on register `EECR`
2319pub const EERIE: *mut u8 = 0x8 as *mut u8;
2320
2321/// Bitfield on register `EECR`
2322pub const EEPM: *mut u8 = 0x30 as *mut u8;
2323
2324/// Bitfield on register `EICRA`
2325pub const ISC2: *mut u8 = 0x30 as *mut u8;
2326
2327/// Bitfield on register `EICRA`
2328pub const ISC0: *mut u8 = 0x3 as *mut u8;
2329
2330/// Bitfield on register `EICRA`
2331pub const ISC1: *mut u8 = 0xC as *mut u8;
2332
2333/// Bitfield on register `EICRA`
2334pub const ISC3: *mut u8 = 0xC0 as *mut u8;
2335
2336/// Bitfield on register `EICRB`
2337pub const ISC5: *mut u8 = 0xC as *mut u8;
2338
2339/// Bitfield on register `EICRB`
2340pub const ISC7: *mut u8 = 0xC0 as *mut u8;
2341
2342/// Bitfield on register `EICRB`
2343pub const ISC6: *mut u8 = 0x30 as *mut u8;
2344
2345/// Bitfield on register `EICRB`
2346pub const ISC4: *mut u8 = 0x3 as *mut u8;
2347
2348/// Bitfield on register `EXTENDED`
2349pub const BODLEVEL: *mut u8 = 0x7 as *mut u8;
2350
2351/// Bitfield on register `FTN_CTRL`
2352pub const FTN_START: *mut u8 = 0x80 as *mut u8;
2353
2354/// Bitfield on register `GPIOR0`
2355pub const GPIOR04: *mut u8 = 0x10 as *mut u8;
2356
2357/// Bitfield on register `GPIOR0`
2358pub const GPIOR06: *mut u8 = 0x40 as *mut u8;
2359
2360/// Bitfield on register `GPIOR0`
2361pub const GPIOR07: *mut u8 = 0x80 as *mut u8;
2362
2363/// Bitfield on register `GPIOR0`
2364pub const GPIOR05: *mut u8 = 0x20 as *mut u8;
2365
2366/// Bitfield on register `GPIOR0`
2367pub const GPIOR01: *mut u8 = 0x2 as *mut u8;
2368
2369/// Bitfield on register `GPIOR0`
2370pub const GPIOR03: *mut u8 = 0x8 as *mut u8;
2371
2372/// Bitfield on register `GPIOR0`
2373pub const GPIOR02: *mut u8 = 0x4 as *mut u8;
2374
2375/// Bitfield on register `GPIOR0`
2376pub const GPIOR00: *mut u8 = 0x1 as *mut u8;
2377
2378/// Bitfield on register `GTCCR`
2379pub const PSRASY: *mut u8 = 0x2 as *mut u8;
2380
2381/// Bitfield on register `GTCCR`
2382pub const TSM: *mut u8 = 0x80 as *mut u8;
2383
2384/// Bitfield on register `HIGH`
2385pub const BOOTRST: *mut u8 = 0x1 as *mut u8;
2386
2387/// Bitfield on register `HIGH`
2388pub const WDTON: *mut u8 = 0x10 as *mut u8;
2389
2390/// Bitfield on register `HIGH`
2391pub const BOOTSZ: *mut u8 = 0x6 as *mut u8;
2392
2393/// Bitfield on register `HIGH`
2394pub const JTAGEN: *mut u8 = 0x40 as *mut u8;
2395
2396/// Bitfield on register `HIGH`
2397pub const OCDEN: *mut u8 = 0x80 as *mut u8;
2398
2399/// Bitfield on register `HIGH`
2400pub const EESAVE: *mut u8 = 0x8 as *mut u8;
2401
2402/// Bitfield on register `HIGH`
2403pub const SPIEN: *mut u8 = 0x20 as *mut u8;
2404
2405/// Bitfield on register `IEEE_ADDR_0`
2406pub const IEEE_ADDR_02: *mut u8 = 0x4 as *mut u8;
2407
2408/// Bitfield on register `IEEE_ADDR_0`
2409pub const IEEE_ADDR_05: *mut u8 = 0x20 as *mut u8;
2410
2411/// Bitfield on register `IEEE_ADDR_0`
2412pub const IEEE_ADDR_03: *mut u8 = 0x8 as *mut u8;
2413
2414/// Bitfield on register `IEEE_ADDR_0`
2415pub const IEEE_ADDR_04: *mut u8 = 0x10 as *mut u8;
2416
2417/// Bitfield on register `IEEE_ADDR_0`
2418pub const IEEE_ADDR_01: *mut u8 = 0x2 as *mut u8;
2419
2420/// Bitfield on register `IEEE_ADDR_0`
2421pub const IEEE_ADDR_00: *mut u8 = 0x1 as *mut u8;
2422
2423/// Bitfield on register `IEEE_ADDR_0`
2424pub const IEEE_ADDR_06: *mut u8 = 0x40 as *mut u8;
2425
2426/// Bitfield on register `IEEE_ADDR_0`
2427pub const IEEE_ADDR_07: *mut u8 = 0x80 as *mut u8;
2428
2429/// Bitfield on register `IRQ_MASK`
2430pub const AWAKE_EN: *mut u8 = 0x80 as *mut u8;
2431
2432/// Bitfield on register `IRQ_MASK`
2433pub const RX_START_EN: *mut u8 = 0x4 as *mut u8;
2434
2435/// Bitfield on register `IRQ_MASK`
2436pub const TX_END_EN: *mut u8 = 0x40 as *mut u8;
2437
2438/// Bitfield on register `IRQ_MASK`
2439pub const PLL_UNLOCK_EN: *mut u8 = 0x2 as *mut u8;
2440
2441/// Bitfield on register `IRQ_MASK`
2442pub const PLL_LOCK_EN: *mut u8 = 0x1 as *mut u8;
2443
2444/// Bitfield on register `IRQ_MASK`
2445pub const RX_END_EN: *mut u8 = 0x8 as *mut u8;
2446
2447/// Bitfield on register `IRQ_MASK`
2448pub const CCA_ED_DONE_EN: *mut u8 = 0x10 as *mut u8;
2449
2450/// Bitfield on register `IRQ_MASK`
2451pub const AMI_EN: *mut u8 = 0x20 as *mut u8;
2452
2453/// Bitfield on register `IRQ_MASK1`
2454pub const MAF_1_AMI_EN: *mut u8 = 0x4 as *mut u8;
2455
2456/// Bitfield on register `IRQ_MASK1`
2457pub const MAF_3_AMI_EN: *mut u8 = 0x10 as *mut u8;
2458
2459/// Bitfield on register `IRQ_MASK1`
2460pub const TX_START_EN: *mut u8 = 0x1 as *mut u8;
2461
2462/// Bitfield on register `IRQ_MASK1`
2463pub const MAF_2_AMI_EN: *mut u8 = 0x8 as *mut u8;
2464
2465/// Bitfield on register `IRQ_MASK1`
2466pub const MAF_0_AMI_EN: *mut u8 = 0x2 as *mut u8;
2467
2468/// Bitfield on register `IRQ_STATUS`
2469pub const CCA_ED_DONE: *mut u8 = 0x10 as *mut u8;
2470
2471/// Bitfield on register `IRQ_STATUS`
2472pub const TX_END: *mut u8 = 0x40 as *mut u8;
2473
2474/// Bitfield on register `IRQ_STATUS`
2475pub const RX_END: *mut u8 = 0x8 as *mut u8;
2476
2477/// Bitfield on register `IRQ_STATUS`
2478pub const PLL_LOCK: *mut u8 = 0x1 as *mut u8;
2479
2480/// Bitfield on register `IRQ_STATUS`
2481pub const AMI: *mut u8 = 0x20 as *mut u8;
2482
2483/// Bitfield on register `IRQ_STATUS`
2484pub const RX_START: *mut u8 = 0x4 as *mut u8;
2485
2486/// Bitfield on register `IRQ_STATUS`
2487pub const AWAKE: *mut u8 = 0x80 as *mut u8;
2488
2489/// Bitfield on register `IRQ_STATUS`
2490pub const PLL_UNLOCK: *mut u8 = 0x2 as *mut u8;
2491
2492/// Bitfield on register `IRQ_STATUS1`
2493pub const MAF_1_AMI: *mut u8 = 0x4 as *mut u8;
2494
2495/// Bitfield on register `IRQ_STATUS1`
2496pub const MAF_2_AMI: *mut u8 = 0x8 as *mut u8;
2497
2498/// Bitfield on register `IRQ_STATUS1`
2499pub const TX_START: *mut u8 = 0x1 as *mut u8;
2500
2501/// Bitfield on register `IRQ_STATUS1`
2502pub const MAF_0_AMI: *mut u8 = 0x2 as *mut u8;
2503
2504/// Bitfield on register `IRQ_STATUS1`
2505pub const MAF_3_AMI: *mut u8 = 0x10 as *mut u8;
2506
2507/// Bitfield on register `LLCR`
2508pub const LLDONE: *mut u8 = 0x20 as *mut u8;
2509
2510/// Bitfield on register `LLCR`
2511pub const LLENCAL: *mut u8 = 0x1 as *mut u8;
2512
2513/// Bitfield on register `LLCR`
2514pub const LLCAL: *mut u8 = 0x8 as *mut u8;
2515
2516/// Bitfield on register `LLCR`
2517pub const LLCOMP: *mut u8 = 0x10 as *mut u8;
2518
2519/// Bitfield on register `LLCR`
2520pub const LLSHORT: *mut u8 = 0x2 as *mut u8;
2521
2522/// Bitfield on register `LLCR`
2523pub const LLTCO: *mut u8 = 0x4 as *mut u8;
2524
2525/// Bitfield on register `LOCKBIT`
2526pub const LB: *mut u8 = 0x3 as *mut u8;
2527
2528/// Bitfield on register `LOCKBIT`
2529pub const BLB0: *mut u8 = 0xC as *mut u8;
2530
2531/// Bitfield on register `LOCKBIT`
2532pub const BLB1: *mut u8 = 0x30 as *mut u8;
2533
2534/// Bitfield on register `LOW`
2535pub const CKOUT: *mut u8 = 0x40 as *mut u8;
2536
2537/// Bitfield on register `LOW`
2538pub const CKSEL_SUT: *mut u8 = 0x3F as *mut u8;
2539
2540/// Bitfield on register `LOW`
2541pub const CKDIV8: *mut u8 = 0x80 as *mut u8;
2542
2543/// Bitfield on register `MAFCR0`
2544pub const MAF1EN: *mut u8 = 0x2 as *mut u8;
2545
2546/// Bitfield on register `MAFCR0`
2547pub const MAF3EN: *mut u8 = 0x8 as *mut u8;
2548
2549/// Bitfield on register `MAFCR0`
2550pub const MAF0EN: *mut u8 = 0x1 as *mut u8;
2551
2552/// Bitfield on register `MAFCR0`
2553pub const MAF2EN: *mut u8 = 0x4 as *mut u8;
2554
2555/// Bitfield on register `MAFCR1`
2556pub const AACK_2_SET_PD: *mut u8 = 0x20 as *mut u8;
2557
2558/// Bitfield on register `MAFCR1`
2559pub const AACK_0_SET_PD: *mut u8 = 0x2 as *mut u8;
2560
2561/// Bitfield on register `MAFCR1`
2562pub const AACK_3_I_AM_COORD: *mut u8 = 0x40 as *mut u8;
2563
2564/// Bitfield on register `MAFCR1`
2565pub const AACK_1_I_AM_COORD: *mut u8 = 0x4 as *mut u8;
2566
2567/// Bitfield on register `MAFCR1`
2568pub const AACK_2_I_AM_COORD: *mut u8 = 0x10 as *mut u8;
2569
2570/// Bitfield on register `MAFCR1`
2571pub const AACK_0_I_AM_COORD: *mut u8 = 0x1 as *mut u8;
2572
2573/// Bitfield on register `MAFCR1`
2574pub const AACK_1_SET_PD: *mut u8 = 0x8 as *mut u8;
2575
2576/// Bitfield on register `MAFCR1`
2577pub const AACK_3_SET_PD: *mut u8 = 0x80 as *mut u8;
2578
2579/// Bitfield on register `MAN_ID_0`
2580pub const MAN_ID_06: *mut u8 = 0x40 as *mut u8;
2581
2582/// Bitfield on register `MAN_ID_0`
2583pub const MAN_ID_00: *mut u8 = 0x1 as *mut u8;
2584
2585/// Bitfield on register `MAN_ID_0`
2586pub const MAN_ID_02: *mut u8 = 0x4 as *mut u8;
2587
2588/// Bitfield on register `MAN_ID_0`
2589pub const MAN_ID_01: *mut u8 = 0x2 as *mut u8;
2590
2591/// Bitfield on register `MAN_ID_0`
2592pub const MAN_ID_03: *mut u8 = 0x8 as *mut u8;
2593
2594/// Bitfield on register `MAN_ID_0`
2595pub const MAN_ID_04: *mut u8 = 0x10 as *mut u8;
2596
2597/// Bitfield on register `MAN_ID_0`
2598pub const MAN_ID_05: *mut u8 = 0x20 as *mut u8;
2599
2600/// Bitfield on register `MAN_ID_0`
2601pub const MAN_ID_07: *mut u8 = 0x80 as *mut u8;
2602
2603/// Bitfield on register `MCUCR`
2604pub const PUD: *mut u8 = 0x10 as *mut u8;
2605
2606/// Bitfield on register `MCUSR`
2607pub const JTRF: *mut u8 = 0x10 as *mut u8;
2608
2609/// Bitfield on register `MCUSR`
2610pub const WDRF: *mut u8 = 0x8 as *mut u8;
2611
2612/// Bitfield on register `MCUSR`
2613pub const EXTRF: *mut u8 = 0x2 as *mut u8;
2614
2615/// Bitfield on register `MCUSR`
2616pub const PORF: *mut u8 = 0x1 as *mut u8;
2617
2618/// Bitfield on register `MCUSR`
2619pub const BORF: *mut u8 = 0x4 as *mut u8;
2620
2621/// Bitfield on register `NEMCR`
2622pub const AEAM: *mut u8 = 0x30 as *mut u8;
2623
2624/// Bitfield on register `NEMCR`
2625pub const ENEAM: *mut u8 = 0x40 as *mut u8;
2626
2627/// Bitfield on register `PAN_ID_0`
2628pub const PAN_ID_05: *mut u8 = 0x20 as *mut u8;
2629
2630/// Bitfield on register `PAN_ID_0`
2631pub const PAN_ID_07: *mut u8 = 0x80 as *mut u8;
2632
2633/// Bitfield on register `PAN_ID_0`
2634pub const PAN_ID_00: *mut u8 = 0x1 as *mut u8;
2635
2636/// Bitfield on register `PAN_ID_0`
2637pub const PAN_ID_04: *mut u8 = 0x10 as *mut u8;
2638
2639/// Bitfield on register `PAN_ID_0`
2640pub const PAN_ID_03: *mut u8 = 0x8 as *mut u8;
2641
2642/// Bitfield on register `PAN_ID_0`
2643pub const PAN_ID_02: *mut u8 = 0x4 as *mut u8;
2644
2645/// Bitfield on register `PAN_ID_0`
2646pub const PAN_ID_06: *mut u8 = 0x40 as *mut u8;
2647
2648/// Bitfield on register `PAN_ID_0`
2649pub const PAN_ID_01: *mut u8 = 0x2 as *mut u8;
2650
2651/// Bitfield on register `PARCR`
2652pub const PARDFI: *mut u8 = 0x2 as *mut u8;
2653
2654/// Bitfield on register `PARCR`
2655pub const PARUFI: *mut u8 = 0x1 as *mut u8;
2656
2657/// Bitfield on register `PARCR`
2658pub const PALTD: *mut u8 = 0xE0 as *mut u8;
2659
2660/// Bitfield on register `PARCR`
2661pub const PALTU: *mut u8 = 0x1C as *mut u8;
2662
2663/// Bitfield on register `PCICR`
2664pub const PCIE: *mut u8 = 0x7 as *mut u8;
2665
2666/// Bitfield on register `PCIFR`
2667pub const PCIF: *mut u8 = 0x7 as *mut u8;
2668
2669/// Bitfield on register `PHY_CC_CCA`
2670pub const CCA_MODE: *mut u8 = 0x60 as *mut u8;
2671
2672/// Bitfield on register `PHY_CC_CCA`
2673pub const CHANNEL: *mut u8 = 0x1F as *mut u8;
2674
2675/// Bitfield on register `PHY_CC_CCA`
2676pub const CCA_REQUEST: *mut u8 = 0x80 as *mut u8;
2677
2678/// Bitfield on register `PHY_RSSI`
2679pub const RSSI: *mut u8 = 0x1F as *mut u8;
2680
2681/// Bitfield on register `PHY_RSSI`
2682pub const RX_CRC_VALID: *mut u8 = 0x80 as *mut u8;
2683
2684/// Bitfield on register `PHY_RSSI`
2685pub const RND_VALUE: *mut u8 = 0x60 as *mut u8;
2686
2687/// Bitfield on register `PHY_TX_PWR`
2688pub const TX_PWR: *mut u8 = 0xF as *mut u8;
2689
2690/// Bitfield on register `PLL_CF`
2691pub const PLL_CF_START: *mut u8 = 0x80 as *mut u8;
2692
2693/// Bitfield on register `PLL_DCU`
2694pub const PLL_DCU_START: *mut u8 = 0x80 as *mut u8;
2695
2696/// Bitfield on register `PRR0`
2697pub const PRTIM2: *mut u8 = 0x40 as *mut u8;
2698
2699/// Bitfield on register `PRR0`
2700pub const PRTIM0: *mut u8 = 0x20 as *mut u8;
2701
2702/// Bitfield on register `PRR0`
2703pub const PRPGA: *mut u8 = 0x10 as *mut u8;
2704
2705/// Bitfield on register `PRR0`
2706pub const PRSPI: *mut u8 = 0x4 as *mut u8;
2707
2708/// Bitfield on register `PRR0`
2709pub const PRTIM1: *mut u8 = 0x8 as *mut u8;
2710
2711/// Bitfield on register `PRR0`
2712pub const PRADC: *mut u8 = 0x1 as *mut u8;
2713
2714/// Bitfield on register `PRR0`
2715pub const PRTWI: *mut u8 = 0x80 as *mut u8;
2716
2717/// Bitfield on register `PRR0`
2718pub const PRUSART0: *mut u8 = 0x2 as *mut u8;
2719
2720/// Bitfield on register `PRR1`
2721pub const PRTIM3: *mut u8 = 0x8 as *mut u8;
2722
2723/// Bitfield on register `PRR1`
2724pub const PRUSART1: *mut u8 = 0x1 as *mut u8;
2725
2726/// Bitfield on register `PRR1`
2727pub const PRTIM4: *mut u8 = 0x10 as *mut u8;
2728
2729/// Bitfield on register `PRR1`
2730pub const PRTRX24: *mut u8 = 0x40 as *mut u8;
2731
2732/// Bitfield on register `PRR1`
2733pub const PRTIM5: *mut u8 = 0x20 as *mut u8;
2734
2735/// Bitfield on register `PRR2`
2736pub const PRRAM2: *mut u8 = 0x4 as *mut u8;
2737
2738/// Bitfield on register `PRR2`
2739pub const PRRAM0: *mut u8 = 0x1 as *mut u8;
2740
2741/// Bitfield on register `PRR2`
2742pub const PRRAM3: *mut u8 = 0x8 as *mut u8;
2743
2744/// Bitfield on register `PRR2`
2745pub const PRRAM1: *mut u8 = 0x2 as *mut u8;
2746
2747/// Bitfield on register `RX_CTRL`
2748pub const PDT_THRES: *mut u8 = 0xF as *mut u8;
2749
2750/// Bitfield on register `RX_SYN`
2751pub const RX_PDT_DIS: *mut u8 = 0x80 as *mut u8;
2752
2753/// Bitfield on register `RX_SYN`
2754pub const RX_OVERRIDE: *mut u8 = 0x40 as *mut u8;
2755
2756/// Bitfield on register `RX_SYN`
2757pub const RX_PDT_LEVEL: *mut u8 = 0xF as *mut u8;
2758
2759/// Bitfield on register `SCCR0`
2760pub const SCMBTS: *mut u8 = 0x40 as *mut u8;
2761
2762/// Bitfield on register `SCCR0`
2763pub const SCEN: *mut u8 = 0x20 as *mut u8;
2764
2765/// Bitfield on register `SCCR0`
2766pub const SCTSE: *mut u8 = 0x8 as *mut u8;
2767
2768/// Bitfield on register `SCCR0`
2769pub const SCRES: *mut u8 = 0x80 as *mut u8;
2770
2771/// Bitfield on register `SCCR0`
2772pub const SCCKSEL: *mut u8 = 0x10 as *mut u8;
2773
2774/// Bitfield on register `SCCR0`
2775pub const SCCMP: *mut u8 = 0x7 as *mut u8;
2776
2777/// Bitfield on register `SCCR1`
2778pub const SCEECLK: *mut u8 = 0x2 as *mut u8;
2779
2780/// Bitfield on register `SCCR1`
2781pub const SCCKDIV: *mut u8 = 0x1C as *mut u8;
2782
2783/// Bitfield on register `SCCR1`
2784pub const SCBTSM: *mut u8 = 0x20 as *mut u8;
2785
2786/// Bitfield on register `SCCR1`
2787pub const SCENBO: *mut u8 = 0x1 as *mut u8;
2788
2789/// Bitfield on register `SCCSR`
2790pub const SCCS1: *mut u8 = 0x3 as *mut u8;
2791
2792/// Bitfield on register `SCCSR`
2793pub const SCCS2: *mut u8 = 0xC as *mut u8;
2794
2795/// Bitfield on register `SCCSR`
2796pub const SCCS3: *mut u8 = 0x30 as *mut u8;
2797
2798/// Bitfield on register `SCIRQM`
2799pub const IRQMBO: *mut u8 = 0x10 as *mut u8;
2800
2801/// Bitfield on register `SCIRQM`
2802pub const IRQMOF: *mut u8 = 0x8 as *mut u8;
2803
2804/// Bitfield on register `SCIRQM`
2805pub const IRQMCP: *mut u8 = 0x7 as *mut u8;
2806
2807/// Bitfield on register `SCIRQS`
2808pub const IRQSCP: *mut u8 = 0x7 as *mut u8;
2809
2810/// Bitfield on register `SCIRQS`
2811pub const IRQSOF: *mut u8 = 0x8 as *mut u8;
2812
2813/// Bitfield on register `SCIRQS`
2814pub const IRQSBO: *mut u8 = 0x10 as *mut u8;
2815
2816/// Bitfield on register `SCSR`
2817pub const SCBSY: *mut u8 = 0x1 as *mut u8;
2818
2819/// Bitfield on register `SHORT_ADDR_0`
2820pub const SHORT_ADDR_07: *mut u8 = 0x80 as *mut u8;
2821
2822/// Bitfield on register `SHORT_ADDR_0`
2823pub const SHORT_ADDR_04: *mut u8 = 0x10 as *mut u8;
2824
2825/// Bitfield on register `SHORT_ADDR_0`
2826pub const SHORT_ADDR_02: *mut u8 = 0x4 as *mut u8;
2827
2828/// Bitfield on register `SHORT_ADDR_0`
2829pub const SHORT_ADDR_05: *mut u8 = 0x20 as *mut u8;
2830
2831/// Bitfield on register `SHORT_ADDR_0`
2832pub const SHORT_ADDR_06: *mut u8 = 0x40 as *mut u8;
2833
2834/// Bitfield on register `SHORT_ADDR_0`
2835pub const SHORT_ADDR_01: *mut u8 = 0x2 as *mut u8;
2836
2837/// Bitfield on register `SHORT_ADDR_0`
2838pub const SHORT_ADDR_00: *mut u8 = 0x1 as *mut u8;
2839
2840/// Bitfield on register `SHORT_ADDR_0`
2841pub const SHORT_ADDR_03: *mut u8 = 0x8 as *mut u8;
2842
2843/// Bitfield on register `SMCR`
2844pub const SE: *mut u8 = 0x1 as *mut u8;
2845
2846/// Bitfield on register `SMCR`
2847pub const SM: *mut u8 = 0xE as *mut u8;
2848
2849/// Bitfield on register `SPCR`
2850pub const DORD: *mut u8 = 0x20 as *mut u8;
2851
2852/// Bitfield on register `SPCR`
2853pub const SPE: *mut u8 = 0x40 as *mut u8;
2854
2855/// Bitfield on register `SPCR`
2856pub const CPHA: *mut u8 = 0x4 as *mut u8;
2857
2858/// Bitfield on register `SPCR`
2859pub const SPIE: *mut u8 = 0x80 as *mut u8;
2860
2861/// Bitfield on register `SPCR`
2862pub const MSTR: *mut u8 = 0x10 as *mut u8;
2863
2864/// Bitfield on register `SPCR`
2865pub const SPR: *mut u8 = 0x3 as *mut u8;
2866
2867/// Bitfield on register `SPCR`
2868pub const CPOL: *mut u8 = 0x8 as *mut u8;
2869
2870/// Bitfield on register `SPMCSR`
2871pub const SPMIE: *mut u8 = 0x80 as *mut u8;
2872
2873/// Bitfield on register `SPMCSR`
2874pub const BLBSET: *mut u8 = 0x8 as *mut u8;
2875
2876/// Bitfield on register `SPMCSR`
2877pub const SPMEN: *mut u8 = 0x1 as *mut u8;
2878
2879/// Bitfield on register `SPMCSR`
2880pub const RWWSRE: *mut u8 = 0x10 as *mut u8;
2881
2882/// Bitfield on register `SPMCSR`
2883pub const PGERS: *mut u8 = 0x2 as *mut u8;
2884
2885/// Bitfield on register `SPMCSR`
2886pub const RWWSB: *mut u8 = 0x40 as *mut u8;
2887
2888/// Bitfield on register `SPMCSR`
2889pub const PGWRT: *mut u8 = 0x4 as *mut u8;
2890
2891/// Bitfield on register `SPMCSR`
2892pub const SIGRD: *mut u8 = 0x20 as *mut u8;
2893
2894/// Bitfield on register `SPSR`
2895pub const SPI2X: *mut u8 = 0x1 as *mut u8;
2896
2897/// Bitfield on register `SPSR`
2898pub const WCOL: *mut u8 = 0x40 as *mut u8;
2899
2900/// Bitfield on register `SPSR`
2901pub const SPIF: *mut u8 = 0x80 as *mut u8;
2902
2903/// Bitfield on register `SREG`
2904pub const C: *mut u8 = 0x1 as *mut u8;
2905
2906/// Bitfield on register `SREG`
2907pub const H: *mut u8 = 0x20 as *mut u8;
2908
2909/// Bitfield on register `SREG`
2910pub const S: *mut u8 = 0x10 as *mut u8;
2911
2912/// Bitfield on register `SREG`
2913pub const I: *mut u8 = 0x80 as *mut u8;
2914
2915/// Bitfield on register `SREG`
2916pub const V: *mut u8 = 0x8 as *mut u8;
2917
2918/// Bitfield on register `SREG`
2919pub const N: *mut u8 = 0x4 as *mut u8;
2920
2921/// Bitfield on register `SREG`
2922pub const Z: *mut u8 = 0x2 as *mut u8;
2923
2924/// Bitfield on register `SREG`
2925pub const T: *mut u8 = 0x40 as *mut u8;
2926
2927/// Bitfield on register `TCCR0A`
2928pub const COM0B: *mut u8 = 0x30 as *mut u8;
2929
2930/// Bitfield on register `TCCR0A`
2931pub const COM0A: *mut u8 = 0xC0 as *mut u8;
2932
2933/// Bitfield on register `TCCR0A`
2934pub const WGM0: *mut u8 = 0x3 as *mut u8;
2935
2936/// Bitfield on register `TCCR0B`
2937pub const WGM02: *mut u8 = 0x8 as *mut u8;
2938
2939/// Bitfield on register `TCCR0B`
2940pub const FOC0B: *mut u8 = 0x40 as *mut u8;
2941
2942/// Bitfield on register `TCCR0B`
2943pub const CS0: *mut u8 = 0x7 as *mut u8;
2944
2945/// Bitfield on register `TCCR0B`
2946pub const FOC0A: *mut u8 = 0x80 as *mut u8;
2947
2948/// Bitfield on register `TCCR1A`
2949pub const COM1C: *mut u8 = 0xC as *mut u8;
2950
2951/// Bitfield on register `TCCR1A`
2952pub const COM1A: *mut u8 = 0xC0 as *mut u8;
2953
2954/// Bitfield on register `TCCR1A`
2955pub const COM1B: *mut u8 = 0x30 as *mut u8;
2956
2957/// Bitfield on register `TCCR1B`
2958pub const ICNC1: *mut u8 = 0x80 as *mut u8;
2959
2960/// Bitfield on register `TCCR1B`
2961pub const CS1: *mut u8 = 0x7 as *mut u8;
2962
2963/// Bitfield on register `TCCR1B`
2964pub const ICES1: *mut u8 = 0x40 as *mut u8;
2965
2966/// Bitfield on register `TCCR1C`
2967pub const FOC1B: *mut u8 = 0x40 as *mut u8;
2968
2969/// Bitfield on register `TCCR1C`
2970pub const FOC1C: *mut u8 = 0x20 as *mut u8;
2971
2972/// Bitfield on register `TCCR1C`
2973pub const FOC1A: *mut u8 = 0x80 as *mut u8;
2974
2975/// Bitfield on register `TCCR2A`
2976pub const COM2B: *mut u8 = 0x30 as *mut u8;
2977
2978/// Bitfield on register `TCCR2A`
2979pub const WGM2: *mut u8 = 0x3 as *mut u8;
2980
2981/// Bitfield on register `TCCR2A`
2982pub const COM2A: *mut u8 = 0xC0 as *mut u8;
2983
2984/// Bitfield on register `TCCR2B`
2985pub const CS2: *mut u8 = 0x7 as *mut u8;
2986
2987/// Bitfield on register `TCCR2B`
2988pub const FOC2A: *mut u8 = 0x80 as *mut u8;
2989
2990/// Bitfield on register `TCCR2B`
2991pub const WGM22: *mut u8 = 0x8 as *mut u8;
2992
2993/// Bitfield on register `TCCR2B`
2994pub const FOC2B: *mut u8 = 0x40 as *mut u8;
2995
2996/// Bitfield on register `TCCR3A`
2997pub const COM3B: *mut u8 = 0x30 as *mut u8;
2998
2999/// Bitfield on register `TCCR3A`
3000pub const COM3C: *mut u8 = 0xC as *mut u8;
3001
3002/// Bitfield on register `TCCR3A`
3003pub const COM3A: *mut u8 = 0xC0 as *mut u8;
3004
3005/// Bitfield on register `TCCR3B`
3006pub const ICNC3: *mut u8 = 0x80 as *mut u8;
3007
3008/// Bitfield on register `TCCR3B`
3009pub const CS3: *mut u8 = 0x7 as *mut u8;
3010
3011/// Bitfield on register `TCCR3B`
3012pub const ICES3: *mut u8 = 0x40 as *mut u8;
3013
3014/// Bitfield on register `TCCR3C`
3015pub const FOC3C: *mut u8 = 0x20 as *mut u8;
3016
3017/// Bitfield on register `TCCR3C`
3018pub const FOC3B: *mut u8 = 0x40 as *mut u8;
3019
3020/// Bitfield on register `TCCR3C`
3021pub const FOC3A: *mut u8 = 0x80 as *mut u8;
3022
3023/// Bitfield on register `TCCR4A`
3024pub const COM4C: *mut u8 = 0xC as *mut u8;
3025
3026/// Bitfield on register `TCCR4A`
3027pub const COM4A: *mut u8 = 0xC0 as *mut u8;
3028
3029/// Bitfield on register `TCCR4A`
3030pub const COM4B: *mut u8 = 0x30 as *mut u8;
3031
3032/// Bitfield on register `TCCR4B`
3033pub const CS4: *mut u8 = 0x7 as *mut u8;
3034
3035/// Bitfield on register `TCCR4B`
3036pub const ICES4: *mut u8 = 0x40 as *mut u8;
3037
3038/// Bitfield on register `TCCR4B`
3039pub const ICNC4: *mut u8 = 0x80 as *mut u8;
3040
3041/// Bitfield on register `TCCR4C`
3042pub const FOC4A: *mut u8 = 0x80 as *mut u8;
3043
3044/// Bitfield on register `TCCR4C`
3045pub const FOC4B: *mut u8 = 0x40 as *mut u8;
3046
3047/// Bitfield on register `TCCR4C`
3048pub const FOC4C: *mut u8 = 0x20 as *mut u8;
3049
3050/// Bitfield on register `TCCR5A`
3051pub const COM5C: *mut u8 = 0xC as *mut u8;
3052
3053/// Bitfield on register `TCCR5A`
3054pub const COM5A: *mut u8 = 0xC0 as *mut u8;
3055
3056/// Bitfield on register `TCCR5A`
3057pub const COM5B: *mut u8 = 0x30 as *mut u8;
3058
3059/// Bitfield on register `TCCR5B`
3060pub const CS5: *mut u8 = 0x7 as *mut u8;
3061
3062/// Bitfield on register `TCCR5B`
3063pub const ICNC5: *mut u8 = 0x80 as *mut u8;
3064
3065/// Bitfield on register `TCCR5B`
3066pub const ICES5: *mut u8 = 0x40 as *mut u8;
3067
3068/// Bitfield on register `TCCR5C`
3069pub const FOC5A: *mut u8 = 0x80 as *mut u8;
3070
3071/// Bitfield on register `TCCR5C`
3072pub const FOC5B: *mut u8 = 0x40 as *mut u8;
3073
3074/// Bitfield on register `TCCR5C`
3075pub const FOC5C: *mut u8 = 0x20 as *mut u8;
3076
3077/// Bitfield on register `TIFR0`
3078pub const OCF0B: *mut u8 = 0x4 as *mut u8;
3079
3080/// Bitfield on register `TIFR0`
3081pub const OCF0A: *mut u8 = 0x2 as *mut u8;
3082
3083/// Bitfield on register `TIFR0`
3084pub const TOV0: *mut u8 = 0x1 as *mut u8;
3085
3086/// Bitfield on register `TIFR1`
3087pub const TOV1: *mut u8 = 0x1 as *mut u8;
3088
3089/// Bitfield on register `TIFR1`
3090pub const OCF1A: *mut u8 = 0x2 as *mut u8;
3091
3092/// Bitfield on register `TIFR1`
3093pub const OCF1B: *mut u8 = 0x4 as *mut u8;
3094
3095/// Bitfield on register `TIFR1`
3096pub const OCF1C: *mut u8 = 0x8 as *mut u8;
3097
3098/// Bitfield on register `TIFR1`
3099pub const ICF1: *mut u8 = 0x20 as *mut u8;
3100
3101/// Bitfield on register `TIFR2`
3102pub const OCF2B: *mut u8 = 0x4 as *mut u8;
3103
3104/// Bitfield on register `TIFR2`
3105pub const OCF2A: *mut u8 = 0x2 as *mut u8;
3106
3107/// Bitfield on register `TIFR2`
3108pub const TOV2: *mut u8 = 0x1 as *mut u8;
3109
3110/// Bitfield on register `TIFR3`
3111pub const OCF3C: *mut u8 = 0x8 as *mut u8;
3112
3113/// Bitfield on register `TIFR3`
3114pub const ICF3: *mut u8 = 0x20 as *mut u8;
3115
3116/// Bitfield on register `TIFR3`
3117pub const TOV3: *mut u8 = 0x1 as *mut u8;
3118
3119/// Bitfield on register `TIFR3`
3120pub const OCF3A: *mut u8 = 0x2 as *mut u8;
3121
3122/// Bitfield on register `TIFR3`
3123pub const OCF3B: *mut u8 = 0x4 as *mut u8;
3124
3125/// Bitfield on register `TIFR4`
3126pub const ICF4: *mut u8 = 0x20 as *mut u8;
3127
3128/// Bitfield on register `TIFR4`
3129pub const OCF4A: *mut u8 = 0x2 as *mut u8;
3130
3131/// Bitfield on register `TIFR4`
3132pub const TOV4: *mut u8 = 0x1 as *mut u8;
3133
3134/// Bitfield on register `TIFR4`
3135pub const OCF4B: *mut u8 = 0x4 as *mut u8;
3136
3137/// Bitfield on register `TIFR4`
3138pub const OCF4C: *mut u8 = 0x8 as *mut u8;
3139
3140/// Bitfield on register `TIFR5`
3141pub const ICF5: *mut u8 = 0x20 as *mut u8;
3142
3143/// Bitfield on register `TIFR5`
3144pub const TOV5: *mut u8 = 0x1 as *mut u8;
3145
3146/// Bitfield on register `TIFR5`
3147pub const OCF5A: *mut u8 = 0x2 as *mut u8;
3148
3149/// Bitfield on register `TIFR5`
3150pub const OCF5B: *mut u8 = 0x4 as *mut u8;
3151
3152/// Bitfield on register `TIFR5`
3153pub const OCF5C: *mut u8 = 0x8 as *mut u8;
3154
3155/// Bitfield on register `TIMSK0`
3156pub const OCIE0A: *mut u8 = 0x2 as *mut u8;
3157
3158/// Bitfield on register `TIMSK0`
3159pub const TOIE0: *mut u8 = 0x1 as *mut u8;
3160
3161/// Bitfield on register `TIMSK0`
3162pub const OCIE0B: *mut u8 = 0x4 as *mut u8;
3163
3164/// Bitfield on register `TIMSK1`
3165pub const OCIE1C: *mut u8 = 0x8 as *mut u8;
3166
3167/// Bitfield on register `TIMSK1`
3168pub const OCIE1A: *mut u8 = 0x2 as *mut u8;
3169
3170/// Bitfield on register `TIMSK1`
3171pub const TOIE1: *mut u8 = 0x1 as *mut u8;
3172
3173/// Bitfield on register `TIMSK1`
3174pub const ICIE1: *mut u8 = 0x20 as *mut u8;
3175
3176/// Bitfield on register `TIMSK1`
3177pub const OCIE1B: *mut u8 = 0x4 as *mut u8;
3178
3179/// Bitfield on register `TIMSK2`
3180pub const TOIE2: *mut u8 = 0x1 as *mut u8;
3181
3182/// Bitfield on register `TIMSK2`
3183pub const OCIE2B: *mut u8 = 0x4 as *mut u8;
3184
3185/// Bitfield on register `TIMSK2`
3186pub const OCIE2A: *mut u8 = 0x2 as *mut u8;
3187
3188/// Bitfield on register `TIMSK3`
3189pub const ICIE3: *mut u8 = 0x20 as *mut u8;
3190
3191/// Bitfield on register `TIMSK3`
3192pub const OCIE3C: *mut u8 = 0x8 as *mut u8;
3193
3194/// Bitfield on register `TIMSK3`
3195pub const OCIE3B: *mut u8 = 0x4 as *mut u8;
3196
3197/// Bitfield on register `TIMSK3`
3198pub const OCIE3A: *mut u8 = 0x2 as *mut u8;
3199
3200/// Bitfield on register `TIMSK3`
3201pub const TOIE3: *mut u8 = 0x1 as *mut u8;
3202
3203/// Bitfield on register `TIMSK4`
3204pub const OCIE4B: *mut u8 = 0x4 as *mut u8;
3205
3206/// Bitfield on register `TIMSK4`
3207pub const ICIE4: *mut u8 = 0x20 as *mut u8;
3208
3209/// Bitfield on register `TIMSK4`
3210pub const TOIE4: *mut u8 = 0x1 as *mut u8;
3211
3212/// Bitfield on register `TIMSK4`
3213pub const OCIE4A: *mut u8 = 0x2 as *mut u8;
3214
3215/// Bitfield on register `TIMSK4`
3216pub const OCIE4C: *mut u8 = 0x8 as *mut u8;
3217
3218/// Bitfield on register `TIMSK5`
3219pub const TOIE5: *mut u8 = 0x1 as *mut u8;
3220
3221/// Bitfield on register `TIMSK5`
3222pub const OCIE5A: *mut u8 = 0x2 as *mut u8;
3223
3224/// Bitfield on register `TIMSK5`
3225pub const OCIE5C: *mut u8 = 0x8 as *mut u8;
3226
3227/// Bitfield on register `TIMSK5`
3228pub const OCIE5B: *mut u8 = 0x4 as *mut u8;
3229
3230/// Bitfield on register `TIMSK5`
3231pub const ICIE5: *mut u8 = 0x20 as *mut u8;
3232
3233/// Bitfield on register `TRXPR`
3234pub const SLPTR: *mut u8 = 0x2 as *mut u8;
3235
3236/// Bitfield on register `TRXPR`
3237pub const TRXRST: *mut u8 = 0x1 as *mut u8;
3238
3239/// Bitfield on register `TRX_CTRL_0`
3240pub const PMU_IF_INV: *mut u8 = 0x10 as *mut u8;
3241
3242/// Bitfield on register `TRX_CTRL_0`
3243pub const PMU_START: *mut u8 = 0x20 as *mut u8;
3244
3245/// Bitfield on register `TRX_CTRL_0`
3246pub const PMU_EN: *mut u8 = 0x40 as *mut u8;
3247
3248/// Bitfield on register `TRX_CTRL_0`
3249pub const Res7: *mut u8 = 0x80 as *mut u8;
3250
3251/// Bitfield on register `TRX_CTRL_1`
3252pub const TX_AUTO_CRC_ON: *mut u8 = 0x20 as *mut u8;
3253
3254/// Bitfield on register `TRX_CTRL_1`
3255pub const PLL_TX_FLT: *mut u8 = 0x10 as *mut u8;
3256
3257/// Bitfield on register `TRX_CTRL_1`
3258pub const PA_EXT_EN: *mut u8 = 0x80 as *mut u8;
3259
3260/// Bitfield on register `TRX_CTRL_1`
3261pub const IRQ_2_EXT_EN: *mut u8 = 0x40 as *mut u8;
3262
3263/// Bitfield on register `TRX_CTRL_2`
3264pub const RX_SAFE_MODE: *mut u8 = 0x80 as *mut u8;
3265
3266/// Bitfield on register `TRX_CTRL_2`
3267pub const OQPSK_DATA_RATE: *mut u8 = 0x3 as *mut u8;
3268
3269/// Bitfield on register `TRX_RPC`
3270pub const PDT_RPC_EN: *mut u8 = 0x10 as *mut u8;
3271
3272/// Bitfield on register `TRX_RPC`
3273pub const IPAN_RPC_EN: *mut u8 = 0x2 as *mut u8;
3274
3275/// Bitfield on register `TRX_RPC`
3276pub const XAH_RPC_EN: *mut u8 = 0x1 as *mut u8;
3277
3278/// Bitfield on register `TRX_RPC`
3279pub const PLL_RPC_EN: *mut u8 = 0x8 as *mut u8;
3280
3281/// Bitfield on register `TRX_RPC`
3282pub const RX_RPC_EN: *mut u8 = 0x20 as *mut u8;
3283
3284/// Bitfield on register `TRX_RPC`
3285pub const RX_RPC_CTRL: *mut u8 = 0xC0 as *mut u8;
3286
3287/// Bitfield on register `TRX_STATE`
3288pub const TRAC_STATUS: *mut u8 = 0xE0 as *mut u8;
3289
3290/// Bitfield on register `TRX_STATE`
3291pub const TRX_CMD: *mut u8 = 0x1F as *mut u8;
3292
3293/// Bitfield on register `TRX_STATUS`
3294pub const CCA_DONE: *mut u8 = 0x80 as *mut u8;
3295
3296/// Bitfield on register `TRX_STATUS`
3297pub const CCA_STATUS: *mut u8 = 0x40 as *mut u8;
3298
3299/// Bitfield on register `TRX_STATUS`
3300pub const TST_STATUS: *mut u8 = 0x20 as *mut u8;
3301
3302/// Bitfield on register `TST_CTRL_DIGI`
3303pub const TST_CTRL_DIG: *mut u8 = 0xF as *mut u8;
3304
3305/// Bitfield on register `TWAMR`
3306pub const TWAM: *mut u8 = 0xFE as *mut u8;
3307
3308/// Bitfield on register `TWAR`
3309pub const TWA: *mut u8 = 0xFE as *mut u8;
3310
3311/// Bitfield on register `TWAR`
3312pub const TWGCE: *mut u8 = 0x1 as *mut u8;
3313
3314/// Bitfield on register `TWCR`
3315pub const TWIE: *mut u8 = 0x1 as *mut u8;
3316
3317/// Bitfield on register `TWCR`
3318pub const TWINT: *mut u8 = 0x80 as *mut u8;
3319
3320/// Bitfield on register `TWCR`
3321pub const TWWC: *mut u8 = 0x8 as *mut u8;
3322
3323/// Bitfield on register `TWCR`
3324pub const TWSTA: *mut u8 = 0x20 as *mut u8;
3325
3326/// Bitfield on register `TWCR`
3327pub const TWSTO: *mut u8 = 0x10 as *mut u8;
3328
3329/// Bitfield on register `TWCR`
3330pub const TWEN: *mut u8 = 0x4 as *mut u8;
3331
3332/// Bitfield on register `TWCR`
3333pub const TWEA: *mut u8 = 0x40 as *mut u8;
3334
3335/// Bitfield on register `TWSR`
3336pub const TWPS: *mut u8 = 0x3 as *mut u8;
3337
3338/// Bitfield on register `TWSR`
3339pub const TWS: *mut u8 = 0xF8 as *mut u8;
3340
3341/// Bitfield on register `UCSR0A`
3342pub const UDRE0: *mut u8 = 0x20 as *mut u8;
3343
3344/// Bitfield on register `UCSR0A`
3345pub const TXC0: *mut u8 = 0x40 as *mut u8;
3346
3347/// Bitfield on register `UCSR0A`
3348pub const RXC0: *mut u8 = 0x80 as *mut u8;
3349
3350/// Bitfield on register `UCSR0B`
3351pub const TXEN0: *mut u8 = 0x8 as *mut u8;
3352
3353/// Bitfield on register `UCSR0B`
3354pub const RXCIE0: *mut u8 = 0x80 as *mut u8;
3355
3356/// Bitfield on register `UCSR0B`
3357pub const TXCIE0: *mut u8 = 0x40 as *mut u8;
3358
3359/// Bitfield on register `UCSR0B`
3360pub const RXEN0: *mut u8 = 0x10 as *mut u8;
3361
3362/// Bitfield on register `UCSR0B`
3363pub const UDRIE0: *mut u8 = 0x20 as *mut u8;
3364
3365/// Bitfield on register `UCSR0C`
3366pub const UCPOL0: *mut u8 = 0x1 as *mut u8;
3367
3368/// Bitfield on register `UCSR0C`
3369pub const UCPHA0: *mut u8 = 0x2 as *mut u8;
3370
3371/// Bitfield on register `UCSR0C`
3372pub const UDORD0: *mut u8 = 0x4 as *mut u8;
3373
3374/// Bitfield on register `UCSR1A`
3375pub const UDRE1: *mut u8 = 0x20 as *mut u8;
3376
3377/// Bitfield on register `UCSR1A`
3378pub const TXC1: *mut u8 = 0x40 as *mut u8;
3379
3380/// Bitfield on register `UCSR1A`
3381pub const RXC1: *mut u8 = 0x80 as *mut u8;
3382
3383/// Bitfield on register `UCSR1B`
3384pub const UDRIE1: *mut u8 = 0x20 as *mut u8;
3385
3386/// Bitfield on register `UCSR1B`
3387pub const RXCIE1: *mut u8 = 0x80 as *mut u8;
3388
3389/// Bitfield on register `UCSR1B`
3390pub const TXCIE1: *mut u8 = 0x40 as *mut u8;
3391
3392/// Bitfield on register `UCSR1B`
3393pub const RXEN1: *mut u8 = 0x10 as *mut u8;
3394
3395/// Bitfield on register `UCSR1B`
3396pub const TXEN1: *mut u8 = 0x8 as *mut u8;
3397
3398/// Bitfield on register `UCSR1C`
3399pub const UCPOL1: *mut u8 = 0x1 as *mut u8;
3400
3401/// Bitfield on register `UCSR1C`
3402pub const UDORD1: *mut u8 = 0x4 as *mut u8;
3403
3404/// Bitfield on register `UCSR1C`
3405pub const UCPHA1: *mut u8 = 0x2 as *mut u8;
3406
3407/// Bitfield on register `VREG_CTRL`
3408pub const AVDD_OK: *mut u8 = 0x40 as *mut u8;
3409
3410/// Bitfield on register `VREG_CTRL`
3411pub const AVREG_EXT: *mut u8 = 0x80 as *mut u8;
3412
3413/// Bitfield on register `VREG_CTRL`
3414pub const DVDD_OK: *mut u8 = 0x4 as *mut u8;
3415
3416/// Bitfield on register `VREG_CTRL`
3417pub const DVREG_EXT: *mut u8 = 0x8 as *mut u8;
3418
3419/// Bitfield on register `WDTCSR`
3420pub const WDP: *mut u8 = 0x27 as *mut u8;
3421
3422/// Bitfield on register `WDTCSR`
3423pub const WDE: *mut u8 = 0x8 as *mut u8;
3424
3425/// Bitfield on register `WDTCSR`
3426pub const WDCE: *mut u8 = 0x10 as *mut u8;
3427
3428/// Bitfield on register `WDTCSR`
3429pub const WDIE: *mut u8 = 0x40 as *mut u8;
3430
3431/// Bitfield on register `WDTCSR`
3432pub const WDIF: *mut u8 = 0x80 as *mut u8;
3433
3434/// Bitfield on register `XAH_CTRL_0`
3435pub const SLOTTED_OPERATION: *mut u8 = 0x1 as *mut u8;
3436
3437/// Bitfield on register `XAH_CTRL_0`
3438pub const MAX_FRAME_RETRIES: *mut u8 = 0xF0 as *mut u8;
3439
3440/// Bitfield on register `XAH_CTRL_0`
3441pub const MAX_CSMA_RETRIES: *mut u8 = 0xE as *mut u8;
3442
3443/// Bitfield on register `XAH_CTRL_1`
3444pub const AACK_FLTR_RES_FT: *mut u8 = 0x20 as *mut u8;
3445
3446/// Bitfield on register `XAH_CTRL_1`
3447pub const AACK_PROM_MODE: *mut u8 = 0x2 as *mut u8;
3448
3449/// Bitfield on register `XAH_CTRL_1`
3450pub const AACK_ACK_TIME: *mut u8 = 0x4 as *mut u8;
3451
3452/// Bitfield on register `XAH_CTRL_1`
3453pub const AACK_UPLD_RES_FT: *mut u8 = 0x10 as *mut u8;
3454
3455/// Bitfield on register `XOSC_CTRL`
3456pub const XTAL_TRIM: *mut u8 = 0xF as *mut u8;
3457
3458/// Bitfield on register `XOSC_CTRL`
3459pub const XTAL_MODE: *mut u8 = 0xF0 as *mut u8;
3460
3461/// `AACK_ACK_TIME_bitf` value group
3462#[allow(non_upper_case_globals)]
3463pub mod aack_ack_time_bitf {
3464 /// 12 symbols acknowledgment time.
3465 pub const AACK_ACK_TIME_12_SYM: u32 = 0x0;
3466 /// 2 symbols acknowledgment time.
3467 pub const AACK_ACK_TIME_2_SYM: u32 = 0x1;
3468}
3469
3470/// `AACK_FVN_MODE_bitf` value group
3471#[allow(non_upper_case_globals)]
3472pub mod aack_fvn_mode_bitf {
3473 /// Acknowledge frames with version number 0.
3474 pub const VAL_0: u32 = 0x0;
3475 /// Acknowledge frames with version number 0 or 1.
3476 pub const VAL_1: u32 = 0x1;
3477 /// Acknowledge frames with version number 0 or 1 or 2.
3478 pub const VAL_2: u32 = 0x2;
3479 /// Acknowledge frames independent of frame version number.
3480 pub const VAL_3: u32 = 0x3;
3481}
3482
3483/// `AES_DIRECTION_BITF` value group
3484#[allow(non_upper_case_globals)]
3485pub mod aes_direction_bitf {
3486 /// AES operation is encryption.
3487 pub const AES_DIR_ENC: u32 = 0x0;
3488 /// AES operation is decryption.
3489 pub const AES_DIR_DEC: u32 = 0x1;
3490}
3491
3492/// `AES_MODE_BITF` value group
3493#[allow(non_upper_case_globals)]
3494pub mod aes_mode_bitf {
3495 /// AES Mode is ECB (Electronic Code Book).
3496 pub const AES_MODE_ECB: u32 = 0x0;
3497 /// AES Mode is CBC (Cipher Block Chaining).
3498 pub const AES_MODE_CBC: u32 = 0x1;
3499}
3500
3501/// `ANALOG_ADC_AUTO_TRIGGER` value group
3502#[allow(non_upper_case_globals)]
3503pub mod analog_adc_auto_trigger {
3504 /// Free Running mode.
3505 pub const VAL_0x00: u32 = 0x0;
3506 /// Analog Comparator.
3507 pub const VAL_0x01: u32 = 0x1;
3508 /// External Interrupt Request 0.
3509 pub const VAL_0x02: u32 = 0x2;
3510 /// Timer/Counter0 Compare Match A.
3511 pub const VAL_0x03: u32 = 0x3;
3512 /// Timer/Counter0 Overflow.
3513 pub const VAL_0x04: u32 = 0x4;
3514 /// Timer/Counter1 Compare Match B.
3515 pub const VAL_0x05: u32 = 0x5;
3516 /// Timer/Counter1 Overflow.
3517 pub const VAL_0x06: u32 = 0x6;
3518 /// Timer/Counter1 Capture Event.
3519 pub const VAL_0x07: u32 = 0x7;
3520}
3521
3522/// `ANALOG_ADC_PRESCALER` value group
3523#[allow(non_upper_case_globals)]
3524pub mod analog_adc_prescaler {
3525 /// 2.
3526 pub const VAL_0x00: u32 = 0x0;
3527 /// 2.
3528 pub const VAL_0x01: u32 = 0x1;
3529 /// 4.
3530 pub const VAL_0x02: u32 = 0x2;
3531 /// 8.
3532 pub const VAL_0x03: u32 = 0x3;
3533 /// 16.
3534 pub const VAL_0x04: u32 = 0x4;
3535 /// 32.
3536 pub const VAL_0x05: u32 = 0x5;
3537 /// 64.
3538 pub const VAL_0x06: u32 = 0x6;
3539 /// 128.
3540 pub const VAL_0x07: u32 = 0x7;
3541}
3542
3543/// `ANALOG_ADC_STARTUP_TIME` value group
3544#[allow(non_upper_case_globals)]
3545pub mod analog_adc_startup_time {
3546 /// 3 ADC clock cycles.
3547 pub const VAL_0x00: u32 = 0x0;
3548 /// 7 ADC clock cycles.
3549 pub const VAL_0x01: u32 = 0x1;
3550 /// 11 ADC clock cycles.
3551 pub const VAL_0x02: u32 = 0x2;
3552 /// 15 ADC clock cycles.
3553 pub const VAL_0x03: u32 = 0x3;
3554 /// ...
3555 pub const VAL_0x04: u32 = 0x4;
3556 /// 251 ADC clock cycles.
3557 pub const VAL_0x3E: u32 = 0x3E;
3558 /// 255 ADC clock cycles.
3559 pub const VAL_0x3F: u32 = 0x3F;
3560}
3561
3562/// `ANALOG_ADC_TRACK_AND_HOLD_TIME` value group
3563#[allow(non_upper_case_globals)]
3564pub mod analog_adc_track_and_hold_time {
3565 /// Single ended: 1, differential 3 ADC clock cycles.
3566 pub const VAL_0x00: u32 = 0x0;
3567 /// Single ended: 2, differential 5 ADC clock cycles.
3568 pub const VAL_0x01: u32 = 0x1;
3569 /// Single ended: 3, differential 7 ADC clock cycles.
3570 pub const VAL_0x02: u32 = 0x2;
3571 /// Single ended: 4, differential 9 ADC clock cycles.
3572 pub const VAL_0x03: u32 = 0x3;
3573}
3574
3575/// `ANALOG_ADC_V_REF9` value group
3576#[allow(non_upper_case_globals)]
3577pub mod analog_adc_v_ref9 {
3578 /// AREF, Internal reference voltage generation turned off.
3579 pub const VAL_0x00: u32 = 0x0;
3580 /// AVDD with external capacitor at AREF pin.
3581 pub const VAL_0x01: u32 = 0x1;
3582 /// Internal 1.5V Voltage Reference (no external capacitor at AREF pin).
3583 pub const VAL_0x02: u32 = 0x2;
3584 /// Internal 1.6V Voltage Reference (no external capacitor at AREF pin).
3585 pub const VAL_0x03: u32 = 0x3;
3586}
3587
3588/// `ANALOG_COMP_INTERRUPT` value group
3589#[allow(non_upper_case_globals)]
3590pub mod analog_comp_interrupt {
3591 /// Interrupt on Toggle.
3592 pub const VAL_0x00: u32 = 0x0;
3593 /// Reserved.
3594 pub const VAL_0x01: u32 = 0x1;
3595 /// Interrupt on Falling Edge.
3596 pub const VAL_0x02: u32 = 0x2;
3597 /// Interrupt on Rising Edge.
3598 pub const VAL_0x03: u32 = 0x3;
3599}
3600
3601/// `ANT_CTRL_bitf` value group
3602#[allow(non_upper_case_globals)]
3603pub mod ant_ctrl_bitf {
3604 /// Reserved.
3605 pub const VAL_0: u32 = 0x0;
3606 /// Antenna 1: DIG1=H, DIG2=L.
3607 pub const ANT_1: u32 = 0x1;
3608 /// Antenna 0: DIG1=L, DIG2=H.
3609 pub const ANT_0: u32 = 0x2;
3610 /// Default value for ANT_EXT_SW_EN=0; Mandatory setting for applications not using Antenna Diversity.
3611 pub const ANT_RESET: u32 = 0x3;
3612}
3613
3614/// `ANT_DIV_EN_bitf` value group
3615#[allow(non_upper_case_globals)]
3616pub mod ant_div_en_bitf {
3617 /// Antenna Diversity algorithm disabled.
3618 pub const VAL_0: u32 = 0x0;
3619 /// Antenna Diversity algorithm enabled.
3620 pub const VAL_1: u32 = 0x1;
3621}
3622
3623/// `ANT_EXT_SW_EN_bitf` value group
3624#[allow(non_upper_case_globals)]
3625pub mod ant_ext_sw_en_bitf {
3626 /// Antenna Diversity RF switch control disabled.
3627 pub const ANT_DIV_EXT_SW_DIS: u32 = 0x0;
3628 /// Antenna Diversity RF switch control enabled.
3629 pub const ANT_DIV_EXT_SW_EN: u32 = 0x1;
3630}
3631
3632/// `ANT_SEL_bitf` value group
3633#[allow(non_upper_case_globals)]
3634pub mod ant_sel_bitf {
3635 /// Antenna 0.
3636 pub const ANTENNA_0: u32 = 0x0;
3637 /// Antenna 1.
3638 pub const ANTENNA_1: u32 = 0x1;
3639}
3640
3641/// `AVDD_OK_BITF` value group
3642#[allow(non_upper_case_globals)]
3643pub mod avdd_ok_bitf {
3644 /// Analog voltage regulator disabled or supply voltage not stable.
3645 pub const VAL_0: u32 = 0x0;
3646 /// Analog supply voltage has settled.
3647 pub const VAL_1: u32 = 0x1;
3648}
3649
3650/// `AVREG_EXT_BITF` value group
3651#[allow(non_upper_case_globals)]
3652pub mod avreg_ext_bitf {
3653 /// Internal AVDD voltage regulator for the analog section is enabled.
3654 pub const AVDD_INT: u32 = 0x0;
3655 /// Internal AVDD voltage regulator is disabled; use external regulated 1.8V supply voltage for the analog section.
3656 pub const AVDD_EXT: u32 = 0x1;
3657}
3658
3659/// `BATMON_HR_bitf` value group
3660#[allow(non_upper_case_globals)]
3661pub mod batmon_hr_bitf {
3662 /// Enables the low range, see BATMON_VTH.
3663 pub const BATMON_HR_DIS: u32 = 0x0;
3664 /// Enables the high range, see BATMON_VTH.
3665 pub const BATMON_HR_EN: u32 = 0x1;
3666}
3667
3668/// `BATMON_OK_bitf` value group
3669#[allow(non_upper_case_globals)]
3670pub mod batmon_ok_bitf {
3671 /// The battery voltage is below the threshold.
3672 pub const VAL_0: u32 = 0x0;
3673 /// The battery voltage is above the threshold.
3674 pub const VAL_1: u32 = 0x1;
3675}
3676
3677/// `BATMON_VTH_bitf` value group
3678#[allow(non_upper_case_globals)]
3679pub mod batmon_vth_bitf {
3680 /// 2.550V / 1.70V (BATMON_HR=1/0).
3681 pub const VAL_0x0: u32 = 0x0;
3682 /// 2.625V / 1.75V (BATMON_HR=1/0).
3683 pub const VAL_0x1: u32 = 0x1;
3684 /// 2.700V / 1.80V (BATMON_HR=1/0).
3685 pub const VAL_0x2: u32 = 0x2;
3686 /// 2.775V / 1.85V (BATMON_HR=1/0).
3687 pub const VAL_0x3: u32 = 0x3;
3688 /// 2.850V / 1.90V (BATMON_HR=1/0).
3689 pub const VAL_0x4: u32 = 0x4;
3690 /// 2.925V / 1.95V (BATMON_HR=1/0).
3691 pub const VAL_0x5: u32 = 0x5;
3692 /// 3.000V / 2.00V (BATMON_HR=1/0).
3693 pub const VAL_0x6: u32 = 0x6;
3694 /// 3.075V / 2.05V (BATMON_HR=1/0).
3695 pub const VAL_0x7: u32 = 0x7;
3696 /// 3.150V / 2.10V (BATMON_HR=1/0).
3697 pub const VAL_0x8: u32 = 0x8;
3698 /// 3.225V / 2.15V (BATMON_HR=1/0).
3699 pub const VAL_0x9: u32 = 0x9;
3700 /// 3.300V / 2.20V (BATMON_HR=1/0).
3701 pub const VAL_0xA: u32 = 0xA;
3702 /// 3.375V / 2.25V (BATMON_HR=1/0).
3703 pub const VAL_0xB: u32 = 0xB;
3704 /// 3.450V / 2.30V (BATMON_HR=1/0).
3705 pub const VAL_0xC: u32 = 0xC;
3706 /// 3.525V / 2.35V (BATMON_HR=1/0).
3707 pub const VAL_0xD: u32 = 0xD;
3708 /// 3.600V / 2.40V (BATMON_HR=1/0).
3709 pub const VAL_0xE: u32 = 0xE;
3710 /// 3.675V / 2.45V (BATMON_HR=1/0).
3711 pub const VAL_0xF: u32 = 0xF;
3712}
3713
3714/// `BGCAL_BITF` value group
3715#[allow(non_upper_case_globals)]
3716pub mod bgcal_bitf {
3717 /// Center value.
3718 pub const VAL_4: u32 = 0x4;
3719 /// Voltage step up.
3720 pub const VAL_3: u32 = 0x3;
3721 /// Voltage step down.
3722 pub const VAL_5: u32 = 0x5;
3723 /// Setting for highest voltage.
3724 pub const VAL_0: u32 = 0x0;
3725 /// Setting for lowest voltage.
3726 pub const VAL_7: u32 = 0x7;
3727}
3728
3729/// `BGCAL_FINE_BITF` value group
3730#[allow(non_upper_case_globals)]
3731pub mod bgcal_fine_bitf {
3732 /// Center value.
3733 pub const VAL_0: u32 = 0x0;
3734 /// Voltage step up.
3735 pub const VAL_1: u32 = 0x1;
3736 /// Voltage step down.
3737 pub const VAL_8: u32 = 0x8;
3738 /// Setting for highest voltage.
3739 pub const VAL_7: u32 = 0x7;
3740 /// Setting for lowest voltage.
3741 pub const VAL_15: u32 = 0xF;
3742}
3743
3744/// `CCA_DONE_bitf` value group
3745#[allow(non_upper_case_globals)]
3746pub mod cca_done_bitf {
3747 /// CCA calculation not finished.
3748 pub const CCA_NOT_FIN: u32 = 0x0;
3749 /// CCA calculation finished.
3750 pub const CCA_FIN: u32 = 0x1;
3751}
3752
3753/// `CCA_MODE_bitf` value group
3754#[allow(non_upper_case_globals)]
3755pub mod cca_mode_bitf {
3756 /// Mode 3a, Carrier sense OR energy above threshold.
3757 pub const CCA_CS_OR_ED: u32 = 0x0;
3758 /// Mode 1, Energy above threshold.
3759 pub const CCA_ED: u32 = 0x1;
3760 /// Mode 2, Carrier sense only.
3761 pub const CCA_CS: u32 = 0x2;
3762 /// Mode 3b, Carrier sense AND energy above threshold.
3763 pub const CCA_CS_AND_ED: u32 = 0x3;
3764}
3765
3766/// `CCA_STATUS_bitf` value group
3767#[allow(non_upper_case_globals)]
3768pub mod cca_status_bitf {
3769 /// Channel indicated as busy.
3770 pub const CCA_BUSY: u32 = 0x0;
3771 /// Channel indicated as idle.
3772 pub const CCA_IDLE: u32 = 0x1;
3773}
3774
3775/// `CHANNEL_bitf` value group
3776#[allow(non_upper_case_globals)]
3777pub mod channel_bitf {
3778 /// 2405 MHz.
3779 pub const F_2405MHZ: u32 = 0xB;
3780 /// 2410 MHz.
3781 pub const F_2410MHZ: u32 = 0xC;
3782 /// 2415 MHz.
3783 pub const F_2415MHZ: u32 = 0xD;
3784 /// 2420 MHz.
3785 pub const F_2420MHZ: u32 = 0xE;
3786 /// 2425 MHz.
3787 pub const F_2425MHZ: u32 = 0xF;
3788 /// 2430 MHz.
3789 pub const F_2430MHZ: u32 = 0x10;
3790 /// 2435 MHz.
3791 pub const F_2435MHZ: u32 = 0x11;
3792 /// 2440 MHz.
3793 pub const F_2440MHZ: u32 = 0x12;
3794 /// 2445 MHz.
3795 pub const F_2445MHZ: u32 = 0x13;
3796 /// 2450 MHz.
3797 pub const F_2450MHZ: u32 = 0x14;
3798 /// 2455 MHz.
3799 pub const F_2455MHZ: u32 = 0x15;
3800 /// 2460 MHz.
3801 pub const F_2460MHZ: u32 = 0x16;
3802 /// 2465 MHz.
3803 pub const F_2465MHZ: u32 = 0x17;
3804 /// 2470 MHz.
3805 pub const F_2470MHZ: u32 = 0x18;
3806 /// 2475 MHz.
3807 pub const F_2475MHZ: u32 = 0x19;
3808 /// 2480 MHz.
3809 pub const F_2480MHZ: u32 = 0x1A;
3810}
3811
3812/// `CLK_SEL_3BIT_EXT_MEGARF` value group
3813#[allow(non_upper_case_globals)]
3814pub mod clk_sel_3bit_ext_megarf {
3815 /// No clock source (Timer/Counter stopped).
3816 pub const VAL_0x00: u32 = 0x0;
3817 /// clk_IO/1 (no prescaling).
3818 pub const VAL_0x01: u32 = 0x1;
3819 /// clk_IO/8 (from prescaler).
3820 pub const VAL_0x02: u32 = 0x2;
3821 /// clk_IO/64 (from prescaler).
3822 pub const VAL_0x03: u32 = 0x3;
3823 /// clk_IO/256 (from prescaler).
3824 pub const VAL_0x04: u32 = 0x4;
3825 /// clk_IO/1024 (from prescaler).
3826 pub const VAL_0x05: u32 = 0x5;
3827 /// External clock source on Tn pin, clock on falling edge.
3828 pub const VAL_0x06: u32 = 0x6;
3829 /// External clock source on Tn pin, clock on rising edge.
3830 pub const VAL_0x07: u32 = 0x7;
3831}
3832
3833/// `CLK_SEL_3BIT_NOEXT_MEGARF` value group
3834#[allow(non_upper_case_globals)]
3835pub mod clk_sel_3bit_noext_megarf {
3836 /// No clock source (Timer/Counter stopped).
3837 pub const VAL_0x00: u32 = 0x0;
3838 /// clk_IO/1 (no prescaling).
3839 pub const VAL_0x01: u32 = 0x1;
3840 /// clk_IO/8 (from prescaler).
3841 pub const VAL_0x02: u32 = 0x2;
3842 /// clk_IO/64 (from prescaler).
3843 pub const VAL_0x03: u32 = 0x3;
3844 /// clk_IO/256 (from prescaler).
3845 pub const VAL_0x04: u32 = 0x4;
3846 /// clk_IO/1024 (from prescaler).
3847 pub const VAL_0x05: u32 = 0x5;
3848 /// Reserved.
3849 pub const VAL_0x06: u32 = 0x6;
3850 /// Reserved.
3851 pub const VAL_0x07: u32 = 0x7;
3852}
3853
3854/// `COMM_SCK_RATE_SPI2X` value group
3855#[allow(non_upper_case_globals)]
3856pub mod comm_sck_rate_spi2x {
3857 /// fosc/4 / fosc/2 (SPI2X=0/1).
3858 pub const VAL_0x00: u32 = 0x0;
3859 /// fosc/16 / fosc/8 (SPI2X=0/1).
3860 pub const VAL_0x01: u32 = 0x1;
3861 /// fosc/64 / fosc/32 (SPI2X=0/1).
3862 pub const VAL_0x02: u32 = 0x2;
3863 /// fosc/128 / fosc/64 (SPI2X=0/1).
3864 pub const VAL_0x03: u32 = 0x3;
3865}
3866
3867/// `COMM_STOP_BIT_SEL` value group
3868#[allow(non_upper_case_globals)]
3869pub mod comm_stop_bit_sel {
3870 /// 1-bit.
3871 pub const VAL_0x00: u32 = 0x0;
3872 /// 2-bit.
3873 pub const VAL_0x01: u32 = 0x1;
3874}
3875
3876/// `COMM_TWI_PRESACLE` value group
3877#[allow(non_upper_case_globals)]
3878pub mod comm_twi_presacle {
3879 /// 1.
3880 pub const VAL_0x00: u32 = 0x0;
3881 /// 4.
3882 pub const VAL_0x01: u32 = 0x1;
3883 /// 16.
3884 pub const VAL_0x02: u32 = 0x2;
3885 /// 64.
3886 pub const VAL_0x03: u32 = 0x3;
3887}
3888
3889/// `COMM_UPM_PARITY_MODE` value group
3890#[allow(non_upper_case_globals)]
3891pub mod comm_upm_parity_mode {
3892 /// Disabled.
3893 pub const VAL_0x00: u32 = 0x0;
3894 /// Reserved.
3895 pub const VAL_0x01: u32 = 0x1;
3896 /// Enabled, Even Parity.
3897 pub const VAL_0x02: u32 = 0x2;
3898 /// Enabled, Odd Parity.
3899 pub const VAL_0x03: u32 = 0x3;
3900}
3901
3902/// `COMM_USART_MODE_2BIT_MEGARF` value group
3903#[allow(non_upper_case_globals)]
3904pub mod comm_usart_mode_2bit_megarf {
3905 /// Asynchronous USART.
3906 pub const VAL_0x00: u32 = 0x0;
3907 /// Synchronous USART.
3908 pub const VAL_0x01: u32 = 0x1;
3909 /// Reserved.
3910 pub const VAL_0x02: u32 = 0x2;
3911 /// Master SPI (MSPIM).
3912 pub const VAL_0x03: u32 = 0x3;
3913}
3914
3915/// `CPU_CLK_PRESCALE_4_BITS_SMALL_MEGARF` value group
3916#[allow(non_upper_case_globals)]
3917pub mod cpu_clk_prescale_4_bits_small_megarf {
3918 /// Division factor 1 / RC-Oscillator 2.
3919 pub const VAL_0x0: u32 = 0x0;
3920 /// Division factor 2 / RC-Oscillator 4.
3921 pub const VAL_0x1: u32 = 0x1;
3922 /// Division factor 4 / RC-Oscillator 8.
3923 pub const VAL_0x2: u32 = 0x2;
3924 /// Division factor 8 / RC-Oscillator 16.
3925 pub const VAL_0x3: u32 = 0x3;
3926 /// Division factor 16 / RC-Oscillator 32.
3927 pub const VAL_0x4: u32 = 0x4;
3928 /// Division factor 32 / RC-Oscillator 64.
3929 pub const VAL_0x5: u32 = 0x5;
3930 /// Division factor 64 / RC-Oscillator 128.
3931 pub const VAL_0x6: u32 = 0x6;
3932 /// Division factor 128 / RC-Oscillator 256.
3933 pub const VAL_0x7: u32 = 0x7;
3934 /// Division factor 256 / RC-Oscillator 512.
3935 pub const VAL_0x8: u32 = 0x8;
3936 /// Reserved.
3937 pub const VAL_0x9: u32 = 0x9;
3938 /// Reserved.
3939 pub const VAL_0xA: u32 = 0xA;
3940 /// Reserved.
3941 pub const VAL_0xB: u32 = 0xB;
3942 /// Reserved.
3943 pub const VAL_0xC: u32 = 0xC;
3944 /// Reserved.
3945 pub const VAL_0xD: u32 = 0xD;
3946 /// Reserved.
3947 pub const VAL_0xE: u32 = 0xE;
3948 /// Division factor 1 only permitted for RC-Oscillator. Flash and EEPROM programming is not allowed.
3949 pub const VAL_0xF: u32 = 0xF;
3950}
3951
3952/// `CPU_SLEEP_MODE_3BITS` value group
3953#[allow(non_upper_case_globals)]
3954pub mod cpu_sleep_mode_3bits {
3955 /// Idle.
3956 pub const IDLE: u32 = 0x0;
3957 /// ADC Noise Reduction (If Available).
3958 pub const ADC: u32 = 0x1;
3959 /// Power Down.
3960 pub const PDOWN: u32 = 0x2;
3961 /// Power Save.
3962 pub const PSAVE: u32 = 0x3;
3963 /// Reserved.
3964 pub const VAL_0x04: u32 = 0x4;
3965 /// Reserved.
3966 pub const VAL_0x05: u32 = 0x5;
3967 /// Standby.
3968 pub const STDBY: u32 = 0x6;
3969 /// Extended Standby.
3970 pub const ESTDBY: u32 = 0x7;
3971}
3972
3973/// `DVDD_OK_BITF` value group
3974#[allow(non_upper_case_globals)]
3975pub mod dvdd_ok_bitf {
3976 /// Digital voltage regulator disabled or supply voltage not stable.
3977 pub const VAL_0: u32 = 0x0;
3978 /// Digital supply voltage has settled.
3979 pub const VAL_1: u32 = 0x1;
3980}
3981
3982/// `DVREG_EXT_BITF` value group
3983#[allow(non_upper_case_globals)]
3984pub mod dvreg_ext_bitf {
3985 /// Internal DVDD voltage regulator for the digital section is enabled.
3986 pub const DVDD_INT: u32 = 0x0;
3987 /// Internal DVDD voltage regulator is disabled; use external regulated 1.8V supply voltage for the digital section.
3988 pub const DVDD_EXT: u32 = 0x1;
3989}
3990
3991/// `ED_LEVEL_BITF` value group
3992#[allow(non_upper_case_globals)]
3993pub mod ed_level_bitf {
3994 /// Minimum result of last ED measurement.
3995 pub const ED_MIN: u32 = 0x0;
3996 /// P(RF) = RSSI_BASE_VAL+ED \[dBm\].
3997 pub const ED_MIN_PLUS_1dB: u32 = 0x1;
3998 /// ...
3999 pub const VAL_0x02: u32 = 0x2;
4000 /// Maximum result of last ED measurement.
4001 pub const ED_MAX: u32 = 0x54;
4002 /// Reset value.
4003 pub const ED_RESET: u32 = 0xFF;
4004}
4005
4006/// `EEP_MODE2` value group
4007#[allow(non_upper_case_globals)]
4008pub mod eep_mode2 {
4009 /// Erase and Write in one operation (Atomic Operation).
4010 pub const VAL_0x00: u32 = 0x0;
4011 /// Erase only.
4012 pub const VAL_0x01: u32 = 0x1;
4013 /// Write only.
4014 pub const VAL_0x02: u32 = 0x2;
4015 /// Reserved for future use.
4016 pub const VAL_0x03: u32 = 0x3;
4017}
4018
4019/// `ENUM_BLB` value group
4020#[allow(non_upper_case_globals)]
4021pub mod enum_blb {
4022 /// LPM and SPM prohibited in Application Section.
4023 pub const LPM_SPM_DISABLE: u32 = 0x0;
4024 /// LPM prohibited in Application Section.
4025 pub const LPM_DISABLE: u32 = 0x1;
4026 /// SPM prohibited in Application Section.
4027 pub const SPM_DISABLE: u32 = 0x2;
4028 /// No lock on SPM and LPM in Application Section.
4029 pub const NO_LOCK: u32 = 0x3;
4030}
4031
4032/// `ENUM_BLB2` value group
4033#[allow(non_upper_case_globals)]
4034pub mod enum_blb2 {
4035 /// LPM and SPM prohibited in Boot Section.
4036 pub const LPM_SPM_DISABLE: u32 = 0x0;
4037 /// LPM prohibited in Boot Section.
4038 pub const LPM_DISABLE: u32 = 0x1;
4039 /// SPM prohibited in Boot Section.
4040 pub const SPM_DISABLE: u32 = 0x2;
4041 /// No lock on SPM and LPM in Boot Section.
4042 pub const NO_LOCK: u32 = 0x3;
4043}
4044
4045/// `ENUM_BODLEVEL` value group
4046#[allow(non_upper_case_globals)]
4047pub mod enum_bodlevel {
4048 /// Brown-out detection disabled.
4049 pub const DISABLED: u32 = 0x7;
4050 /// Brown-out detection at VCC=1.8 V.
4051 pub const _1V8: u32 = 0x6;
4052 /// Brown-out detection at VCC=1.9 V.
4053 pub const _1V9: u32 = 0x5;
4054 /// Brown-out detection at VCC=2.0 V.
4055 pub const _2V0: u32 = 0x4;
4056 /// Brown-out detection at VCC=2.1 V.
4057 pub const _2V1: u32 = 0x3;
4058 /// Brown-out detection at VCC=2.2 V.
4059 pub const _2V2: u32 = 0x2;
4060 /// Brown-out detection at VCC=2.3 V.
4061 pub const _2V3: u32 = 0x1;
4062 /// Brown-out detection at VCC=2.4 V.
4063 pub const _2V4: u32 = 0x0;
4064}
4065
4066/// `ENUM_BOOTSZ` value group
4067#[allow(non_upper_case_globals)]
4068pub mod enum_bootsz {
4069 /// Boot Flash size=512 words start address=$1FE00.
4070 pub const _512W_1FE00: u32 = 0x3;
4071 /// Boot Flash size=1024 words start address=$1FC00.
4072 pub const _1024W_1FC00: u32 = 0x2;
4073 /// Boot Flash size=2048 words start address=$1F800.
4074 pub const _2048W_1F800: u32 = 0x1;
4075 /// Boot Flash size=4096 words start address=$1F000.
4076 pub const _4096W_1F000: u32 = 0x0;
4077}
4078
4079/// `ENUM_LB` value group
4080#[allow(non_upper_case_globals)]
4081pub mod enum_lb {
4082 /// Further programming and verification disabled.
4083 pub const PROG_VER_DISABLED: u32 = 0x0;
4084 /// Further programming disabled.
4085 pub const PROG_DISABLED: u32 = 0x2;
4086 /// No memory lock features enabled.
4087 pub const NO_LOCK: u32 = 0x3;
4088}
4089
4090/// `ENUM_SUT_CKSEL` value group
4091#[allow(non_upper_case_globals)]
4092pub mod enum_sut_cksel {
4093 /// Ext. Clock; Start-up time: 6 CK + 0 ms.
4094 pub const EXTCLK_6CK_0MS: u32 = 0x0;
4095 /// Ext. Clock; Start-up time: 6 CK + 4.1 ms.
4096 pub const EXTCLK_6CK_4MS1: u32 = 0x10;
4097 /// Ext. Clock; Start-up time: 6 CK + 65 ms.
4098 pub const EXTCLK_6CK_65MS: u32 = 0x20;
4099 /// Int. RC Osc.; Start-up time: 6 CK + 0 ms.
4100 pub const INTRCOSC_6CK_0MS: u32 = 0x2;
4101 /// Int. RC Osc.; Start-up time: 6 CK + 4.1 ms.
4102 pub const INTRCOSC_6CK_4MS1: u32 = 0x12;
4103 /// Int. RC Osc.; Start-up time: 6 CK + 65 ms.
4104 pub const INTRCOSC_6CK_65MS: u32 = 0x22;
4105 /// Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms.
4106 pub const INTRCOSC_128KHZ_6CK_0MS: u32 = 0x3;
4107 /// Int. 128kHz RC Osc.; Start-up time: 6 CK + 4.1 ms.
4108 pub const INTRCOSC_128KHZ_6CK_4MS1: u32 = 0x13;
4109 /// Int. 128kHz RC Osc.; Start-up time: 6 CK + 65 ms.
4110 pub const INTRCOSC_128KHZ_6CK_65MS: u32 = 0x23;
4111}
4112
4113/// `INTERRUPT_EXT_FLAG_BITF` value group
4114#[allow(non_upper_case_globals)]
4115pub mod interrupt_ext_flag_bitf {
4116 /// No edge or logic change on INT7:0 occurred.
4117 pub const VAL_0x00: u32 = 0x0;
4118 /// A edge or logic change on INT0 occurred and triggered an interrupt request.
4119 pub const VAL_0x01: u32 = 0x1;
4120 /// ...
4121 pub const VAL_0x02: u32 = 0x2;
4122 /// A edge or logic change on INT7 occurred and triggered an interrupt request.
4123 pub const VAL_0x80: u32 = 0x80;
4124}
4125
4126/// `INTERRUPT_REQ_ENABLE_BITF` value group
4127#[allow(non_upper_case_globals)]
4128pub mod interrupt_req_enable_bitf {
4129 /// All external pin interrupts are disabled.
4130 pub const VAL_0x00: u32 = 0x0;
4131 /// All external pin interrupts are enabled.
4132 pub const VAL_0xff: u32 = 0xFF;
4133}
4134
4135/// `INTERRUPT_SENSE_CONTROL3` value group
4136#[allow(non_upper_case_globals)]
4137pub mod interrupt_sense_control3 {
4138 /// The low level of INTn generates an interrupt request.
4139 pub const VAL_0x00: u32 = 0x0;
4140 /// Any edge of INTn generates asynchronously an interrupt request.
4141 pub const VAL_0x01: u32 = 0x1;
4142 /// The falling edge of INTn generates asynchronously an interrupt request.
4143 pub const VAL_0x02: u32 = 0x2;
4144 /// The rising edge of INTn generates asynchronously an interrupt request.
4145 pub const VAL_0x03: u32 = 0x3;
4146}
4147
4148/// `LLDRH_VALUE_BITF` value group
4149#[allow(non_upper_case_globals)]
4150pub mod lldrh_value_bitf {
4151 /// Calibration limit for fast process corner/high output voltage.
4152 pub const VAL_0x00: u32 = 0x0;
4153 /// Calibration limit for slow process corner/low output voltage.
4154 pub const VAL_0x10: u32 = 0x10;
4155}
4156
4157/// `LLDRL_VALUE_BITF` value group
4158#[allow(non_upper_case_globals)]
4159pub mod lldrl_value_bitf {
4160 /// Calibration limit for fast process corner/high output voltage.
4161 pub const VAL_0x00: u32 = 0x0;
4162 /// Calibration limit for slow process corner/low output voltage.
4163 pub const VAL_0x08: u32 = 0x8;
4164}
4165
4166/// `MAN_ID_0_BITF` value group
4167#[allow(non_upper_case_globals)]
4168pub mod man_id_0_bitf {
4169 /// Atmel JEDEC manufacturer ID, bits \[7:0\] of 32 bit manufacturer ID: 00 00 00 1F.
4170 pub const ATMEL_BYTE_0: u32 = 0x1F;
4171}
4172
4173/// `MAN_ID_1_BITF` value group
4174#[allow(non_upper_case_globals)]
4175pub mod man_id_1_bitf {
4176 /// Atmel JEDEC manufacturer ID, bits \[15:8\] of 32 bit manufacturer ID: 00 00 00 1F.
4177 pub const ATMEL_BYTE_1: u32 = 0x0;
4178}
4179
4180/// `MAX_BE_bitf` value group
4181#[allow(non_upper_case_globals)]
4182pub mod max_be_bitf {
4183 /// This value is not valid for the maximum back-off exponent.
4184 pub const VAL_1: u32 = 0x1;
4185 /// This value is not valid for the maximum back-off exponent.
4186 pub const VAL_2: u32 = 0x2;
4187 /// Minimum, IEEE compliant value for the maximum back-off exponent.
4188 pub const VAL_3: u32 = 0x3;
4189 /// ...
4190 pub const VAL_4: u32 = 0x4;
4191 /// Maximum, IEEE compliant value for the maximum back-off exponent.
4192 pub const VAL_8: u32 = 0x8;
4193}
4194
4195/// `MAX_CSMA_RETRIES_bitf` value group
4196#[allow(non_upper_case_globals)]
4197pub mod max_csma_retries_bitf {
4198 /// No repetition of CSMA-CA procedure.
4199 pub const VAL_0x0: u32 = 0x0;
4200 /// One repetition of CSMA-CA procedure.
4201 pub const VAL_0x1: u32 = 0x1;
4202 /// ...
4203 pub const VAL_0x2: u32 = 0x2;
4204 /// Five repetitions (highest IEEE 802.15.4 compliant value).
4205 pub const VAL_0x5: u32 = 0x5;
4206 /// Reserved.
4207 pub const VAL_0x6: u32 = 0x6;
4208 /// Immediate frame re-transmission without performing CSMA-CA.
4209 pub const VAL_0x7: u32 = 0x7;
4210}
4211
4212/// `MAX_FRAME_RETRIES_bitf` value group
4213#[allow(non_upper_case_globals)]
4214pub mod max_frame_retries_bitf {
4215 /// Retransmission of frame is not attempted.
4216 pub const VAL_0x0: u32 = 0x0;
4217 /// Retransmission of frame is attempted once.
4218 pub const VAL_0x1: u32 = 0x1;
4219 /// ...
4220 pub const VAL_0x2: u32 = 0x2;
4221 /// Retransmission of frame is attempted 15 times.
4222 pub const VAL_0xF: u32 = 0xF;
4223}
4224
4225/// `MIN_BE_bitf` value group
4226#[allow(non_upper_case_globals)]
4227pub mod min_be_bitf {
4228 /// Minimum value of minimum back-off exponent.
4229 pub const VAL_0: u32 = 0x0;
4230 /// ...
4231 pub const VAL_1: u32 = 0x1;
4232 /// Maximum value of minimum back-off exponent. MIN_BE must be smaller or equal to MAX_BE.
4233 pub const VAL_8: u32 = 0x8;
4234}
4235
4236/// `NEMCR_ADDRESS_BITF` value group
4237#[allow(non_upper_case_globals)]
4238pub mod nemcr_address_bitf {
4239 /// Factory Row.
4240 pub const VAL_0: u32 = 0x0;
4241 /// User Row 1.
4242 pub const VAL_1: u32 = 0x1;
4243 /// User Row 2.
4244 pub const VAL_2: u32 = 0x2;
4245 /// User Row 3.
4246 pub const VAL_3: u32 = 0x3;
4247}
4248
4249/// `OCDR_DATA_BITF` value group
4250#[allow(non_upper_case_globals)]
4251pub mod ocdr_data_bitf {
4252 /// Refer to the debugger documentation for further information on how to use this register.
4253 pub const VAL_0: u32 = 0x0;
4254}
4255
4256/// `OQPSK_DATA_RATE_bitf` value group
4257#[allow(non_upper_case_globals)]
4258pub mod oqpsk_data_rate_bitf {
4259 /// 250 kb/s (IEEE 802.15.4 compliant).
4260 pub const RATE_250KB: u32 = 0x0;
4261 /// 500 kb/s.
4262 pub const RATE_500KB: u32 = 0x1;
4263 /// 1000 kb/s.
4264 pub const RATE_1000KB: u32 = 0x2;
4265 /// 2000 kb/s.
4266 pub const RATE_2000KB: u32 = 0x3;
4267}
4268
4269/// `OSCCAL_BITF` value group
4270#[allow(non_upper_case_globals)]
4271pub mod osccal_bitf {
4272 /// Calibration value for lowest oscillator frequency.
4273 pub const VAL_0x00: u32 = 0x0;
4274 /// End value of low frequency range calibration.
4275 pub const VAL_0x7f: u32 = 0x7F;
4276 /// Start value of high frequency range calibration.
4277 pub const VAL_0x80: u32 = 0x80;
4278 /// Calibration value for highest oscillator frequency.
4279 pub const VAL_0xff: u32 = 0xFF;
4280}
4281
4282/// Oscillator Calibration Values
4283#[allow(non_upper_case_globals)]
4284pub mod osccal_value_addresses {
4285 /// 16.0 MHz.
4286 pub const _16_0_MHz: u32 = 0x0;
4287}
4288
4289/// `PAD_IO_bitf` value group
4290#[allow(non_upper_case_globals)]
4291pub mod pad_io_bitf {
4292 /// 2 mA.
4293 pub const PAD_IO_2MA: u32 = 0x0;
4294 /// 4 mA.
4295 pub const PAD_IO_4MA: u32 = 0x1;
4296 /// 6 mA.
4297 pub const PAD_IO_6MA: u32 = 0x2;
4298 /// 8 mA.
4299 pub const PAD_IO_8MA: u32 = 0x3;
4300}
4301
4302/// `PALTD_bitf` value group
4303#[allow(non_upper_case_globals)]
4304pub mod paltd_bitf {
4305 /// -3us.
4306 pub const PALTD_MINUS_3US: u32 = 0x0;
4307 /// -2us.
4308 pub const PALTD_MINUS_2US: u32 = 0x1;
4309 /// -1us.
4310 pub const PALTD_MINUS_1US: u32 = 0x2;
4311 /// 0us.
4312 pub const PALTD_0US: u32 = 0x3;
4313 /// 1us.
4314 pub const PALTD_1US: u32 = 0x4;
4315 /// 2us.
4316 pub const PALTD_2US: u32 = 0x5;
4317 /// 3us.
4318 pub const PALTD_3US: u32 = 0x6;
4319 /// 4us.
4320 pub const PALTD_4US: u32 = 0x7;
4321}
4322
4323/// `PALTU_bitf` value group
4324#[allow(non_upper_case_globals)]
4325pub mod paltu_bitf {
4326 /// -3us.
4327 pub const PALTU_MINUS_3US: u32 = 0x0;
4328 /// -2us.
4329 pub const PALTU_MINUS_2US: u32 = 0x1;
4330 /// -1us.
4331 pub const PALTU_MINUS_1US: u32 = 0x2;
4332 /// 0us.
4333 pub const PALTU_0US: u32 = 0x3;
4334 /// 1us.
4335 pub const PALTU_1US: u32 = 0x4;
4336 /// 2us.
4337 pub const PALTU_2US: u32 = 0x5;
4338 /// 3us.
4339 pub const PALTU_3US: u32 = 0x6;
4340 /// 4us.
4341 pub const PALTU_4US: u32 = 0x7;
4342}
4343
4344/// `PART_NUM_bitf` value group
4345#[allow(non_upper_case_globals)]
4346pub mod part_num_bitf {
4347 /// ATmega128RFA1 part number.
4348 pub const P_ATmega128RFA1: u32 = 0x83;
4349 /// RFA2 family.
4350 pub const P_RFA2: u32 = 0x93;
4351 /// RFR2 family.
4352 pub const P_RFR2: u32 = 0x94;
4353}
4354
4355/// `PDT_THRES_bitf` value group
4356#[allow(non_upper_case_globals)]
4357pub mod pdt_thres_bitf {
4358 /// Reset value, to be used if Antenna Diversity algorithm is disabled.
4359 pub const PDT_THRES_ANT_DIV_OFF: u32 = 0x7;
4360 /// Recommended correlator threshold for Antenna Diversity operation.
4361 pub const PDT_THRES_ANT_DIV_ON: u32 = 0x3;
4362}
4363
4364/// `RAMPZ_BITF` value group
4365#[allow(non_upper_case_globals)]
4366pub mod rampz_bitf {
4367 /// Default value of Z-pointer MSB's.
4368 pub const VAL_0: u32 = 0x0;
4369}
4370
4371/// `RSSI_VALUE_BITF` value group
4372#[allow(non_upper_case_globals)]
4373pub mod rssi_value_bitf {
4374 /// Minimum RSSI value: P(RF) < -90 dBm.
4375 pub const RSSI_MIN: u32 = 0x0;
4376 /// P(RF) = RSSI_BASE_VAL+3 · (RSSI-1) \[dBm\].
4377 pub const RSSI_MIN_PLUS_3dB: u32 = 0x1;
4378 /// ...
4379 pub const VAL_2: u32 = 0x2;
4380 /// Maximum RSSI value: P(RF) ≥ -10 dBm.
4381 pub const RSSI_MAX: u32 = 0x1C;
4382}
4383
4384/// `RX_CRC_VALID_bitf` value group
4385#[allow(non_upper_case_globals)]
4386pub mod rx_crc_valid_bitf {
4387 /// CRC (FCS) not valid.
4388 pub const CRC_INVALID: u32 = 0x0;
4389 /// CRC (FCS) valid.
4390 pub const CRC_VALID: u32 = 0x1;
4391}
4392
4393/// `RX_PDT_LEVEL_BITF` value group
4394#[allow(non_upper_case_globals)]
4395pub mod rx_pdt_level_bitf {
4396 /// RX_THRES ≤ RSSI_BASE_VAL (Reset value); RSSI value not considered.
4397 pub const RX_PDT_LEVEL_MIN: u32 = 0x0;
4398 /// RX_THRES > RSSI_BASE_VAL + 0 · 3; RSSI > -90 dBm.
4399 pub const VAL_0x1: u32 = 0x1;
4400 /// ...
4401 pub const VAL_0x2: u32 = 0x2;
4402 /// RX_THRES > RSSI_BASE_VAL + 13 · 3; RSSI > -51 dBm.
4403 pub const VAL_0xE: u32 = 0xE;
4404 /// RX_THRES > RSSI_BASE_VAL + 14 · 3; RSSI > -48 dBm.
4405 pub const RX_PDT_LEVEL_MAX: u32 = 0xF;
4406}
4407
4408/// `RX_RPC_CTRL_BITF` value group
4409#[allow(non_upper_case_globals)]
4410pub mod rx_rpc_ctrl_bitf {
4411 /// Activates minimum power saving behaviour for smart receiving mode.
4412 pub const VAL_0: u32 = 0x0;
4413 /// Reserved.
4414 pub const VAL_1: u32 = 0x1;
4415 /// Reserved.
4416 pub const VAL_2: u32 = 0x2;
4417 /// Activates maximum power saving behaviour for smart receiving mode.
4418 pub const VAL_3: u32 = 0x3;
4419}
4420
4421/// `SCCKDIV_BITF` value group
4422#[allow(non_upper_case_globals)]
4423pub mod scckdiv_bitf {
4424 /// Transceiver Clock divided by 256, (62.5kHz).
4425 pub const VAL_0: u32 = 0x0;
4426 /// Transceiver Clock divided by 128, (125kHz).
4427 pub const VAL_1: u32 = 0x1;
4428 /// Transceiver Clock divided by 64, (250kHz).
4429 pub const VAL_2: u32 = 0x2;
4430 /// Transceiver Clock divided by 32, (500kHz).
4431 pub const VAL_3: u32 = 0x3;
4432 /// Transceiver Clock divided by 16, (1MHz).
4433 pub const VAL_4: u32 = 0x4;
4434 /// Transceiver Clock divided by 8, (2MHz).
4435 pub const VAL_5: u32 = 0x5;
4436 /// Transceiver Clock divided by 4, (4MHz).
4437 pub const VAL_6: u32 = 0x6;
4438}
4439
4440/// `SCCS1_BITF` value group
4441#[allow(non_upper_case_globals)]
4442pub mod sccs1_bitf {
4443 /// Compare Unit 1 Relative Compare Source = Beacon Timestamp Register.
4444 pub const VAL_0: u32 = 0x0;
4445 /// Compare Unit 1 Relative Compare Source = Transmit Frame Timestamp Register.
4446 pub const VAL_1: u32 = 0x1;
4447 /// Compare Unit 1 Relative Compare Source = Received Frame Timestamp Register.
4448 pub const VAL_2: u32 = 0x2;
4449}
4450
4451/// `SCCS2_BITF` value group
4452#[allow(non_upper_case_globals)]
4453pub mod sccs2_bitf {
4454 /// Compare Unit 2 Relative Compare Source = Beacon Timestamp Register.
4455 pub const VAL_0: u32 = 0x0;
4456 /// Compare Unit 2 Relative Compare Source = Transmit Frame Timestamp Register.
4457 pub const VAL_1: u32 = 0x1;
4458 /// Compare Unit 2 Relative Compare Source = Received Frame Timestamp Register.
4459 pub const VAL_2: u32 = 0x2;
4460}
4461
4462/// `SCCS3_BITF` value group
4463#[allow(non_upper_case_globals)]
4464pub mod sccs3_bitf {
4465 /// Compare Unit 3 Relative Compare Source = Beacon Timestamp Register.
4466 pub const VAL_0: u32 = 0x0;
4467 /// Compare Unit 3 Relative Compare Source = Transmit Frame Timestamp Register.
4468 pub const VAL_1: u32 = 0x1;
4469 /// Compare Unit 3 Relative Compare Source = Received Frame Timestamp Register.
4470 pub const VAL_2: u32 = 0x2;
4471}
4472
4473/// `SFD_VALUE_BITF` value group
4474#[allow(non_upper_case_globals)]
4475pub mod sfd_value_bitf {
4476 /// IEEE 802.15.4 compliant value of the SFD.
4477 pub const IEEE_SFD: u32 = 0xA7;
4478}
4479
4480/// `SLOTTED_OPERATION_BITF` value group
4481#[allow(non_upper_case_globals)]
4482pub mod slotted_operation_bitf {
4483 /// The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested.
4484 pub const SLOTTED_OP_DIS: u32 = 0x0;
4485 /// The transmission of an acknowledgment frame has to be controlled by the microcontroller.
4486 pub const SLOTTED_OP_EN: u32 = 0x1;
4487}
4488
4489/// `SPI_CPHA_BITF` value group
4490#[allow(non_upper_case_globals)]
4491pub mod spi_cpha_bitf {
4492 /// Sample (Leading Edge), Setup (Trailing Edge).
4493 pub const VAL_0: u32 = 0x0;
4494 /// Setup (Leading Edge), Sample (Trailing Edge).
4495 pub const VAL_1: u32 = 0x1;
4496}
4497
4498/// `SPI_CPOL_BITF` value group
4499#[allow(non_upper_case_globals)]
4500pub mod spi_cpol_bitf {
4501 /// Rising (Leading Edge), Falling (Trailing Edge).
4502 pub const VAL_0: u32 = 0x0;
4503 /// Falling (Leading Egde), Rising (Trailing Edge).
4504 pub const VAL_1: u32 = 0x1;
4505}
4506
4507/// `TC0_CLK_SEL_3BIT_EXT` value group
4508#[allow(non_upper_case_globals)]
4509pub mod tc0_clk_sel_3bit_ext {
4510 /// No clock source (Timer/Counter0 stopped).
4511 pub const VAL_0x00: u32 = 0x0;
4512 /// clk_IO/1 (no prescaling).
4513 pub const VAL_0x01: u32 = 0x1;
4514 /// clk_IO/8 (from prescaler).
4515 pub const VAL_0x02: u32 = 0x2;
4516 /// clk_IO/64 (from prescaler).
4517 pub const VAL_0x03: u32 = 0x3;
4518 /// clk_IO/256 (from prescaler).
4519 pub const VAL_0x04: u32 = 0x4;
4520 /// clk_IO/1024 (from prescaler).
4521 pub const VAL_0x05: u32 = 0x5;
4522 /// External clock source on T0 pin, clock on falling edge.
4523 pub const VAL_0x06: u32 = 0x6;
4524 /// External clock source on T0 pin, clock on rising edge.
4525 pub const VAL_0x07: u32 = 0x7;
4526}
4527
4528/// `TC0_COM0A_BITF` value group
4529#[allow(non_upper_case_globals)]
4530pub mod tc0_com0a_bitf {
4531 /// Normal port operation, OC0A disconnected.
4532 pub const VAL_0: u32 = 0x0;
4533 /// Toggle OC0A on Compare Match.
4534 pub const VAL_1: u32 = 0x1;
4535 /// Clear OC0A on Compare Match.
4536 pub const VAL_2: u32 = 0x2;
4537 /// Set OC0A on Compare Match.
4538 pub const VAL_3: u32 = 0x3;
4539}
4540
4541/// `TC0_COM0B_BITF` value group
4542#[allow(non_upper_case_globals)]
4543pub mod tc0_com0b_bitf {
4544 /// Normal port operation, OC0B disconnected.
4545 pub const VAL_0: u32 = 0x0;
4546 /// Toggle OC0B on Compare Match.
4547 pub const VAL_1: u32 = 0x1;
4548 /// Clear OC0B on Compare Match.
4549 pub const VAL_2: u32 = 0x2;
4550 /// Set OC0B on Compare Match.
4551 pub const VAL_3: u32 = 0x3;
4552}
4553
4554/// `TC0_WGM_BITF` value group
4555#[allow(non_upper_case_globals)]
4556pub mod tc0_wgm_bitf {
4557 /// Normal mode of operation.
4558 pub const VAL_0x0: u32 = 0x0;
4559 /// PWM, phase correct, TOP=0xFF.
4560 pub const VAL_0x1: u32 = 0x1;
4561 /// CTC, TOP = OCRA.
4562 pub const VAL_0x2: u32 = 0x2;
4563 /// Fast PWM, TOP=0xFF.
4564 pub const VAL_0x3: u32 = 0x3;
4565 /// Reserved.
4566 pub const VAL_0x4: u32 = 0x4;
4567 /// PWM, Phase correct, TOP = OCRA.
4568 pub const VAL_0x5: u32 = 0x5;
4569 /// Reserved.
4570 pub const VAL_0x6: u32 = 0x6;
4571 /// Fast PWM, TOP=OCRA.
4572 pub const VAL_0x7: u32 = 0x7;
4573}
4574
4575/// `TC1_COMNX_BITF` value group
4576#[allow(non_upper_case_globals)]
4577pub mod tc1_comnx_bitf {
4578 /// Normal port operation, OCnA/OCnB/OCnC disconnected.
4579 pub const VAL_0: u32 = 0x0;
4580 /// Toggle OCnA/OCnB/OCnC on Compare Match.
4581 pub const VAL_1: u32 = 0x1;
4582 /// Clear OCnA/OCnB/OCnC on Compare Match (set output to low level).
4583 pub const VAL_2: u32 = 0x2;
4584 /// Set OCnA/OCnB/OCnC on Compare Match (set output to high level).
4585 pub const VAL_3: u32 = 0x3;
4586}
4587
4588/// `TC1_WGMX_BITF` value group
4589#[allow(non_upper_case_globals)]
4590pub mod tc1_wgmx_bitf {
4591 /// Normal mode of operation.
4592 pub const VAL_0x0: u32 = 0x0;
4593 /// PWM, phase correct, 8-bit.
4594 pub const VAL_0x1: u32 = 0x1;
4595 /// PWM, phase correct, 9-bit.
4596 pub const VAL_0x2: u32 = 0x2;
4597 /// PWM, phase correct, 10-bit.
4598 pub const VAL_0x3: u32 = 0x3;
4599 /// CTC, TOP = OCRnA.
4600 pub const VAL_0x4: u32 = 0x4;
4601 /// Fast PWM, 8-bit.
4602 pub const VAL_0x5: u32 = 0x5;
4603 /// Fast PWM, 9-bit.
4604 pub const VAL_0x6: u32 = 0x6;
4605 /// Fast PWM, 10-bit.
4606 pub const VAL_0x7: u32 = 0x7;
4607 /// PWM, Phase and frequency correct, TOP = ICRn.
4608 pub const VAL_0x8: u32 = 0x8;
4609 /// PWM, Phase and frequency correct, TOP = OCRnA.
4610 pub const VAL_0x9: u32 = 0x9;
4611 /// PWM, Phase correct, TOP = ICRn.
4612 pub const VAL_0xA: u32 = 0xA;
4613 /// PWM, Phase correct, TOP = OCRnA.
4614 pub const VAL_0xB: u32 = 0xB;
4615 /// CTC, TOP = OCRnA.
4616 pub const VAL_0xC: u32 = 0xC;
4617 /// Reserved.
4618 pub const VAL_0xD: u32 = 0xD;
4619 /// Fast PWM, TOP = ICRn.
4620 pub const VAL_0xE: u32 = 0xE;
4621 /// Fast PWM, TOP = OCRnA.
4622 pub const VAL_0xF: u32 = 0xF;
4623}
4624
4625/// `TC2_CLK_SEL_3BIT` value group
4626#[allow(non_upper_case_globals)]
4627pub mod tc2_clk_sel_3bit {
4628 /// No clock source (Timer/Counter2 stopped).
4629 pub const VAL_0x00: u32 = 0x0;
4630 /// clk_T2S/1 (no prescaling).
4631 pub const VAL_0x01: u32 = 0x1;
4632 /// clk_T2S/8 (from prescaler).
4633 pub const VAL_0x02: u32 = 0x2;
4634 /// clk_T2S/32 (from prescaler).
4635 pub const VAL_0x03: u32 = 0x3;
4636 /// clk_T2S/64 (from prescaler).
4637 pub const VAL_0x04: u32 = 0x4;
4638 /// clk_T2S/128 (from prescaler).
4639 pub const VAL_0x05: u32 = 0x5;
4640 /// clk_T2S/256 (from prescaler).
4641 pub const VAL_0x06: u32 = 0x6;
4642 /// clk_T2S/1024 (from prescaler).
4643 pub const VAL_0x07: u32 = 0x7;
4644}
4645
4646/// `TC2_COM2A_BITF` value group
4647#[allow(non_upper_case_globals)]
4648pub mod tc2_com2a_bitf {
4649 /// Normal port operation, OC2A disconnected.
4650 pub const VAL_0: u32 = 0x0;
4651 /// Toggle OC2A on Compare Match.
4652 pub const VAL_1: u32 = 0x1;
4653 /// Clear OC2A on Compare Match.
4654 pub const VAL_2: u32 = 0x2;
4655 /// Set OC2A on Compare Match.
4656 pub const VAL_3: u32 = 0x3;
4657}
4658
4659/// `TC2_COM2B_BITF` value group
4660#[allow(non_upper_case_globals)]
4661pub mod tc2_com2b_bitf {
4662 /// Normal port operation, OC2B disconnected.
4663 pub const VAL_0: u32 = 0x0;
4664 /// Toggle OC2B on Compare Match.
4665 pub const VAL_1: u32 = 0x1;
4666 /// Clear OC2B on Compare Match.
4667 pub const VAL_2: u32 = 0x2;
4668 /// Set OC2B on Compare Match.
4669 pub const VAL_3: u32 = 0x3;
4670}
4671
4672/// `TC4_COMNX_BITF` value group
4673#[allow(non_upper_case_globals)]
4674pub mod tc4_comnx_bitf {
4675 /// Normal operation.
4676 pub const VAL_0: u32 = 0x0;
4677 /// Reserved.
4678 pub const VAL_1: u32 = 0x1;
4679 /// Reserved.
4680 pub const VAL_2: u32 = 0x2;
4681 /// Reserved.
4682 pub const VAL_3: u32 = 0x3;
4683}
4684
4685/// `TRAC_STATUS_bitf` value group
4686#[allow(non_upper_case_globals)]
4687pub mod trac_status_bitf {
4688 /// SUCCESS (RX_AACK, TX_ARET).
4689 pub const TRAC_SUCCESS: u32 = 0x0;
4690 /// SUCCESS_DATA_PENDING (TX_ARET).
4691 pub const TRAC_SUCCESS_DATA_PENDING: u32 = 0x1;
4692 /// SUCCESS_WAIT_FOR_ACK (RX_AACK).
4693 pub const TRAC_SUCCESS_WAIT_FOR_ACK: u32 = 0x2;
4694 /// CHANNEL_ACCESS_FAILURE (TX_ARET).
4695 pub const TRAC_CHANNEL_ACCESS_FAILURE: u32 = 0x3;
4696 /// NO_ACK (TX_ARET).
4697 pub const TRAC_NO_ACK: u32 = 0x5;
4698 /// INVALID (RX_AACK, TX_ARET).
4699 pub const TRAC_INVALID: u32 = 0x7;
4700}
4701
4702/// `TRX_CMD_bitf` value group
4703#[allow(non_upper_case_globals)]
4704pub mod trx_cmd_bitf {
4705 /// NOP.
4706 pub const CMD_NOP: u32 = 0x0;
4707 /// TX_START.
4708 pub const CMD_TX_START: u32 = 0x2;
4709 /// FORCE_TRX_OFF.
4710 pub const CMD_FORCE_TRX_OFF: u32 = 0x3;
4711 /// FORCE_PLL_ON.
4712 pub const CMD_FORCE_PLL_ON: u32 = 0x4;
4713 /// RX_ON.
4714 pub const CMD_RX_ON: u32 = 0x6;
4715 /// TRX_OFF.
4716 pub const CMD_TRX_OFF: u32 = 0x8;
4717 /// PLL_ON (TX_ON).
4718 pub const CMD_PLL_ON: u32 = 0x9;
4719 /// RX_AACK_ON.
4720 pub const CMD_RX_AACK_ON: u32 = 0x16;
4721 /// TX_ARET_ON.
4722 pub const CMD_TX_ARET_ON: u32 = 0x19;
4723}
4724
4725/// `TRX_STATUS_bitf` value group
4726#[allow(non_upper_case_globals)]
4727pub mod trx_status_bitf {
4728 /// P_ON.
4729 pub const P_ON: u32 = 0x0;
4730 /// BUSY_RX.
4731 pub const BUSY_RX: u32 = 0x1;
4732 /// BUSY_TX.
4733 pub const BUSY_TX: u32 = 0x2;
4734 /// RX_ON.
4735 pub const RX_ON: u32 = 0x6;
4736 /// TRX_OFF.
4737 pub const TRX_OFF: u32 = 0x8;
4738 /// PLL_ON.
4739 pub const PLL_ON: u32 = 0x9;
4740 /// SLEEP.
4741 pub const SLEEP: u32 = 0xF;
4742 /// BUSY_RX_AACK.
4743 pub const BUSY_RX_AACK: u32 = 0x11;
4744 /// BUSY_TX_ARET.
4745 pub const BUSY_TX_ARET: u32 = 0x12;
4746 /// RX_AACK_ON.
4747 pub const RX_AACK_ON: u32 = 0x16;
4748 /// TX_ARET_ON.
4749 pub const TX_ARET_ON: u32 = 0x19;
4750 /// STATE_TRANSITION_IN_PROGRESS.
4751 pub const STATE_TRANSITION_IN_PROGRESS: u32 = 0x1F;
4752}
4753
4754/// `TST_CTRL_DIG_BITF` value group
4755#[allow(non_upper_case_globals)]
4756pub mod tst_ctrl_dig_bitf {
4757 /// NORMAL (no test is active).
4758 pub const VAL_0: u32 = 0x0;
4759 /// TST_CONT_TX (continuous transmit).
4760 pub const VAL_15: u32 = 0xF;
4761}
4762
4763/// `TST_STATUS_bitf` value group
4764#[allow(non_upper_case_globals)]
4765pub mod tst_status_bitf {
4766 /// Test mode is disabled.
4767 pub const TST_DISABLED: u32 = 0x0;
4768 /// Test mode is active.
4769 pub const TST_ENABLED: u32 = 0x1;
4770}
4771
4772/// `TWI_STATUS_BITF` value group
4773#[allow(non_upper_case_globals)]
4774pub mod twi_status_bitf {
4775 /// Bus error due to illegal START or STOP condition.
4776 pub const VAL_0x00: u32 = 0x0;
4777 /// A START condition has been transmitted.
4778 pub const VAL_0x08: u32 = 0x8;
4779 /// A repeated START condition has been transmitted.
4780 pub const VAL_0x10: u32 = 0x10;
4781 /// SLA+W has been transmitted; ACK has been received.
4782 pub const VAL_0x18: u32 = 0x18;
4783 /// SLA+W has been transmitted; NOT ACK has been received.
4784 pub const VAL_0x20: u32 = 0x20;
4785 /// Data byte has been transmitted; ACK has been received.
4786 pub const VAL_0x28: u32 = 0x28;
4787 /// Data byte has been transmitted; NOT ACK has been received.
4788 pub const VAL_0x30: u32 = 0x30;
4789 /// Arbitration lost in SLA+W or data bytes (Transmitter); Arbitration lost in SLA+R or NOT ACK bit (Receiver).
4790 pub const VAL_0x38: u32 = 0x38;
4791 /// SLA+R has been transmitted; ACK has been received.
4792 pub const VAL_0x40: u32 = 0x40;
4793 /// SLA+R has been transmitted; NOT ACK has been received.
4794 pub const VAL_0x48: u32 = 0x48;
4795 /// Data byte has been received; ACK has been returned.
4796 pub const VAL_0x50: u32 = 0x50;
4797 /// Data byte has been received; NOT ACK has been returned.
4798 pub const VAL_0x58: u32 = 0x58;
4799 /// Own SLA+W has been received; ACK has been returned.
4800 pub const VAL_0x60: u32 = 0x60;
4801 /// Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned.
4802 pub const VAL_0x68: u32 = 0x68;
4803 /// General call address has been received; ACK has been returned.
4804 pub const VAL_0x70: u32 = 0x70;
4805 /// Arbitration lost in SLA+R/W as Master; general call address has been received; ACK has been returned.
4806 pub const VAL_0x78: u32 = 0x78;
4807 /// Previously addressed with own SLA+W; data has been received; ACK has been returned.
4808 pub const VAL_0x80: u32 = 0x80;
4809 /// Previously addressed with own SLA+W; data has been received; NOT ACK has been returned.
4810 pub const VAL_0x88: u32 = 0x88;
4811 /// Previously addressed with general call; data has been received; ACK has been returned.
4812 pub const VAL_0x90: u32 = 0x90;
4813 /// Previously addressed with general call; data has been received; NOT ACK has been returned.
4814 pub const VAL_0x98: u32 = 0x98;
4815 /// A STOP condition or repeated START condition has been received while still addressed as Slave.
4816 pub const VAL_0xA0: u32 = 0xA0;
4817 /// Own SLA+R has been received; ACK has been returned.
4818 pub const VAL_0xA8: u32 = 0xA8;
4819 /// Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned.
4820 pub const VAL_0xB0: u32 = 0xB0;
4821 /// Data byte in TWDR has been transmitted; ACK has been received.
4822 pub const VAL_0xB8: u32 = 0xB8;
4823 /// Data byte in TWDR has been transmitted; NO ACK has been received.
4824 pub const VAL_0xC0: u32 = 0xC0;
4825 /// Last data byte in TWDR has been transmitted (TWEA = 0); ACK has been received.
4826 pub const VAL_0xC8: u32 = 0xC8;
4827 /// No relevant state information available; TWINT = 0.
4828 pub const VAL_0xF8: u32 = 0xF8;
4829}
4830
4831/// `TX_PWR_bitf` value group
4832#[allow(non_upper_case_globals)]
4833pub mod tx_pwr_bitf {
4834 /// 3.5 dBm.
4835 pub const VAL_0: u32 = 0x0;
4836 /// 3.3 dBm.
4837 pub const VAL_1: u32 = 0x1;
4838 /// 2.8 dBm.
4839 pub const VAL_2: u32 = 0x2;
4840 /// 2.3 dBm.
4841 pub const VAL_3: u32 = 0x3;
4842 /// 1.8 dBm.
4843 pub const VAL_4: u32 = 0x4;
4844 /// 1.2 dBm.
4845 pub const VAL_5: u32 = 0x5;
4846 /// 0.5 dBm.
4847 pub const VAL_6: u32 = 0x6;
4848 /// -0.5 dBm.
4849 pub const VAL_7: u32 = 0x7;
4850 /// -1.5 dBm.
4851 pub const VAL_8: u32 = 0x8;
4852 /// -2.5 dBm.
4853 pub const VAL_9: u32 = 0x9;
4854 /// -3.5 dBm.
4855 pub const VAL_10: u32 = 0xA;
4856 /// -4.5 dBm.
4857 pub const VAL_11: u32 = 0xB;
4858 /// -6.5 dBm.
4859 pub const VAL_12: u32 = 0xC;
4860 /// -8.5 dBm.
4861 pub const VAL_13: u32 = 0xD;
4862 /// -11.5 dBm.
4863 pub const VAL_14: u32 = 0xE;
4864 /// -16.5 dBm.
4865 pub const VAL_15: u32 = 0xF;
4866}
4867
4868/// `USART_CHAR_SIZE_BITF` value group
4869#[allow(non_upper_case_globals)]
4870pub mod usart_char_size_bitf {
4871 /// 5-bit.
4872 pub const VAL_0: u32 = 0x0;
4873 /// 6-bit.
4874 pub const VAL_1: u32 = 0x1;
4875 /// 7-bit.
4876 pub const VAL_2: u32 = 0x2;
4877 /// 8-bit.
4878 pub const VAL_3: u32 = 0x3;
4879 /// Reserved.
4880 pub const VAL_4: u32 = 0x4;
4881 /// Reserved.
4882 pub const VAL_5: u32 = 0x5;
4883 /// Reserved.
4884 pub const VAL_6: u32 = 0x6;
4885 /// 9-bit.
4886 pub const VAL_7: u32 = 0x7;
4887}
4888
4889/// `USART_CLK_POLARITY_BITF` value group
4890#[allow(non_upper_case_globals)]
4891pub mod usart_clk_polarity_bitf {
4892 /// Rising XCKn Edge (Transmitted Data Changed), Falling XCKn Edge (Received Data Sampled).
4893 pub const VAL_0: u32 = 0x0;
4894 /// Falling XCKn Edge (Transmitted Data Changed), Rising XCKn Edge (Received Data Sampled).
4895 pub const VAL_1: u32 = 0x1;
4896}
4897
4898/// `VERSION_NUM_2_BITF` value group
4899#[allow(non_upper_case_globals)]
4900pub mod version_num_2_bitf {
4901 /// Revision A.
4902 pub const REV_A: u32 = 0xC;
4903 /// Revision B.
4904 pub const REV_B: u32 = 0x1;
4905 /// Revision C.
4906 pub const REV_C: u32 = 0x3;
4907 /// Revision D.
4908 pub const REV_D: u32 = 0x4;
4909}
4910
4911/// `WDOG_TIMER_PRESCALE_4BITS` value group
4912#[allow(non_upper_case_globals)]
4913pub mod wdog_timer_prescale_4bits {
4914 /// Oscillator Cycles 2K.
4915 pub const VAL_0x00: u32 = 0x0;
4916 /// Oscillator Cycles 4K.
4917 pub const VAL_0x01: u32 = 0x1;
4918 /// Oscillator Cycles 8K.
4919 pub const VAL_0x02: u32 = 0x2;
4920 /// Oscillator Cycles 16K.
4921 pub const VAL_0x03: u32 = 0x3;
4922 /// Oscillator Cycles 32K.
4923 pub const VAL_0x04: u32 = 0x4;
4924 /// Oscillator Cycles 64K.
4925 pub const VAL_0x05: u32 = 0x5;
4926 /// Oscillator Cycles 128K.
4927 pub const VAL_0x06: u32 = 0x6;
4928 /// Oscillator Cycles 256K.
4929 pub const VAL_0x07: u32 = 0x7;
4930 /// Oscillator Cycles 512K.
4931 pub const VAL_0x08: u32 = 0x8;
4932 /// Oscillator Cycles 1024K.
4933 pub const VAL_0x09: u32 = 0x9;
4934}
4935
4936/// `XTAL_MODE_BITF` value group
4937#[allow(non_upper_case_globals)]
4938pub mod xtal_mode_bitf {
4939 /// Internal crystal oscillator disabled; use external reference frequency.
4940 pub const VAL_0x4: u32 = 0x4;
4941 /// Internal crystal oscillator enabled; amplitude regulation of oscillation enabled.
4942 pub const VAL_0xF: u32 = 0xF;
4943}
4944
4945/// `XTAL_TRIM_bitf` value group
4946#[allow(non_upper_case_globals)]
4947pub mod xtal_trim_bitf {
4948 /// 0.0 pF, trimming capacitors disconnected.
4949 pub const XTAL_TRIM_MIN: u32 = 0x0;
4950 /// 0.3 pF, trimming capacitor switched on.
4951 pub const VAL_0x1: u32 = 0x1;
4952 /// ...
4953 pub const VAL_0x2: u32 = 0x2;
4954 /// 4.5 pF, trimming capacitor switched on.
4955 pub const XTAL_TRIM_MAX: u32 = 0xF;
4956}
4957