avrd/gen/atmega644rfr2.rs
1//! The AVR ATmega644RFR2 microcontroller
2//!
3//! # Variants
4//! | | Pinout | Mcu age | Operating temperature | Operating voltage | Max speed |
5//! |--------|--------|---------|-----------------------|-------------------|-----------|
6//! | ATmega644RFR2-ZU | | VQFN48 | -40°C - 85°C | 1.8V - 3.6V | 16 MHz |
7//! | ATmega644RFR2-ZUR | | VQFN48 | -40°C - 85°C | 1.8V - 3.6V | 16 MHz |
8//! | ATmega644RFR2-ZF | | VQFN48 | -40°C - 125°C | 1.8V - 3.6V | 16 MHz |
9//! | ATmega644RFR2-ZFR | | VQFN48 | -40°C - 125°C | 1.8V - 3.6V | 16 MHz |
10//!
11
12#![allow(non_upper_case_globals)]
13
14/// `LOW` register
15///
16/// Bitfields:
17///
18/// | Name | Mask (binary) |
19/// | ---- | ------------- |
20/// | CKOUT | 1000000 |
21/// | CKSEL_SUT | 111111 |
22/// | CKDIV8 | 10000000 |
23pub const LOW: *mut u8 = 0x0 as *mut u8;
24
25/// `LOCKBIT` register
26///
27/// Bitfields:
28///
29/// | Name | Mask (binary) |
30/// | ---- | ------------- |
31/// | BLB1 | 110000 |
32/// | LB | 11 |
33/// | BLB0 | 1100 |
34pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
35
36/// `HIGH` register
37///
38/// Bitfields:
39///
40/// | Name | Mask (binary) |
41/// | ---- | ------------- |
42/// | OCDEN | 10000000 |
43/// | BOOTRST | 1 |
44/// | SPIEN | 100000 |
45/// | WDTON | 10000 |
46/// | EESAVE | 1000 |
47/// | JTAGEN | 1000000 |
48/// | BOOTSZ | 110 |
49pub const HIGH: *mut u8 = 0x1 as *mut u8;
50
51/// `EXTENDED` register
52///
53/// Bitfields:
54///
55/// | Name | Mask (binary) |
56/// | ---- | ------------- |
57/// | BODLEVEL | 111 |
58pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
59
60/// Port A Input Pins Address.
61pub const PINA: *mut u8 = 0x20 as *mut u8;
62
63/// Port A Data Direction Register.
64pub const DDRA: *mut u8 = 0x21 as *mut u8;
65
66/// Port A Data Register.
67pub const PORTA: *mut u8 = 0x22 as *mut u8;
68
69/// Port B Input Pins Address.
70pub const PINB: *mut u8 = 0x23 as *mut u8;
71
72/// Port B Data Direction Register.
73pub const DDRB: *mut u8 = 0x24 as *mut u8;
74
75/// Port B Data Register.
76pub const PORTB: *mut u8 = 0x25 as *mut u8;
77
78/// Port C Input Pins Address.
79pub const PINC: *mut u8 = 0x26 as *mut u8;
80
81/// Port C Data Direction Register.
82pub const DDRC: *mut u8 = 0x27 as *mut u8;
83
84/// Port C Data Register.
85pub const PORTC: *mut u8 = 0x28 as *mut u8;
86
87/// Port D Input Pins Address.
88pub const PIND: *mut u8 = 0x29 as *mut u8;
89
90/// Port D Data Direction Register.
91pub const DDRD: *mut u8 = 0x2A as *mut u8;
92
93/// Port D Data Register.
94pub const PORTD: *mut u8 = 0x2B as *mut u8;
95
96/// Port E Input Pins Address.
97pub const PINE: *mut u8 = 0x2C as *mut u8;
98
99/// Port E Data Direction Register.
100pub const DDRE: *mut u8 = 0x2D as *mut u8;
101
102/// Port E Data Register.
103pub const PORTE: *mut u8 = 0x2E as *mut u8;
104
105/// Port F Input Pins Address.
106pub const PINF: *mut u8 = 0x2F as *mut u8;
107
108/// Port F Data Direction Register.
109pub const DDRF: *mut u8 = 0x30 as *mut u8;
110
111/// Port F Data Register.
112pub const PORTF: *mut u8 = 0x31 as *mut u8;
113
114/// Port G Input Pins Address.
115pub const PING: *mut u8 = 0x32 as *mut u8;
116
117/// Port G Data Direction Register.
118pub const DDRG: *mut u8 = 0x33 as *mut u8;
119
120/// Port G Data Register.
121pub const PORTG: *mut u8 = 0x34 as *mut u8;
122
123/// Timer/Counter0 Interrupt Flag Register.
124///
125/// Bitfields:
126///
127/// | Name | Mask (binary) |
128/// | ---- | ------------- |
129/// | OCF0A | 10 |
130/// | OCF0B | 100 |
131/// | TOV0 | 1 |
132pub const TIFR0: *mut u8 = 0x35 as *mut u8;
133
134/// Timer/Counter1 Interrupt Flag Register.
135///
136/// Bitfields:
137///
138/// | Name | Mask (binary) |
139/// | ---- | ------------- |
140/// | OCF1C | 1000 |
141/// | TOV1 | 1 |
142/// | ICF1 | 100000 |
143/// | OCF1A | 10 |
144/// | OCF1B | 100 |
145pub const TIFR1: *mut u8 = 0x36 as *mut u8;
146
147/// Timer/Counter Interrupt Flag Register.
148///
149/// Bitfields:
150///
151/// | Name | Mask (binary) |
152/// | ---- | ------------- |
153/// | TOV2 | 1 |
154/// | OCF2A | 10 |
155/// | OCF2B | 100 |
156pub const TIFR2: *mut u8 = 0x37 as *mut u8;
157
158/// Timer/Counter3 Interrupt Flag Register.
159///
160/// Bitfields:
161///
162/// | Name | Mask (binary) |
163/// | ---- | ------------- |
164/// | ICF3 | 100000 |
165/// | OCF3A | 10 |
166/// | OCF3B | 100 |
167/// | TOV3 | 1 |
168/// | OCF3C | 1000 |
169pub const TIFR3: *mut u8 = 0x38 as *mut u8;
170
171/// Timer/Counter4 Interrupt Flag Register.
172///
173/// Bitfields:
174///
175/// | Name | Mask (binary) |
176/// | ---- | ------------- |
177/// | OCF4C | 1000 |
178/// | TOV4 | 1 |
179/// | ICF4 | 100000 |
180/// | OCF4A | 10 |
181/// | OCF4B | 100 |
182pub const TIFR4: *mut u8 = 0x39 as *mut u8;
183
184/// Timer/Counter5 Interrupt Flag Register.
185///
186/// Bitfields:
187///
188/// | Name | Mask (binary) |
189/// | ---- | ------------- |
190/// | OCF5A | 10 |
191/// | OCF5B | 100 |
192/// | ICF5 | 100000 |
193/// | TOV5 | 1 |
194/// | OCF5C | 1000 |
195pub const TIFR5: *mut u8 = 0x3A as *mut u8;
196
197/// Pin Change Interrupt Flag Register.
198///
199/// Bitfields:
200///
201/// | Name | Mask (binary) |
202/// | ---- | ------------- |
203/// | PCIF | 111 |
204pub const PCIFR: *mut u8 = 0x3B as *mut u8;
205
206/// External Interrupt Flag Register.
207pub const EIFR: *mut u8 = 0x3C as *mut u8;
208
209/// External Interrupt Mask Register.
210pub const EIMSK: *mut u8 = 0x3D as *mut u8;
211
212/// General Purpose IO Register 0.
213///
214/// Bitfields:
215///
216/// | Name | Mask (binary) |
217/// | ---- | ------------- |
218/// | GPIOR01 | 10 |
219/// | GPIOR00 | 1 |
220/// | GPIOR07 | 10000000 |
221/// | GPIOR03 | 1000 |
222/// | GPIOR04 | 10000 |
223/// | GPIOR05 | 100000 |
224/// | GPIOR02 | 100 |
225/// | GPIOR06 | 1000000 |
226pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
227
228/// EEPROM Control Register.
229///
230/// Bitfields:
231///
232/// | Name | Mask (binary) |
233/// | ---- | ------------- |
234/// | EEPM | 110000 |
235/// | EEPE | 10 |
236/// | EEMPE | 100 |
237/// | EERE | 1 |
238/// | EERIE | 1000 |
239pub const EECR: *mut u8 = 0x3F as *mut u8;
240
241/// EEPROM Data Register.
242pub const EEDR: *mut u8 = 0x40 as *mut u8;
243
244/// EEPROM Address Register Bytes low byte.
245pub const EEARL: *mut u8 = 0x41 as *mut u8;
246
247/// EEPROM Address Register Bytes.
248pub const EEAR: *mut u16 = 0x41 as *mut u16;
249
250/// EEPROM Address Register Bytes high byte.
251pub const EEARH: *mut u8 = 0x42 as *mut u8;
252
253/// General Timer Counter Control register.
254///
255/// Bitfields:
256///
257/// | Name | Mask (binary) |
258/// | ---- | ------------- |
259/// | PSRASY | 10 |
260/// | TSM | 10000000 |
261pub const GTCCR: *mut u8 = 0x43 as *mut u8;
262
263/// Timer/Counter0 Control Register A.
264///
265/// Bitfields:
266///
267/// | Name | Mask (binary) |
268/// | ---- | ------------- |
269/// | COM0B | 110000 |
270/// | WGM0 | 11 |
271/// | COM0A | 11000000 |
272pub const TCCR0A: *mut u8 = 0x44 as *mut u8;
273
274/// Timer/Counter0 Control Register B.
275///
276/// Bitfields:
277///
278/// | Name | Mask (binary) |
279/// | ---- | ------------- |
280/// | CS0 | 111 |
281/// | WGM02 | 1000 |
282/// | FOC0A | 10000000 |
283/// | FOC0B | 1000000 |
284pub const TCCR0B: *mut u8 = 0x45 as *mut u8;
285
286/// Timer/Counter0 Register.
287pub const TCNT0: *mut u8 = 0x46 as *mut u8;
288
289/// Timer/Counter0 Output Compare Register.
290pub const OCR0A: *mut u8 = 0x47 as *mut u8;
291
292/// Timer/Counter0 Output Compare Register B.
293pub const OCR0B: *mut u8 = 0x48 as *mut u8;
294
295/// General Purpose IO Register 1.
296pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
297
298/// General Purpose I/O Register 2.
299pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
300
301/// SPI Control Register.
302///
303/// Bitfields:
304///
305/// | Name | Mask (binary) |
306/// | ---- | ------------- |
307/// | SPR | 11 |
308/// | SPE | 1000000 |
309/// | DORD | 100000 |
310/// | CPOL | 1000 |
311/// | CPHA | 100 |
312/// | SPIE | 10000000 |
313/// | MSTR | 10000 |
314pub const SPCR: *mut u8 = 0x4C as *mut u8;
315
316/// SPI Status Register.
317///
318/// Bitfields:
319///
320/// | Name | Mask (binary) |
321/// | ---- | ------------- |
322/// | WCOL | 1000000 |
323/// | SPIF | 10000000 |
324/// | SPI2X | 1 |
325pub const SPSR: *mut u8 = 0x4D as *mut u8;
326
327/// SPI Data Register.
328pub const SPDR: *mut u8 = 0x4E as *mut u8;
329
330/// Analog Comparator Control And Status Register.
331///
332/// Bitfields:
333///
334/// | Name | Mask (binary) |
335/// | ---- | ------------- |
336/// | ACO | 100000 |
337/// | ACIE | 1000 |
338/// | ACI | 10000 |
339/// | ACD | 10000000 |
340/// | ACIC | 100 |
341/// | ACBG | 1000000 |
342/// | ACIS | 11 |
343pub const ACSR: *mut u8 = 0x50 as *mut u8;
344
345/// On-Chip Debug Register.
346pub const OCDR: *mut u8 = 0x51 as *mut u8;
347
348/// Sleep Mode Control Register.
349///
350/// Bitfields:
351///
352/// | Name | Mask (binary) |
353/// | ---- | ------------- |
354/// | SE | 1 |
355/// | SM | 1110 |
356pub const SMCR: *mut u8 = 0x53 as *mut u8;
357
358/// MCU Status Register.
359///
360/// Bitfields:
361///
362/// | Name | Mask (binary) |
363/// | ---- | ------------- |
364/// | JTRF | 10000 |
365/// | EXTRF | 10 |
366/// | WDRF | 1000 |
367/// | BORF | 100 |
368/// | PORF | 1 |
369pub const MCUSR: *mut u8 = 0x54 as *mut u8;
370
371/// MCU Control Register.
372///
373/// Bitfields:
374///
375/// | Name | Mask (binary) |
376/// | ---- | ------------- |
377/// | PUD | 10000 |
378pub const MCUCR: *mut u8 = 0x55 as *mut u8;
379
380/// Store Program Memory Control Register.
381///
382/// Bitfields:
383///
384/// | Name | Mask (binary) |
385/// | ---- | ------------- |
386/// | PGWRT | 100 |
387/// | RWWSB | 1000000 |
388/// | PGERS | 10 |
389/// | BLBSET | 1000 |
390/// | RWWSRE | 10000 |
391/// | SPMEN | 1 |
392/// | SIGRD | 100000 |
393/// | SPMIE | 10000000 |
394pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
395
396/// Stack Pointer.
397pub const SP: *mut u16 = 0x5D as *mut u16;
398
399/// Stack Pointer low byte.
400pub const SPL: *mut u8 = 0x5D as *mut u8;
401
402/// Stack Pointer high byte.
403pub const SPH: *mut u8 = 0x5E as *mut u8;
404
405/// Status Register.
406///
407/// Bitfields:
408///
409/// | Name | Mask (binary) |
410/// | ---- | ------------- |
411/// | S | 10000 |
412/// | N | 100 |
413/// | V | 1000 |
414/// | C | 1 |
415/// | H | 100000 |
416/// | I | 10000000 |
417/// | T | 1000000 |
418/// | Z | 10 |
419pub const SREG: *mut u8 = 0x5F as *mut u8;
420
421/// Watchdog Timer Control Register.
422///
423/// Bitfields:
424///
425/// | Name | Mask (binary) |
426/// | ---- | ------------- |
427/// | WDCE | 10000 |
428/// | WDP | 100111 |
429/// | WDIE | 1000000 |
430/// | WDE | 1000 |
431/// | WDIF | 10000000 |
432pub const WDTCSR: *mut u8 = 0x60 as *mut u8;
433
434/// Clock Prescale Register.
435///
436/// Bitfields:
437///
438/// | Name | Mask (binary) |
439/// | ---- | ------------- |
440/// | CLKPCE | 10000000 |
441/// | CLKPS | 1111 |
442pub const CLKPR: *mut u8 = 0x61 as *mut u8;
443
444/// Power Reduction Register 2.
445///
446/// Bitfields:
447///
448/// | Name | Mask (binary) |
449/// | ---- | ------------- |
450/// | PRRAM2 | 100 |
451/// | PRRAM1 | 10 |
452/// | PRRAM3 | 1000 |
453/// | PRRAM0 | 1 |
454pub const PRR2: *mut u8 = 0x63 as *mut u8;
455
456/// Power Reduction Register0.
457///
458/// Bitfields:
459///
460/// | Name | Mask (binary) |
461/// | ---- | ------------- |
462/// | PRPGA | 10000 |
463/// | PRSPI | 100 |
464/// | PRTWI | 10000000 |
465/// | PRTIM1 | 1000 |
466/// | PRUSART0 | 10 |
467/// | PRTIM0 | 100000 |
468/// | PRADC | 1 |
469/// | PRTIM2 | 1000000 |
470pub const PRR0: *mut u8 = 0x64 as *mut u8;
471
472/// Power Reduction Register 1.
473///
474/// Bitfields:
475///
476/// | Name | Mask (binary) |
477/// | ---- | ------------- |
478/// | PRTIM5 | 100000 |
479/// | PRUSART1 | 1 |
480/// | PRTRX24 | 1000000 |
481/// | PRTIM3 | 1000 |
482/// | PRTIM4 | 10000 |
483pub const PRR1: *mut u8 = 0x65 as *mut u8;
484
485/// Oscillator Calibration Value.
486pub const OSCCAL: *mut u8 = 0x66 as *mut u8;
487
488/// Reference Voltage Calibration Register.
489///
490/// Bitfields:
491///
492/// | Name | Mask (binary) |
493/// | ---- | ------------- |
494/// | BGCAL_FINE | 1111000 |
495/// | BGCAL | 111 |
496pub const BGCR: *mut u8 = 0x67 as *mut u8;
497
498/// Pin Change Interrupt Control Register.
499///
500/// Bitfields:
501///
502/// | Name | Mask (binary) |
503/// | ---- | ------------- |
504/// | PCIE | 111 |
505pub const PCICR: *mut u8 = 0x68 as *mut u8;
506
507/// External Interrupt Control Register A.
508///
509/// Bitfields:
510///
511/// | Name | Mask (binary) |
512/// | ---- | ------------- |
513/// | ISC1 | 1100 |
514/// | ISC0 | 11 |
515/// | ISC3 | 11000000 |
516/// | ISC2 | 110000 |
517pub const EICRA: *mut u8 = 0x69 as *mut u8;
518
519/// External Interrupt Control Register B.
520///
521/// Bitfields:
522///
523/// | Name | Mask (binary) |
524/// | ---- | ------------- |
525/// | ISC5 | 1100 |
526/// | ISC7 | 11000000 |
527/// | ISC4 | 11 |
528/// | ISC6 | 110000 |
529pub const EICRB: *mut u8 = 0x6A as *mut u8;
530
531/// Pin Change Mask Register 0.
532pub const PCMSK0: *mut u8 = 0x6B as *mut u8;
533
534/// Pin Change Mask Register 1.
535pub const PCMSK1: *mut u8 = 0x6C as *mut u8;
536
537/// Pin Change Mask Register 2.
538pub const PCMSK2: *mut u8 = 0x6D as *mut u8;
539
540/// Timer/Counter0 Interrupt Mask Register.
541///
542/// Bitfields:
543///
544/// | Name | Mask (binary) |
545/// | ---- | ------------- |
546/// | OCIE0A | 10 |
547/// | OCIE0B | 100 |
548/// | TOIE0 | 1 |
549pub const TIMSK0: *mut u8 = 0x6E as *mut u8;
550
551/// Timer/Counter1 Interrupt Mask Register.
552///
553/// Bitfields:
554///
555/// | Name | Mask (binary) |
556/// | ---- | ------------- |
557/// | OCIE1B | 100 |
558/// | ICIE1 | 100000 |
559/// | OCIE1C | 1000 |
560/// | TOIE1 | 1 |
561/// | OCIE1A | 10 |
562pub const TIMSK1: *mut u8 = 0x6F as *mut u8;
563
564/// Timer/Counter Interrupt Mask register.
565///
566/// Bitfields:
567///
568/// | Name | Mask (binary) |
569/// | ---- | ------------- |
570/// | TOIE2 | 1 |
571/// | OCIE2A | 10 |
572/// | OCIE2B | 100 |
573pub const TIMSK2: *mut u8 = 0x70 as *mut u8;
574
575/// Timer/Counter3 Interrupt Mask Register.
576///
577/// Bitfields:
578///
579/// | Name | Mask (binary) |
580/// | ---- | ------------- |
581/// | TOIE3 | 1 |
582/// | ICIE3 | 100000 |
583/// | OCIE3A | 10 |
584/// | OCIE3C | 1000 |
585/// | OCIE3B | 100 |
586pub const TIMSK3: *mut u8 = 0x71 as *mut u8;
587
588/// Timer/Counter4 Interrupt Mask Register.
589///
590/// Bitfields:
591///
592/// | Name | Mask (binary) |
593/// | ---- | ------------- |
594/// | OCIE4B | 100 |
595/// | ICIE4 | 100000 |
596/// | OCIE4A | 10 |
597/// | OCIE4C | 1000 |
598/// | TOIE4 | 1 |
599pub const TIMSK4: *mut u8 = 0x72 as *mut u8;
600
601/// Timer/Counter5 Interrupt Mask Register.
602///
603/// Bitfields:
604///
605/// | Name | Mask (binary) |
606/// | ---- | ------------- |
607/// | OCIE5A | 10 |
608/// | OCIE5C | 1000 |
609/// | ICIE5 | 100000 |
610/// | OCIE5B | 100 |
611/// | TOIE5 | 1 |
612pub const TIMSK5: *mut u8 = 0x73 as *mut u8;
613
614/// Flash Extended-Mode Control-Register.
615///
616/// Bitfields:
617///
618/// | Name | Mask (binary) |
619/// | ---- | ------------- |
620/// | ENEAM | 1000000 |
621/// | AEAM | 110000 |
622pub const NEMCR: *mut u8 = 0x75 as *mut u8;
623
624/// The ADC Control and Status Register C.
625///
626/// Bitfields:
627///
628/// | Name | Mask (binary) |
629/// | ---- | ------------- |
630/// | ADSUT | 11111 |
631/// | ADTHT | 11000000 |
632pub const ADCSRC: *mut u8 = 0x77 as *mut u8;
633
634/// ADC Data Register Bytes.
635pub const ADC: *mut u16 = 0x78 as *mut u16;
636
637/// ADC Data Register Bytes low byte.
638pub const ADCL: *mut u8 = 0x78 as *mut u8;
639
640/// ADC Data Register Bytes high byte.
641pub const ADCH: *mut u8 = 0x79 as *mut u8;
642
643/// The ADC Control and Status Register A.
644///
645/// Bitfields:
646///
647/// | Name | Mask (binary) |
648/// | ---- | ------------- |
649/// | ADIE | 1000 |
650/// | ADPS | 111 |
651/// | ADATE | 100000 |
652/// | ADEN | 10000000 |
653/// | ADSC | 1000000 |
654/// | ADIF | 10000 |
655pub const ADCSRA: *mut u8 = 0x7A as *mut u8;
656
657/// The ADC Control and Status Register B.
658///
659/// Bitfields:
660///
661/// | Name | Mask (binary) |
662/// | ---- | ------------- |
663/// | AVDDOK | 10000000 |
664/// | MUX5 | 1000 |
665/// | ACCH | 10000 |
666/// | REFOK | 100000 |
667/// | ADTS | 111 |
668/// | ACME | 1000000 |
669pub const ADCSRB: *mut u8 = 0x7B as *mut u8;
670
671/// The ADC Multiplexer Selection Register.
672///
673/// Bitfields:
674///
675/// | Name | Mask (binary) |
676/// | ---- | ------------- |
677/// | MUX | 11111 |
678/// | REFS | 11000000 |
679/// | ADLAR | 100000 |
680pub const ADMUX: *mut u8 = 0x7C as *mut u8;
681
682/// Digital Input Disable Register 2.
683///
684/// Bitfields:
685///
686/// | Name | Mask (binary) |
687/// | ---- | ------------- |
688/// | ADC10D | 100 |
689/// | ADC11D | 1000 |
690/// | ADC12D | 10000 |
691/// | ADC14D | 1000000 |
692/// | ADC15D | 10000000 |
693/// | ADC8D | 1 |
694/// | ADC9D | 10 |
695/// | ADC13D | 100000 |
696pub const DIDR2: *mut u8 = 0x7D as *mut u8;
697
698/// Digital Input Disable Register 0.
699///
700/// Bitfields:
701///
702/// | Name | Mask (binary) |
703/// | ---- | ------------- |
704/// | ADC4D | 10000 |
705/// | ADC5D | 100000 |
706/// | ADC0D | 1 |
707/// | ADC6D | 1000000 |
708/// | ADC3D | 1000 |
709/// | ADC2D | 100 |
710/// | ADC1D | 10 |
711/// | ADC7D | 10000000 |
712pub const DIDR0: *mut u8 = 0x7E as *mut u8;
713
714/// Digital Input Disable Register 1.
715///
716/// Bitfields:
717///
718/// | Name | Mask (binary) |
719/// | ---- | ------------- |
720/// | AIN1D | 10 |
721/// | AIN0D | 1 |
722pub const DIDR1: *mut u8 = 0x7F as *mut u8;
723
724/// Timer/Counter1 Control Register A.
725///
726/// Bitfields:
727///
728/// | Name | Mask (binary) |
729/// | ---- | ------------- |
730/// | COM1C | 1100 |
731/// | COM1B | 110000 |
732/// | COM1A | 11000000 |
733pub const TCCR1A: *mut u8 = 0x80 as *mut u8;
734
735/// Timer/Counter1 Control Register B.
736///
737/// Bitfields:
738///
739/// | Name | Mask (binary) |
740/// | ---- | ------------- |
741/// | ICNC1 | 10000000 |
742/// | CS1 | 111 |
743/// | ICES1 | 1000000 |
744pub const TCCR1B: *mut u8 = 0x81 as *mut u8;
745
746/// Timer/Counter1 Control Register C.
747///
748/// Bitfields:
749///
750/// | Name | Mask (binary) |
751/// | ---- | ------------- |
752/// | FOC1A | 10000000 |
753/// | FOC1B | 1000000 |
754/// | FOC1C | 100000 |
755pub const TCCR1C: *mut u8 = 0x82 as *mut u8;
756
757/// Timer/Counter1 Bytes low byte.
758pub const TCNT1L: *mut u8 = 0x84 as *mut u8;
759
760/// Timer/Counter1 Bytes.
761pub const TCNT1: *mut u16 = 0x84 as *mut u16;
762
763/// Timer/Counter1 Bytes high byte.
764pub const TCNT1H: *mut u8 = 0x85 as *mut u8;
765
766/// Timer/Counter1 Input Capture Register Bytes low byte.
767pub const ICR1L: *mut u8 = 0x86 as *mut u8;
768
769/// Timer/Counter1 Input Capture Register Bytes.
770pub const ICR1: *mut u16 = 0x86 as *mut u16;
771
772/// Timer/Counter1 Input Capture Register Bytes high byte.
773pub const ICR1H: *mut u8 = 0x87 as *mut u8;
774
775/// Timer/Counter1 Output Compare Register A Bytes.
776pub const OCR1A: *mut u16 = 0x88 as *mut u16;
777
778/// Timer/Counter1 Output Compare Register A Bytes low byte.
779pub const OCR1AL: *mut u8 = 0x88 as *mut u8;
780
781/// Timer/Counter1 Output Compare Register A Bytes high byte.
782pub const OCR1AH: *mut u8 = 0x89 as *mut u8;
783
784/// Timer/Counter1 Output Compare Register B Bytes low byte.
785pub const OCR1BL: *mut u8 = 0x8A as *mut u8;
786
787/// Timer/Counter1 Output Compare Register B Bytes.
788pub const OCR1B: *mut u16 = 0x8A as *mut u16;
789
790/// Timer/Counter1 Output Compare Register B Bytes high byte.
791pub const OCR1BH: *mut u8 = 0x8B as *mut u8;
792
793/// Timer/Counter1 Output Compare Register C Bytes.
794pub const OCR1C: *mut u16 = 0x8C as *mut u16;
795
796/// Timer/Counter1 Output Compare Register C Bytes low byte.
797pub const OCR1CL: *mut u8 = 0x8C as *mut u8;
798
799/// Timer/Counter1 Output Compare Register C Bytes high byte.
800pub const OCR1CH: *mut u8 = 0x8D as *mut u8;
801
802/// Timer/Counter3 Control Register A.
803///
804/// Bitfields:
805///
806/// | Name | Mask (binary) |
807/// | ---- | ------------- |
808/// | COM3A | 11000000 |
809/// | COM3C | 1100 |
810/// | COM3B | 110000 |
811pub const TCCR3A: *mut u8 = 0x90 as *mut u8;
812
813/// Timer/Counter3 Control Register B.
814///
815/// Bitfields:
816///
817/// | Name | Mask (binary) |
818/// | ---- | ------------- |
819/// | CS3 | 111 |
820/// | ICNC3 | 10000000 |
821/// | ICES3 | 1000000 |
822pub const TCCR3B: *mut u8 = 0x91 as *mut u8;
823
824/// Timer/Counter3 Control Register C.
825///
826/// Bitfields:
827///
828/// | Name | Mask (binary) |
829/// | ---- | ------------- |
830/// | FOC3A | 10000000 |
831/// | FOC3C | 100000 |
832/// | FOC3B | 1000000 |
833pub const TCCR3C: *mut u8 = 0x92 as *mut u8;
834
835/// Timer/Counter3 Bytes.
836pub const TCNT3: *mut u16 = 0x94 as *mut u16;
837
838/// Timer/Counter3 Bytes low byte.
839pub const TCNT3L: *mut u8 = 0x94 as *mut u8;
840
841/// Timer/Counter3 Bytes high byte.
842pub const TCNT3H: *mut u8 = 0x95 as *mut u8;
843
844/// Timer/Counter3 Input Capture Register Bytes low byte.
845pub const ICR3L: *mut u8 = 0x96 as *mut u8;
846
847/// Timer/Counter3 Input Capture Register Bytes.
848pub const ICR3: *mut u16 = 0x96 as *mut u16;
849
850/// Timer/Counter3 Input Capture Register Bytes high byte.
851pub const ICR3H: *mut u8 = 0x97 as *mut u8;
852
853/// Timer/Counter3 Output Compare Register A Bytes.
854pub const OCR3A: *mut u16 = 0x98 as *mut u16;
855
856/// Timer/Counter3 Output Compare Register A Bytes low byte.
857pub const OCR3AL: *mut u8 = 0x98 as *mut u8;
858
859/// Timer/Counter3 Output Compare Register A Bytes high byte.
860pub const OCR3AH: *mut u8 = 0x99 as *mut u8;
861
862/// Timer/Counter3 Output Compare Register B Bytes low byte.
863pub const OCR3BL: *mut u8 = 0x9A as *mut u8;
864
865/// Timer/Counter3 Output Compare Register B Bytes.
866pub const OCR3B: *mut u16 = 0x9A as *mut u16;
867
868/// Timer/Counter3 Output Compare Register B Bytes high byte.
869pub const OCR3BH: *mut u8 = 0x9B as *mut u8;
870
871/// Timer/Counter3 Output Compare Register C Bytes low byte.
872pub const OCR3CL: *mut u8 = 0x9C as *mut u8;
873
874/// Timer/Counter3 Output Compare Register C Bytes.
875pub const OCR3C: *mut u16 = 0x9C as *mut u16;
876
877/// Timer/Counter3 Output Compare Register C Bytes high byte.
878pub const OCR3CH: *mut u8 = 0x9D as *mut u8;
879
880/// Timer/Counter4 Control Register A.
881///
882/// Bitfields:
883///
884/// | Name | Mask (binary) |
885/// | ---- | ------------- |
886/// | COM4A | 11000000 |
887/// | COM4C | 1100 |
888/// | COM4B | 110000 |
889pub const TCCR4A: *mut u8 = 0xA0 as *mut u8;
890
891/// Timer/Counter4 Control Register B.
892///
893/// Bitfields:
894///
895/// | Name | Mask (binary) |
896/// | ---- | ------------- |
897/// | ICNC4 | 10000000 |
898/// | ICES4 | 1000000 |
899/// | CS4 | 111 |
900pub const TCCR4B: *mut u8 = 0xA1 as *mut u8;
901
902/// Timer/Counter4 Control Register C.
903///
904/// Bitfields:
905///
906/// | Name | Mask (binary) |
907/// | ---- | ------------- |
908/// | FOC4A | 10000000 |
909/// | FOC4B | 1000000 |
910/// | FOC4C | 100000 |
911pub const TCCR4C: *mut u8 = 0xA2 as *mut u8;
912
913/// Timer/Counter4 Bytes low byte.
914pub const TCNT4L: *mut u8 = 0xA4 as *mut u8;
915
916/// Timer/Counter4 Bytes.
917pub const TCNT4: *mut u16 = 0xA4 as *mut u16;
918
919/// Timer/Counter4 Bytes high byte.
920pub const TCNT4H: *mut u8 = 0xA5 as *mut u8;
921
922/// Timer/Counter4 Input Capture Register Bytes.
923pub const ICR4: *mut u16 = 0xA6 as *mut u16;
924
925/// Timer/Counter4 Input Capture Register Bytes low byte.
926pub const ICR4L: *mut u8 = 0xA6 as *mut u8;
927
928/// Timer/Counter4 Input Capture Register Bytes high byte.
929pub const ICR4H: *mut u8 = 0xA7 as *mut u8;
930
931/// Timer/Counter4 Output Compare Register A Bytes low byte.
932pub const OCR4AL: *mut u8 = 0xA8 as *mut u8;
933
934/// Timer/Counter4 Output Compare Register A Bytes.
935pub const OCR4A: *mut u16 = 0xA8 as *mut u16;
936
937/// Timer/Counter4 Output Compare Register A Bytes high byte.
938pub const OCR4AH: *mut u8 = 0xA9 as *mut u8;
939
940/// Timer/Counter4 Output Compare Register B Bytes low byte.
941pub const OCR4BL: *mut u8 = 0xAA as *mut u8;
942
943/// Timer/Counter4 Output Compare Register B Bytes.
944pub const OCR4B: *mut u16 = 0xAA as *mut u16;
945
946/// Timer/Counter4 Output Compare Register B Bytes high byte.
947pub const OCR4BH: *mut u8 = 0xAB as *mut u8;
948
949/// Timer/Counter4 Output Compare Register C Bytes low byte.
950pub const OCR4CL: *mut u8 = 0xAC as *mut u8;
951
952/// Timer/Counter4 Output Compare Register C Bytes.
953pub const OCR4C: *mut u16 = 0xAC as *mut u16;
954
955/// Timer/Counter4 Output Compare Register C Bytes high byte.
956pub const OCR4CH: *mut u8 = 0xAD as *mut u8;
957
958/// Timer/Counter2 Control Register A.
959///
960/// Bitfields:
961///
962/// | Name | Mask (binary) |
963/// | ---- | ------------- |
964/// | WGM2 | 11 |
965/// | COM2A | 11000000 |
966/// | COM2B | 110000 |
967pub const TCCR2A: *mut u8 = 0xB0 as *mut u8;
968
969/// Timer/Counter2 Control Register B.
970///
971/// Bitfields:
972///
973/// | Name | Mask (binary) |
974/// | ---- | ------------- |
975/// | FOC2B | 1000000 |
976/// | WGM22 | 1000 |
977/// | FOC2A | 10000000 |
978/// | CS2 | 111 |
979pub const TCCR2B: *mut u8 = 0xB1 as *mut u8;
980
981/// Timer/Counter2.
982pub const TCNT2: *mut u8 = 0xB2 as *mut u8;
983
984/// Timer/Counter2 Output Compare Register A.
985pub const OCR2A: *mut u8 = 0xB3 as *mut u8;
986
987/// Timer/Counter2 Output Compare Register B.
988pub const OCR2B: *mut u8 = 0xB4 as *mut u8;
989
990/// Asynchronous Status Register.
991///
992/// Bitfields:
993///
994/// | Name | Mask (binary) |
995/// | ---- | ------------- |
996/// | AS2 | 100000 |
997/// | TCN2UB | 10000 |
998/// | TCR2BUB | 1 |
999/// | OCR2AUB | 1000 |
1000/// | OCR2BUB | 100 |
1001/// | EXCLK | 1000000 |
1002/// | EXCLKAMR | 10000000 |
1003/// | TCR2AUB | 10 |
1004pub const ASSR: *mut u8 = 0xB6 as *mut u8;
1005
1006/// TWI Bit Rate Register.
1007pub const TWBR: *mut u8 = 0xB8 as *mut u8;
1008
1009/// TWI Status Register.
1010///
1011/// Bitfields:
1012///
1013/// | Name | Mask (binary) |
1014/// | ---- | ------------- |
1015/// | TWS | 11111000 |
1016/// | TWPS | 11 |
1017pub const TWSR: *mut u8 = 0xB9 as *mut u8;
1018
1019/// TWI (Slave) Address Register.
1020///
1021/// Bitfields:
1022///
1023/// | Name | Mask (binary) |
1024/// | ---- | ------------- |
1025/// | TWA | 11111110 |
1026/// | TWGCE | 1 |
1027pub const TWAR: *mut u8 = 0xBA as *mut u8;
1028
1029/// TWI Data Register.
1030pub const TWDR: *mut u8 = 0xBB as *mut u8;
1031
1032/// TWI Control Register.
1033///
1034/// Bitfields:
1035///
1036/// | Name | Mask (binary) |
1037/// | ---- | ------------- |
1038/// | TWEA | 1000000 |
1039/// | TWSTO | 10000 |
1040/// | TWIE | 1 |
1041/// | TWINT | 10000000 |
1042/// | TWWC | 1000 |
1043/// | TWEN | 100 |
1044/// | TWSTA | 100000 |
1045pub const TWCR: *mut u8 = 0xBC as *mut u8;
1046
1047/// TWI (Slave) Address Mask Register.
1048///
1049/// Bitfields:
1050///
1051/// | Name | Mask (binary) |
1052/// | ---- | ------------- |
1053/// | TWAM | 11111110 |
1054pub const TWAMR: *mut u8 = 0xBD as *mut u8;
1055
1056/// Transceiver Interrupt Enable Register 1.
1057///
1058/// Bitfields:
1059///
1060/// | Name | Mask (binary) |
1061/// | ---- | ------------- |
1062/// | MAF_2_AMI_EN | 1000 |
1063/// | TX_START_EN | 1 |
1064/// | MAF_3_AMI_EN | 10000 |
1065/// | MAF_1_AMI_EN | 100 |
1066/// | MAF_0_AMI_EN | 10 |
1067pub const IRQ_MASK1: *mut u8 = 0xBE as *mut u8;
1068
1069/// Transceiver Interrupt Status Register 1.
1070///
1071/// Bitfields:
1072///
1073/// | Name | Mask (binary) |
1074/// | ---- | ------------- |
1075/// | MAF_3_AMI | 10000 |
1076/// | MAF_1_AMI | 100 |
1077/// | TX_START | 1 |
1078/// | MAF_2_AMI | 1000 |
1079/// | MAF_0_AMI | 10 |
1080pub const IRQ_STATUS1: *mut u8 = 0xBF as *mut u8;
1081
1082/// USART0 MSPIM Control and Status Register A.
1083///
1084/// Bitfields:
1085///
1086/// | Name | Mask (binary) |
1087/// | ---- | ------------- |
1088/// | TXC0 | 1000000 |
1089/// | UDRE0 | 100000 |
1090/// | RXC0 | 10000000 |
1091pub const UCSR0A: *mut u8 = 0xC0 as *mut u8;
1092
1093/// USART0 MSPIM Control and Status Register B.
1094///
1095/// Bitfields:
1096///
1097/// | Name | Mask (binary) |
1098/// | ---- | ------------- |
1099/// | UDRIE0 | 100000 |
1100/// | TXEN0 | 1000 |
1101/// | RXEN0 | 10000 |
1102/// | RXCIE0 | 10000000 |
1103/// | TXCIE0 | 1000000 |
1104pub const UCSR0B: *mut u8 = 0xC1 as *mut u8;
1105
1106/// USART0 MSPIM Control and Status Register C.
1107///
1108/// Bitfields:
1109///
1110/// | Name | Mask (binary) |
1111/// | ---- | ------------- |
1112/// | UDORD0 | 100 |
1113/// | UCPOL0 | 1 |
1114/// | UCPHA0 | 10 |
1115pub const UCSR0C: *mut u8 = 0xC2 as *mut u8;
1116
1117/// USART0 Baud Rate Register Bytes low byte.
1118pub const UBRR0L: *mut u8 = 0xC4 as *mut u8;
1119
1120/// USART0 Baud Rate Register Bytes.
1121pub const UBRR0: *mut u16 = 0xC4 as *mut u16;
1122
1123/// USART0 Baud Rate Register Bytes high byte.
1124pub const UBRR0H: *mut u8 = 0xC5 as *mut u8;
1125
1126/// USART0 I/O Data Register.
1127pub const UDR0: *mut u8 = 0xC6 as *mut u8;
1128
1129/// USART1 MSPIM Control and Status Register A.
1130///
1131/// Bitfields:
1132///
1133/// | Name | Mask (binary) |
1134/// | ---- | ------------- |
1135/// | RXC1 | 10000000 |
1136/// | UDRE1 | 100000 |
1137/// | TXC1 | 1000000 |
1138pub const UCSR1A: *mut u8 = 0xC8 as *mut u8;
1139
1140/// USART1 MSPIM Control and Status Register B.
1141///
1142/// Bitfields:
1143///
1144/// | Name | Mask (binary) |
1145/// | ---- | ------------- |
1146/// | TXCIE1 | 1000000 |
1147/// | UDRIE1 | 100000 |
1148/// | TXEN1 | 1000 |
1149/// | RXEN1 | 10000 |
1150/// | RXCIE1 | 10000000 |
1151pub const UCSR1B: *mut u8 = 0xC9 as *mut u8;
1152
1153/// USART1 MSPIM Control and Status Register C.
1154///
1155/// Bitfields:
1156///
1157/// | Name | Mask (binary) |
1158/// | ---- | ------------- |
1159/// | UCPHA1 | 10 |
1160/// | UDORD1 | 100 |
1161/// | UCPOL1 | 1 |
1162pub const UCSR1C: *mut u8 = 0xCA as *mut u8;
1163
1164/// USART1 Baud Rate Register Bytes low byte.
1165pub const UBRR1L: *mut u8 = 0xCC as *mut u8;
1166
1167/// USART1 Baud Rate Register Bytes.
1168pub const UBRR1: *mut u16 = 0xCC as *mut u16;
1169
1170/// USART1 Baud Rate Register Bytes high byte.
1171pub const UBRR1H: *mut u8 = 0xCD as *mut u8;
1172
1173/// USART1 I/O Data Register.
1174pub const UDR1: *mut u8 = 0xCE as *mut u8;
1175
1176/// Symbol Counter Received Frame Timestamp Register LL-Byte.
1177pub const SCRSTRLL: *mut u8 = 0xD7 as *mut u8;
1178
1179/// Symbol Counter Received Frame Timestamp Register LH-Byte.
1180pub const SCRSTRLH: *mut u8 = 0xD8 as *mut u8;
1181
1182/// Symbol Counter Received Frame Timestamp Register HL-Byte.
1183pub const SCRSTRHL: *mut u8 = 0xD9 as *mut u8;
1184
1185/// Symbol Counter Received Frame Timestamp Register HH-Byte.
1186pub const SCRSTRHH: *mut u8 = 0xDA as *mut u8;
1187
1188/// Symbol Counter Compare Source Register.
1189///
1190/// Bitfields:
1191///
1192/// | Name | Mask (binary) |
1193/// | ---- | ------------- |
1194/// | SCCS2 | 1100 |
1195/// | SCCS3 | 110000 |
1196/// | SCCS1 | 11 |
1197pub const SCCSR: *mut u8 = 0xDB as *mut u8;
1198
1199/// Symbol Counter Control Register 0.
1200///
1201/// Bitfields:
1202///
1203/// | Name | Mask (binary) |
1204/// | ---- | ------------- |
1205/// | SCCMP | 111 |
1206/// | SCRES | 10000000 |
1207/// | SCTSE | 1000 |
1208/// | SCEN | 100000 |
1209/// | SCMBTS | 1000000 |
1210/// | SCCKSEL | 10000 |
1211pub const SCCR0: *mut u8 = 0xDC as *mut u8;
1212
1213/// Symbol Counter Control Register 1.
1214///
1215/// Bitfields:
1216///
1217/// | Name | Mask (binary) |
1218/// | ---- | ------------- |
1219/// | SCENBO | 1 |
1220/// | SCCKDIV | 11100 |
1221/// | SCBTSM | 100000 |
1222/// | SCEECLK | 10 |
1223pub const SCCR1: *mut u8 = 0xDD as *mut u8;
1224
1225/// Symbol Counter Status Register.
1226///
1227/// Bitfields:
1228///
1229/// | Name | Mask (binary) |
1230/// | ---- | ------------- |
1231/// | SCBSY | 1 |
1232pub const SCSR: *mut u8 = 0xDE as *mut u8;
1233
1234/// Symbol Counter Interrupt Mask Register.
1235///
1236/// Bitfields:
1237///
1238/// | Name | Mask (binary) |
1239/// | ---- | ------------- |
1240/// | IRQMBO | 10000 |
1241/// | IRQMOF | 1000 |
1242/// | IRQMCP | 111 |
1243pub const SCIRQM: *mut u8 = 0xDF as *mut u8;
1244
1245/// Symbol Counter Interrupt Status Register.
1246///
1247/// Bitfields:
1248///
1249/// | Name | Mask (binary) |
1250/// | ---- | ------------- |
1251/// | IRQSCP | 111 |
1252/// | IRQSBO | 10000 |
1253/// | IRQSOF | 1000 |
1254pub const SCIRQS: *mut u8 = 0xE0 as *mut u8;
1255
1256/// Symbol Counter Register LL-Byte.
1257pub const SCCNTLL: *mut u8 = 0xE1 as *mut u8;
1258
1259/// Symbol Counter Register LH-Byte.
1260pub const SCCNTLH: *mut u8 = 0xE2 as *mut u8;
1261
1262/// Symbol Counter Register HL-Byte.
1263pub const SCCNTHL: *mut u8 = 0xE3 as *mut u8;
1264
1265/// Symbol Counter Register HH-Byte.
1266pub const SCCNTHH: *mut u8 = 0xE4 as *mut u8;
1267
1268/// Symbol Counter Beacon Timestamp Register LL-Byte.
1269pub const SCBTSRLL: *mut u8 = 0xE5 as *mut u8;
1270
1271/// Symbol Counter Beacon Timestamp Register LH-Byte.
1272pub const SCBTSRLH: *mut u8 = 0xE6 as *mut u8;
1273
1274/// Symbol Counter Beacon Timestamp Register HL-Byte.
1275pub const SCBTSRHL: *mut u8 = 0xE7 as *mut u8;
1276
1277/// Symbol Counter Beacon Timestamp Register HH-Byte.
1278pub const SCBTSRHH: *mut u8 = 0xE8 as *mut u8;
1279
1280/// Symbol Counter Frame Timestamp Register LL-Byte.
1281pub const SCTSRLL: *mut u8 = 0xE9 as *mut u8;
1282
1283/// Symbol Counter Frame Timestamp Register LH-Byte.
1284pub const SCTSRLH: *mut u8 = 0xEA as *mut u8;
1285
1286/// Symbol Counter Frame Timestamp Register HL-Byte.
1287pub const SCTSRHL: *mut u8 = 0xEB as *mut u8;
1288
1289/// Symbol Counter Frame Timestamp Register HH-Byte.
1290pub const SCTSRHH: *mut u8 = 0xEC as *mut u8;
1291
1292/// Symbol Counter Output Compare Register 3 LL-Byte.
1293pub const SCOCR3LL: *mut u8 = 0xED as *mut u8;
1294
1295/// Symbol Counter Output Compare Register 3 LH-Byte.
1296pub const SCOCR3LH: *mut u8 = 0xEE as *mut u8;
1297
1298/// Symbol Counter Output Compare Register 3 HL-Byte.
1299pub const SCOCR3HL: *mut u8 = 0xEF as *mut u8;
1300
1301/// Symbol Counter Output Compare Register 3 HH-Byte.
1302pub const SCOCR3HH: *mut u8 = 0xF0 as *mut u8;
1303
1304/// Symbol Counter Output Compare Register 2 LL-Byte.
1305pub const SCOCR2LL: *mut u8 = 0xF1 as *mut u8;
1306
1307/// Symbol Counter Output Compare Register 2 LH-Byte.
1308pub const SCOCR2LH: *mut u8 = 0xF2 as *mut u8;
1309
1310/// Symbol Counter Output Compare Register 2 HL-Byte.
1311pub const SCOCR2HL: *mut u8 = 0xF3 as *mut u8;
1312
1313/// Symbol Counter Output Compare Register 2 HH-Byte.
1314pub const SCOCR2HH: *mut u8 = 0xF4 as *mut u8;
1315
1316/// Symbol Counter Output Compare Register 1 LL-Byte.
1317pub const SCOCR1LL: *mut u8 = 0xF5 as *mut u8;
1318
1319/// Symbol Counter Output Compare Register 1 LH-Byte.
1320pub const SCOCR1LH: *mut u8 = 0xF6 as *mut u8;
1321
1322/// Symbol Counter Output Compare Register 1 HL-Byte.
1323pub const SCOCR1HL: *mut u8 = 0xF7 as *mut u8;
1324
1325/// Symbol Counter Output Compare Register 1 HH-Byte.
1326pub const SCOCR1HH: *mut u8 = 0xF8 as *mut u8;
1327
1328/// Symbol Counter Transmit Frame Timestamp Register LL-Byte.
1329pub const SCTSTRLL: *mut u8 = 0xF9 as *mut u8;
1330
1331/// Symbol Counter Transmit Frame Timestamp Register LH-Byte.
1332pub const SCTSTRLH: *mut u8 = 0xFA as *mut u8;
1333
1334/// Symbol Counter Transmit Frame Timestamp Register HL-Byte.
1335pub const SCTSTRHL: *mut u8 = 0xFB as *mut u8;
1336
1337/// Symbol Counter Transmit Frame Timestamp Register HH-Byte.
1338pub const SCTSTRHH: *mut u8 = 0xFC as *mut u8;
1339
1340/// Multiple Address Filter Configuration Register 0.
1341///
1342/// Bitfields:
1343///
1344/// | Name | Mask (binary) |
1345/// | ---- | ------------- |
1346/// | MAF0EN | 1 |
1347/// | MAF2EN | 100 |
1348/// | MAF3EN | 1000 |
1349/// | MAF1EN | 10 |
1350pub const MAFCR0: *mut u8 = 0x10C as *mut u8;
1351
1352/// Multiple Address Filter Configuration Register 1.
1353///
1354/// Bitfields:
1355///
1356/// | Name | Mask (binary) |
1357/// | ---- | ------------- |
1358/// | AACK_2_I_AM_COORD | 10000 |
1359/// | AACK_3_SET_PD | 10000000 |
1360/// | AACK_0_I_AM_COORD | 1 |
1361/// | AACK_1_I_AM_COORD | 100 |
1362/// | AACK_1_SET_PD | 1000 |
1363/// | AACK_0_SET_PD | 10 |
1364/// | AACK_2_SET_PD | 100000 |
1365/// | AACK_3_I_AM_COORD | 1000000 |
1366pub const MAFCR1: *mut u8 = 0x10D as *mut u8;
1367
1368/// Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte).
1369pub const MAFSA0L: *mut u8 = 0x10E as *mut u8;
1370
1371/// Transceiver MAC Short Address Register for Frame Filter 0 (High Byte).
1372pub const MAFSA0H: *mut u8 = 0x10F as *mut u8;
1373
1374/// Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte).
1375pub const MAFPA0L: *mut u8 = 0x110 as *mut u8;
1376
1377/// Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte).
1378pub const MAFPA0H: *mut u8 = 0x111 as *mut u8;
1379
1380/// Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte).
1381pub const MAFSA1L: *mut u8 = 0x112 as *mut u8;
1382
1383/// Transceiver MAC Short Address Register for Frame Filter 1 (High Byte).
1384pub const MAFSA1H: *mut u8 = 0x113 as *mut u8;
1385
1386/// Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte).
1387pub const MAFPA1L: *mut u8 = 0x114 as *mut u8;
1388
1389/// Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte).
1390pub const MAFPA1H: *mut u8 = 0x115 as *mut u8;
1391
1392/// Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte).
1393pub const MAFSA2L: *mut u8 = 0x116 as *mut u8;
1394
1395/// Transceiver MAC Short Address Register for Frame Filter 2 (High Byte).
1396pub const MAFSA2H: *mut u8 = 0x117 as *mut u8;
1397
1398/// Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte).
1399pub const MAFPA2L: *mut u8 = 0x118 as *mut u8;
1400
1401/// Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte).
1402pub const MAFPA2H: *mut u8 = 0x119 as *mut u8;
1403
1404/// Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte).
1405pub const MAFSA3L: *mut u8 = 0x11A as *mut u8;
1406
1407/// Transceiver MAC Short Address Register for Frame Filter 3 (High Byte).
1408pub const MAFSA3H: *mut u8 = 0x11B as *mut u8;
1409
1410/// Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte).
1411pub const MAFPA3L: *mut u8 = 0x11C as *mut u8;
1412
1413/// Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte).
1414pub const MAFPA3H: *mut u8 = 0x11D as *mut u8;
1415
1416/// Timer/Counter5 Control Register A.
1417///
1418/// Bitfields:
1419///
1420/// | Name | Mask (binary) |
1421/// | ---- | ------------- |
1422/// | COM5A | 11000000 |
1423/// | COM5B | 110000 |
1424/// | COM5C | 1100 |
1425pub const TCCR5A: *mut u8 = 0x120 as *mut u8;
1426
1427/// Timer/Counter5 Control Register B.
1428///
1429/// Bitfields:
1430///
1431/// | Name | Mask (binary) |
1432/// | ---- | ------------- |
1433/// | ICNC5 | 10000000 |
1434/// | CS5 | 111 |
1435/// | ICES5 | 1000000 |
1436pub const TCCR5B: *mut u8 = 0x121 as *mut u8;
1437
1438/// Timer/Counter5 Control Register C.
1439///
1440/// Bitfields:
1441///
1442/// | Name | Mask (binary) |
1443/// | ---- | ------------- |
1444/// | FOC5C | 100000 |
1445/// | FOC5B | 1000000 |
1446/// | FOC5A | 10000000 |
1447pub const TCCR5C: *mut u8 = 0x122 as *mut u8;
1448
1449/// Timer/Counter5 Bytes low byte.
1450pub const TCNT5L: *mut u8 = 0x124 as *mut u8;
1451
1452/// Timer/Counter5 Bytes.
1453pub const TCNT5: *mut u16 = 0x124 as *mut u16;
1454
1455/// Timer/Counter5 Bytes high byte.
1456pub const TCNT5H: *mut u8 = 0x125 as *mut u8;
1457
1458/// Timer/Counter5 Input Capture Register Bytes low byte.
1459pub const ICR5L: *mut u8 = 0x126 as *mut u8;
1460
1461/// Timer/Counter5 Input Capture Register Bytes.
1462pub const ICR5: *mut u16 = 0x126 as *mut u16;
1463
1464/// Timer/Counter5 Input Capture Register Bytes high byte.
1465pub const ICR5H: *mut u8 = 0x127 as *mut u8;
1466
1467/// Timer/Counter5 Output Compare Register A Bytes.
1468pub const OCR5A: *mut u16 = 0x128 as *mut u16;
1469
1470/// Timer/Counter5 Output Compare Register A Bytes low byte.
1471pub const OCR5AL: *mut u8 = 0x128 as *mut u8;
1472
1473/// Timer/Counter5 Output Compare Register A Bytes high byte.
1474pub const OCR5AH: *mut u8 = 0x129 as *mut u8;
1475
1476/// Timer/Counter5 Output Compare Register B Bytes low byte.
1477pub const OCR5BL: *mut u8 = 0x12A as *mut u8;
1478
1479/// Timer/Counter5 Output Compare Register B Bytes.
1480pub const OCR5B: *mut u16 = 0x12A as *mut u16;
1481
1482/// Timer/Counter5 Output Compare Register B Bytes high byte.
1483pub const OCR5BH: *mut u8 = 0x12B as *mut u8;
1484
1485/// Timer/Counter5 Output Compare Register C Bytes.
1486pub const OCR5C: *mut u16 = 0x12C as *mut u16;
1487
1488/// Timer/Counter5 Output Compare Register C Bytes low byte.
1489pub const OCR5CL: *mut u8 = 0x12C as *mut u8;
1490
1491/// Timer/Counter5 Output Compare Register C Bytes high byte.
1492pub const OCR5CH: *mut u8 = 0x12D as *mut u8;
1493
1494/// Low Leakage Voltage Regulator Control Register.
1495///
1496/// Bitfields:
1497///
1498/// | Name | Mask (binary) |
1499/// | ---- | ------------- |
1500/// | LLTCO | 100 |
1501/// | LLCAL | 1000 |
1502/// | LLDONE | 100000 |
1503/// | LLCOMP | 10000 |
1504/// | LLENCAL | 1 |
1505/// | LLSHORT | 10 |
1506pub const LLCR: *mut u8 = 0x12F as *mut u8;
1507
1508/// Low Leakage Voltage Regulator Data Register (Low-Byte).
1509pub const LLDRL: *mut u8 = 0x130 as *mut u8;
1510
1511/// Low Leakage Voltage Regulator Data Register (High-Byte).
1512pub const LLDRH: *mut u8 = 0x131 as *mut u8;
1513
1514/// Data Retention Configuration Register #3.
1515pub const DRTRAM3: *mut u8 = 0x132 as *mut u8;
1516
1517/// Data Retention Configuration Register #2.
1518pub const DRTRAM2: *mut u8 = 0x133 as *mut u8;
1519
1520/// Data Retention Configuration Register #1.
1521pub const DRTRAM1: *mut u8 = 0x134 as *mut u8;
1522
1523/// Data Retention Configuration Register #0.
1524pub const DRTRAM0: *mut u8 = 0x135 as *mut u8;
1525
1526/// Port Driver Strength Register 0.
1527///
1528/// Bitfields:
1529///
1530/// | Name | Mask (binary) |
1531/// | ---- | ------------- |
1532/// | PFDRV | 11000000 |
1533/// | PEDRV | 110000 |
1534/// | PDDRV | 1100 |
1535/// | PBDRV | 11 |
1536pub const DPDS0: *mut u8 = 0x136 as *mut u8;
1537
1538/// Port Driver Strength Register 1.
1539///
1540/// Bitfields:
1541///
1542/// | Name | Mask (binary) |
1543/// | ---- | ------------- |
1544/// | PGDRV | 11 |
1545pub const DPDS1: *mut u8 = 0x137 as *mut u8;
1546
1547/// Power Amplifier Ramp up/down Control Register.
1548///
1549/// Bitfields:
1550///
1551/// | Name | Mask (binary) |
1552/// | ---- | ------------- |
1553/// | PARDFI | 10 |
1554/// | PARUFI | 1 |
1555/// | PALTU | 11100 |
1556/// | PALTD | 11100000 |
1557pub const PARCR: *mut u8 = 0x138 as *mut u8;
1558
1559/// Transceiver Pin Register.
1560///
1561/// Bitfields:
1562///
1563/// | Name | Mask (binary) |
1564/// | ---- | ------------- |
1565/// | SLPTR | 10 |
1566/// | TRXRST | 1 |
1567pub const TRXPR: *mut u8 = 0x139 as *mut u8;
1568
1569/// AES Control Register.
1570///
1571/// Bitfields:
1572///
1573/// | Name | Mask (binary) |
1574/// | ---- | ------------- |
1575/// | AES_DIR | 1000 |
1576/// | AES_REQUEST | 10000000 |
1577/// | AES_IM | 100 |
1578/// | AES_MODE | 100000 |
1579pub const AES_CTRL: *mut u8 = 0x13C as *mut u8;
1580
1581/// AES Status Register.
1582///
1583/// Bitfields:
1584///
1585/// | Name | Mask (binary) |
1586/// | ---- | ------------- |
1587/// | AES_DONE | 1 |
1588/// | AES_ER | 10000000 |
1589pub const AES_STATUS: *mut u8 = 0x13D as *mut u8;
1590
1591/// AES Plain and Cipher Text Buffer Register.
1592pub const AES_STATE: *mut u8 = 0x13E as *mut u8;
1593
1594/// AES Encryption and Decryption Key Buffer Register.
1595pub const AES_KEY: *mut u8 = 0x13F as *mut u8;
1596
1597/// Transceiver Status Register.
1598///
1599/// Bitfields:
1600///
1601/// | Name | Mask (binary) |
1602/// | ---- | ------------- |
1603/// | CCA_DONE | 10000000 |
1604/// | TST_STATUS | 100000 |
1605/// | CCA_STATUS | 1000000 |
1606pub const TRX_STATUS: *mut u8 = 0x141 as *mut u8;
1607
1608/// Transceiver State Control Register.
1609///
1610/// Bitfields:
1611///
1612/// | Name | Mask (binary) |
1613/// | ---- | ------------- |
1614/// | TRAC_STATUS | 11100000 |
1615/// | TRX_CMD | 11111 |
1616pub const TRX_STATE: *mut u8 = 0x142 as *mut u8;
1617
1618/// Reserved.
1619///
1620/// Bitfields:
1621///
1622/// | Name | Mask (binary) |
1623/// | ---- | ------------- |
1624/// | PMU_START | 100000 |
1625/// | PMU_EN | 1000000 |
1626/// | Res7 | 10000000 |
1627/// | PMU_IF_INV | 10000 |
1628pub const TRX_CTRL_0: *mut u8 = 0x143 as *mut u8;
1629
1630/// Transceiver Control Register 1.
1631///
1632/// Bitfields:
1633///
1634/// | Name | Mask (binary) |
1635/// | ---- | ------------- |
1636/// | TX_AUTO_CRC_ON | 100000 |
1637/// | IRQ_2_EXT_EN | 1000000 |
1638/// | PLL_TX_FLT | 10000 |
1639/// | PA_EXT_EN | 10000000 |
1640pub const TRX_CTRL_1: *mut u8 = 0x144 as *mut u8;
1641
1642/// Transceiver Transmit Power Control Register.
1643///
1644/// Bitfields:
1645///
1646/// | Name | Mask (binary) |
1647/// | ---- | ------------- |
1648/// | TX_PWR | 1111 |
1649pub const PHY_TX_PWR: *mut u8 = 0x145 as *mut u8;
1650
1651/// Receiver Signal Strength Indicator Register.
1652///
1653/// Bitfields:
1654///
1655/// | Name | Mask (binary) |
1656/// | ---- | ------------- |
1657/// | RSSI | 11111 |
1658/// | RND_VALUE | 1100000 |
1659/// | RX_CRC_VALID | 10000000 |
1660pub const PHY_RSSI: *mut u8 = 0x146 as *mut u8;
1661
1662/// Transceiver Energy Detection Level Register.
1663pub const PHY_ED_LEVEL: *mut u8 = 0x147 as *mut u8;
1664
1665/// Transceiver Clear Channel Assessment (CCA) Control Register.
1666///
1667/// Bitfields:
1668///
1669/// | Name | Mask (binary) |
1670/// | ---- | ------------- |
1671/// | CCA_REQUEST | 10000000 |
1672/// | CHANNEL | 11111 |
1673/// | CCA_MODE | 1100000 |
1674pub const PHY_CC_CCA: *mut u8 = 0x148 as *mut u8;
1675
1676/// Transceiver CCA Threshold Setting Register.
1677///
1678/// Bitfields:
1679///
1680/// | Name | Mask (binary) |
1681/// | ---- | ------------- |
1682/// | CCA_CS_THRES | 11110000 |
1683/// | CCA_ED_THRES | 1111 |
1684pub const CCA_THRES: *mut u8 = 0x149 as *mut u8;
1685
1686/// Transceiver Receive Control Register.
1687///
1688/// Bitfields:
1689///
1690/// | Name | Mask (binary) |
1691/// | ---- | ------------- |
1692/// | PDT_THRES | 1111 |
1693pub const RX_CTRL: *mut u8 = 0x14A as *mut u8;
1694
1695/// Start of Frame Delimiter Value Register.
1696pub const SFD_VALUE: *mut u8 = 0x14B as *mut u8;
1697
1698/// Transceiver Control Register 2.
1699///
1700/// Bitfields:
1701///
1702/// | Name | Mask (binary) |
1703/// | ---- | ------------- |
1704/// | RX_SAFE_MODE | 10000000 |
1705/// | OQPSK_DATA_RATE | 11 |
1706pub const TRX_CTRL_2: *mut u8 = 0x14C as *mut u8;
1707
1708/// Antenna Diversity Control Register.
1709///
1710/// Bitfields:
1711///
1712/// | Name | Mask (binary) |
1713/// | ---- | ------------- |
1714/// | ANT_DIV_EN | 1000 |
1715/// | ANT_CTRL | 11 |
1716/// | ANT_EXT_SW_EN | 100 |
1717/// | ANT_SEL | 10000000 |
1718pub const ANT_DIV: *mut u8 = 0x14D as *mut u8;
1719
1720/// Transceiver Interrupt Enable Register.
1721///
1722/// Bitfields:
1723///
1724/// | Name | Mask (binary) |
1725/// | ---- | ------------- |
1726/// | RX_START_EN | 100 |
1727/// | PLL_UNLOCK_EN | 10 |
1728/// | AWAKE_EN | 10000000 |
1729/// | CCA_ED_DONE_EN | 10000 |
1730/// | RX_END_EN | 1000 |
1731/// | PLL_LOCK_EN | 1 |
1732/// | TX_END_EN | 1000000 |
1733/// | AMI_EN | 100000 |
1734pub const IRQ_MASK: *mut u8 = 0x14E as *mut u8;
1735
1736/// Transceiver Interrupt Status Register.
1737///
1738/// Bitfields:
1739///
1740/// | Name | Mask (binary) |
1741/// | ---- | ------------- |
1742/// | CCA_ED_DONE | 10000 |
1743/// | AWAKE | 10000000 |
1744/// | RX_START | 100 |
1745/// | PLL_LOCK | 1 |
1746/// | TX_END | 1000000 |
1747/// | AMI | 100000 |
1748/// | PLL_UNLOCK | 10 |
1749/// | RX_END | 1000 |
1750pub const IRQ_STATUS: *mut u8 = 0x14F as *mut u8;
1751
1752/// Voltage Regulator Control and Status Register.
1753///
1754/// Bitfields:
1755///
1756/// | Name | Mask (binary) |
1757/// | ---- | ------------- |
1758/// | DVREG_EXT | 1000 |
1759/// | DVDD_OK | 100 |
1760/// | AVREG_EXT | 10000000 |
1761/// | AVDD_OK | 1000000 |
1762pub const VREG_CTRL: *mut u8 = 0x150 as *mut u8;
1763
1764/// Battery Monitor Control and Status Register.
1765///
1766/// Bitfields:
1767///
1768/// | Name | Mask (binary) |
1769/// | ---- | ------------- |
1770/// | BATMON_VTH | 1111 |
1771/// | BATMON_HR | 10000 |
1772/// | BAT_LOW | 10000000 |
1773/// | BAT_LOW_EN | 1000000 |
1774/// | BATMON_OK | 100000 |
1775pub const BATMON: *mut u8 = 0x151 as *mut u8;
1776
1777/// Crystal Oscillator Control Register.
1778///
1779/// Bitfields:
1780///
1781/// | Name | Mask (binary) |
1782/// | ---- | ------------- |
1783/// | XTAL_TRIM | 1111 |
1784/// | XTAL_MODE | 11110000 |
1785pub const XOSC_CTRL: *mut u8 = 0x152 as *mut u8;
1786
1787/// Channel Control Register 0.
1788pub const CC_CTRL_0: *mut u8 = 0x153 as *mut u8;
1789
1790/// Channel Control Register 1.
1791///
1792/// Bitfields:
1793///
1794/// | Name | Mask (binary) |
1795/// | ---- | ------------- |
1796/// | CC_BAND | 1111 |
1797pub const CC_CTRL_1: *mut u8 = 0x154 as *mut u8;
1798
1799/// Transceiver Receiver Sensitivity Control Register.
1800///
1801/// Bitfields:
1802///
1803/// | Name | Mask (binary) |
1804/// | ---- | ------------- |
1805/// | RX_PDT_DIS | 10000000 |
1806/// | RX_OVERRIDE | 1000000 |
1807/// | RX_PDT_LEVEL | 1111 |
1808pub const RX_SYN: *mut u8 = 0x155 as *mut u8;
1809
1810/// Transceiver Reduced Power Consumption Control.
1811///
1812/// Bitfields:
1813///
1814/// | Name | Mask (binary) |
1815/// | ---- | ------------- |
1816/// | PLL_RPC_EN | 1000 |
1817/// | RX_RPC_CTRL | 11000000 |
1818/// | IPAN_RPC_EN | 10 |
1819/// | PDT_RPC_EN | 10000 |
1820/// | XAH_RPC_EN | 1 |
1821/// | RX_RPC_EN | 100000 |
1822pub const TRX_RPC: *mut u8 = 0x156 as *mut u8;
1823
1824/// Transceiver Acknowledgment Frame Control Register 1.
1825///
1826/// Bitfields:
1827///
1828/// | Name | Mask (binary) |
1829/// | ---- | ------------- |
1830/// | AACK_UPLD_RES_FT | 10000 |
1831/// | AACK_PROM_MODE | 10 |
1832/// | AACK_FLTR_RES_FT | 100000 |
1833/// | AACK_ACK_TIME | 100 |
1834pub const XAH_CTRL_1: *mut u8 = 0x157 as *mut u8;
1835
1836/// Transceiver Filter Tuning Control Register.
1837///
1838/// Bitfields:
1839///
1840/// | Name | Mask (binary) |
1841/// | ---- | ------------- |
1842/// | FTN_START | 10000000 |
1843pub const FTN_CTRL: *mut u8 = 0x158 as *mut u8;
1844
1845/// Transceiver Center Frequency Calibration Control Register.
1846///
1847/// Bitfields:
1848///
1849/// | Name | Mask (binary) |
1850/// | ---- | ------------- |
1851/// | PLL_CF_START | 10000000 |
1852pub const PLL_CF: *mut u8 = 0x15A as *mut u8;
1853
1854/// Transceiver Delay Cell Calibration Control Register.
1855///
1856/// Bitfields:
1857///
1858/// | Name | Mask (binary) |
1859/// | ---- | ------------- |
1860/// | PLL_DCU_START | 10000000 |
1861pub const PLL_DCU: *mut u8 = 0x15B as *mut u8;
1862
1863/// Device Identification Register (Part Number).
1864pub const PART_NUM: *mut u8 = 0x15C as *mut u8;
1865
1866/// Device Identification Register (Version Number).
1867pub const VERSION_NUM: *mut u8 = 0x15D as *mut u8;
1868
1869/// Device Identification Register (Manufacture ID Low Byte).
1870///
1871/// Bitfields:
1872///
1873/// | Name | Mask (binary) |
1874/// | ---- | ------------- |
1875/// | MAN_ID_03 | 1000 |
1876/// | MAN_ID_04 | 10000 |
1877/// | MAN_ID_02 | 100 |
1878/// | MAN_ID_07 | 10000000 |
1879/// | MAN_ID_01 | 10 |
1880/// | MAN_ID_00 | 1 |
1881/// | MAN_ID_06 | 1000000 |
1882/// | MAN_ID_05 | 100000 |
1883pub const MAN_ID_0: *mut u8 = 0x15E as *mut u8;
1884
1885/// Device Identification Register (Manufacture ID High Byte).
1886pub const MAN_ID_1: *mut u8 = 0x15F as *mut u8;
1887
1888/// Transceiver MAC Short Address Register (Low Byte).
1889///
1890/// Bitfields:
1891///
1892/// | Name | Mask (binary) |
1893/// | ---- | ------------- |
1894/// | SHORT_ADDR_04 | 10000 |
1895/// | SHORT_ADDR_00 | 1 |
1896/// | SHORT_ADDR_05 | 100000 |
1897/// | SHORT_ADDR_02 | 100 |
1898/// | SHORT_ADDR_06 | 1000000 |
1899/// | SHORT_ADDR_03 | 1000 |
1900/// | SHORT_ADDR_01 | 10 |
1901/// | SHORT_ADDR_07 | 10000000 |
1902pub const SHORT_ADDR_0: *mut u8 = 0x160 as *mut u8;
1903
1904/// Transceiver MAC Short Address Register (High Byte).
1905pub const SHORT_ADDR_1: *mut u8 = 0x161 as *mut u8;
1906
1907/// Transceiver Personal Area Network ID Register (Low Byte).
1908///
1909/// Bitfields:
1910///
1911/// | Name | Mask (binary) |
1912/// | ---- | ------------- |
1913/// | PAN_ID_00 | 1 |
1914/// | PAN_ID_06 | 1000000 |
1915/// | PAN_ID_03 | 1000 |
1916/// | PAN_ID_01 | 10 |
1917/// | PAN_ID_02 | 100 |
1918/// | PAN_ID_05 | 100000 |
1919/// | PAN_ID_04 | 10000 |
1920/// | PAN_ID_07 | 10000000 |
1921pub const PAN_ID_0: *mut u8 = 0x162 as *mut u8;
1922
1923/// Transceiver Personal Area Network ID Register (High Byte).
1924pub const PAN_ID_1: *mut u8 = 0x163 as *mut u8;
1925
1926/// Transceiver MAC IEEE Address Register 0.
1927///
1928/// Bitfields:
1929///
1930/// | Name | Mask (binary) |
1931/// | ---- | ------------- |
1932/// | IEEE_ADDR_00 | 1 |
1933/// | IEEE_ADDR_01 | 10 |
1934/// | IEEE_ADDR_02 | 100 |
1935/// | IEEE_ADDR_03 | 1000 |
1936/// | IEEE_ADDR_06 | 1000000 |
1937/// | IEEE_ADDR_05 | 100000 |
1938/// | IEEE_ADDR_07 | 10000000 |
1939/// | IEEE_ADDR_04 | 10000 |
1940pub const IEEE_ADDR_0: *mut u8 = 0x164 as *mut u8;
1941
1942/// Transceiver MAC IEEE Address Register 1.
1943pub const IEEE_ADDR_1: *mut u8 = 0x165 as *mut u8;
1944
1945/// Transceiver MAC IEEE Address Register 2.
1946pub const IEEE_ADDR_2: *mut u8 = 0x166 as *mut u8;
1947
1948/// Transceiver MAC IEEE Address Register 3.
1949pub const IEEE_ADDR_3: *mut u8 = 0x167 as *mut u8;
1950
1951/// Transceiver MAC IEEE Address Register 4.
1952pub const IEEE_ADDR_4: *mut u8 = 0x168 as *mut u8;
1953
1954/// Transceiver MAC IEEE Address Register 5.
1955pub const IEEE_ADDR_5: *mut u8 = 0x169 as *mut u8;
1956
1957/// Transceiver MAC IEEE Address Register 6.
1958pub const IEEE_ADDR_6: *mut u8 = 0x16A as *mut u8;
1959
1960/// Transceiver MAC IEEE Address Register 7.
1961pub const IEEE_ADDR_7: *mut u8 = 0x16B as *mut u8;
1962
1963/// Transceiver Extended Operating Mode Control Register.
1964///
1965/// Bitfields:
1966///
1967/// | Name | Mask (binary) |
1968/// | ---- | ------------- |
1969/// | MAX_CSMA_RETRIES | 1110 |
1970/// | SLOTTED_OPERATION | 1 |
1971/// | MAX_FRAME_RETRIES | 11110000 |
1972pub const XAH_CTRL_0: *mut u8 = 0x16C as *mut u8;
1973
1974/// Transceiver CSMA-CA Random Number Generator Seed Register.
1975///
1976/// Bitfields:
1977///
1978/// | Name | Mask (binary) |
1979/// | ---- | ------------- |
1980/// | CSMA_SEED_01 | 10 |
1981/// | CSMA_SEED_07 | 10000000 |
1982/// | CSMA_SEED_05 | 100000 |
1983/// | CSMA_SEED_04 | 10000 |
1984/// | CSMA_SEED_03 | 1000 |
1985/// | CSMA_SEED_02 | 100 |
1986/// | CSMA_SEED_00 | 1 |
1987/// | CSMA_SEED_06 | 1000000 |
1988pub const CSMA_SEED_0: *mut u8 = 0x16D as *mut u8;
1989
1990/// Transceiver Acknowledgment Frame Control Register 2.
1991///
1992/// Bitfields:
1993///
1994/// | Name | Mask (binary) |
1995/// | ---- | ------------- |
1996/// | AACK_FVN_MODE | 11000000 |
1997/// | AACK_SET_PD | 100000 |
1998/// | AACK_DIS_ACK | 10000 |
1999/// | AACK_I_AM_COORD | 1000 |
2000pub const CSMA_SEED_1: *mut u8 = 0x16E as *mut u8;
2001
2002/// Transceiver CSMA-CA Back-off Exponent Control Register.
2003///
2004/// Bitfields:
2005///
2006/// | Name | Mask (binary) |
2007/// | ---- | ------------- |
2008/// | MIN_BE | 1111 |
2009/// | MAX_BE | 11110000 |
2010pub const CSMA_BE: *mut u8 = 0x16F as *mut u8;
2011
2012/// Transceiver Digital Test Control Register.
2013///
2014/// Bitfields:
2015///
2016/// | Name | Mask (binary) |
2017/// | ---- | ------------- |
2018/// | TST_CTRL_DIG | 1111 |
2019pub const TST_CTRL_DIGI: *mut u8 = 0x176 as *mut u8;
2020
2021/// Transceiver Received Frame Length Register.
2022pub const TST_RX_LENGTH: *mut u8 = 0x17B as *mut u8;
2023
2024/// Start of frame buffer.
2025pub const TRXFBST: *mut u8 = 0x180 as *mut u8;
2026
2027/// End of frame buffer.
2028pub const TRXFBEND: *mut u8 = 0x1FF as *mut u8;
2029
2030/// Bitfield on register `ACSR`
2031pub const ACO: *mut u8 = 0x20 as *mut u8;
2032
2033/// Bitfield on register `ACSR`
2034pub const ACIE: *mut u8 = 0x8 as *mut u8;
2035
2036/// Bitfield on register `ACSR`
2037pub const ACI: *mut u8 = 0x10 as *mut u8;
2038
2039/// Bitfield on register `ACSR`
2040pub const ACD: *mut u8 = 0x80 as *mut u8;
2041
2042/// Bitfield on register `ACSR`
2043pub const ACIC: *mut u8 = 0x4 as *mut u8;
2044
2045/// Bitfield on register `ACSR`
2046pub const ACBG: *mut u8 = 0x40 as *mut u8;
2047
2048/// Bitfield on register `ACSR`
2049pub const ACIS: *mut u8 = 0x3 as *mut u8;
2050
2051/// Bitfield on register `ADCSRA`
2052pub const ADIE: *mut u8 = 0x8 as *mut u8;
2053
2054/// Bitfield on register `ADCSRA`
2055pub const ADPS: *mut u8 = 0x7 as *mut u8;
2056
2057/// Bitfield on register `ADCSRA`
2058pub const ADATE: *mut u8 = 0x20 as *mut u8;
2059
2060/// Bitfield on register `ADCSRA`
2061pub const ADEN: *mut u8 = 0x80 as *mut u8;
2062
2063/// Bitfield on register `ADCSRA`
2064pub const ADSC: *mut u8 = 0x40 as *mut u8;
2065
2066/// Bitfield on register `ADCSRA`
2067pub const ADIF: *mut u8 = 0x10 as *mut u8;
2068
2069/// Bitfield on register `ADCSRB`
2070pub const AVDDOK: *mut u8 = 0x80 as *mut u8;
2071
2072/// Bitfield on register `ADCSRB`
2073pub const MUX5: *mut u8 = 0x8 as *mut u8;
2074
2075/// Bitfield on register `ADCSRB`
2076pub const ACCH: *mut u8 = 0x10 as *mut u8;
2077
2078/// Bitfield on register `ADCSRB`
2079pub const REFOK: *mut u8 = 0x20 as *mut u8;
2080
2081/// Bitfield on register `ADCSRB`
2082pub const ADTS: *mut u8 = 0x7 as *mut u8;
2083
2084/// Bitfield on register `ADCSRB`
2085pub const ACME: *mut u8 = 0x40 as *mut u8;
2086
2087/// Bitfield on register `ADCSRC`
2088pub const ADSUT: *mut u8 = 0x1F as *mut u8;
2089
2090/// Bitfield on register `ADCSRC`
2091pub const ADTHT: *mut u8 = 0xC0 as *mut u8;
2092
2093/// Bitfield on register `ADMUX`
2094pub const MUX: *mut u8 = 0x1F as *mut u8;
2095
2096/// Bitfield on register `ADMUX`
2097pub const REFS: *mut u8 = 0xC0 as *mut u8;
2098
2099/// Bitfield on register `ADMUX`
2100pub const ADLAR: *mut u8 = 0x20 as *mut u8;
2101
2102/// Bitfield on register `AES_CTRL`
2103pub const AES_DIR: *mut u8 = 0x8 as *mut u8;
2104
2105/// Bitfield on register `AES_CTRL`
2106pub const AES_REQUEST: *mut u8 = 0x80 as *mut u8;
2107
2108/// Bitfield on register `AES_CTRL`
2109pub const AES_IM: *mut u8 = 0x4 as *mut u8;
2110
2111/// Bitfield on register `AES_CTRL`
2112pub const AES_MODE: *mut u8 = 0x20 as *mut u8;
2113
2114/// Bitfield on register `AES_STATUS`
2115pub const AES_DONE: *mut u8 = 0x1 as *mut u8;
2116
2117/// Bitfield on register `AES_STATUS`
2118pub const AES_ER: *mut u8 = 0x80 as *mut u8;
2119
2120/// Bitfield on register `ANT_DIV`
2121pub const ANT_DIV_EN: *mut u8 = 0x8 as *mut u8;
2122
2123/// Bitfield on register `ANT_DIV`
2124pub const ANT_CTRL: *mut u8 = 0x3 as *mut u8;
2125
2126/// Bitfield on register `ANT_DIV`
2127pub const ANT_EXT_SW_EN: *mut u8 = 0x4 as *mut u8;
2128
2129/// Bitfield on register `ANT_DIV`
2130pub const ANT_SEL: *mut u8 = 0x80 as *mut u8;
2131
2132/// Bitfield on register `ASSR`
2133pub const AS2: *mut u8 = 0x20 as *mut u8;
2134
2135/// Bitfield on register `ASSR`
2136pub const TCN2UB: *mut u8 = 0x10 as *mut u8;
2137
2138/// Bitfield on register `ASSR`
2139pub const TCR2BUB: *mut u8 = 0x1 as *mut u8;
2140
2141/// Bitfield on register `ASSR`
2142pub const OCR2AUB: *mut u8 = 0x8 as *mut u8;
2143
2144/// Bitfield on register `ASSR`
2145pub const OCR2BUB: *mut u8 = 0x4 as *mut u8;
2146
2147/// Bitfield on register `ASSR`
2148pub const EXCLK: *mut u8 = 0x40 as *mut u8;
2149
2150/// Bitfield on register `ASSR`
2151pub const EXCLKAMR: *mut u8 = 0x80 as *mut u8;
2152
2153/// Bitfield on register `ASSR`
2154pub const TCR2AUB: *mut u8 = 0x2 as *mut u8;
2155
2156/// Bitfield on register `BATMON`
2157pub const BATMON_VTH: *mut u8 = 0xF as *mut u8;
2158
2159/// Bitfield on register `BATMON`
2160pub const BATMON_HR: *mut u8 = 0x10 as *mut u8;
2161
2162/// Bitfield on register `BATMON`
2163pub const BAT_LOW: *mut u8 = 0x80 as *mut u8;
2164
2165/// Bitfield on register `BATMON`
2166pub const BAT_LOW_EN: *mut u8 = 0x40 as *mut u8;
2167
2168/// Bitfield on register `BATMON`
2169pub const BATMON_OK: *mut u8 = 0x20 as *mut u8;
2170
2171/// Bitfield on register `BGCR`
2172pub const BGCAL_FINE: *mut u8 = 0x78 as *mut u8;
2173
2174/// Bitfield on register `BGCR`
2175pub const BGCAL: *mut u8 = 0x7 as *mut u8;
2176
2177/// Bitfield on register `CCA_THRES`
2178pub const CCA_CS_THRES: *mut u8 = 0xF0 as *mut u8;
2179
2180/// Bitfield on register `CCA_THRES`
2181pub const CCA_ED_THRES: *mut u8 = 0xF as *mut u8;
2182
2183/// Bitfield on register `CC_CTRL_1`
2184pub const CC_BAND: *mut u8 = 0xF as *mut u8;
2185
2186/// Bitfield on register `CLKPR`
2187pub const CLKPCE: *mut u8 = 0x80 as *mut u8;
2188
2189/// Bitfield on register `CLKPR`
2190pub const CLKPS: *mut u8 = 0xF as *mut u8;
2191
2192/// Bitfield on register `CSMA_BE`
2193pub const MIN_BE: *mut u8 = 0xF as *mut u8;
2194
2195/// Bitfield on register `CSMA_BE`
2196pub const MAX_BE: *mut u8 = 0xF0 as *mut u8;
2197
2198/// Bitfield on register `CSMA_SEED_0`
2199pub const CSMA_SEED_01: *mut u8 = 0x2 as *mut u8;
2200
2201/// Bitfield on register `CSMA_SEED_0`
2202pub const CSMA_SEED_07: *mut u8 = 0x80 as *mut u8;
2203
2204/// Bitfield on register `CSMA_SEED_0`
2205pub const CSMA_SEED_05: *mut u8 = 0x20 as *mut u8;
2206
2207/// Bitfield on register `CSMA_SEED_0`
2208pub const CSMA_SEED_04: *mut u8 = 0x10 as *mut u8;
2209
2210/// Bitfield on register `CSMA_SEED_0`
2211pub const CSMA_SEED_03: *mut u8 = 0x8 as *mut u8;
2212
2213/// Bitfield on register `CSMA_SEED_0`
2214pub const CSMA_SEED_02: *mut u8 = 0x4 as *mut u8;
2215
2216/// Bitfield on register `CSMA_SEED_0`
2217pub const CSMA_SEED_00: *mut u8 = 0x1 as *mut u8;
2218
2219/// Bitfield on register `CSMA_SEED_0`
2220pub const CSMA_SEED_06: *mut u8 = 0x40 as *mut u8;
2221
2222/// Bitfield on register `CSMA_SEED_1`
2223pub const AACK_FVN_MODE: *mut u8 = 0xC0 as *mut u8;
2224
2225/// Bitfield on register `CSMA_SEED_1`
2226pub const AACK_SET_PD: *mut u8 = 0x20 as *mut u8;
2227
2228/// Bitfield on register `CSMA_SEED_1`
2229pub const AACK_DIS_ACK: *mut u8 = 0x10 as *mut u8;
2230
2231/// Bitfield on register `CSMA_SEED_1`
2232pub const AACK_I_AM_COORD: *mut u8 = 0x8 as *mut u8;
2233
2234/// Bitfield on register `DIDR0`
2235pub const ADC4D: *mut u8 = 0x10 as *mut u8;
2236
2237/// Bitfield on register `DIDR0`
2238pub const ADC5D: *mut u8 = 0x20 as *mut u8;
2239
2240/// Bitfield on register `DIDR0`
2241pub const ADC0D: *mut u8 = 0x1 as *mut u8;
2242
2243/// Bitfield on register `DIDR0`
2244pub const ADC6D: *mut u8 = 0x40 as *mut u8;
2245
2246/// Bitfield on register `DIDR0`
2247pub const ADC3D: *mut u8 = 0x8 as *mut u8;
2248
2249/// Bitfield on register `DIDR0`
2250pub const ADC2D: *mut u8 = 0x4 as *mut u8;
2251
2252/// Bitfield on register `DIDR0`
2253pub const ADC1D: *mut u8 = 0x2 as *mut u8;
2254
2255/// Bitfield on register `DIDR0`
2256pub const ADC7D: *mut u8 = 0x80 as *mut u8;
2257
2258/// Bitfield on register `DIDR1`
2259pub const AIN1D: *mut u8 = 0x2 as *mut u8;
2260
2261/// Bitfield on register `DIDR1`
2262pub const AIN0D: *mut u8 = 0x1 as *mut u8;
2263
2264/// Bitfield on register `DIDR2`
2265pub const ADC10D: *mut u8 = 0x4 as *mut u8;
2266
2267/// Bitfield on register `DIDR2`
2268pub const ADC11D: *mut u8 = 0x8 as *mut u8;
2269
2270/// Bitfield on register `DIDR2`
2271pub const ADC12D: *mut u8 = 0x10 as *mut u8;
2272
2273/// Bitfield on register `DIDR2`
2274pub const ADC14D: *mut u8 = 0x40 as *mut u8;
2275
2276/// Bitfield on register `DIDR2`
2277pub const ADC15D: *mut u8 = 0x80 as *mut u8;
2278
2279/// Bitfield on register `DIDR2`
2280pub const ADC8D: *mut u8 = 0x1 as *mut u8;
2281
2282/// Bitfield on register `DIDR2`
2283pub const ADC9D: *mut u8 = 0x2 as *mut u8;
2284
2285/// Bitfield on register `DIDR2`
2286pub const ADC13D: *mut u8 = 0x20 as *mut u8;
2287
2288/// Bitfield on register `DPDS0`
2289pub const PFDRV: *mut u8 = 0xC0 as *mut u8;
2290
2291/// Bitfield on register `DPDS0`
2292pub const PEDRV: *mut u8 = 0x30 as *mut u8;
2293
2294/// Bitfield on register `DPDS0`
2295pub const PDDRV: *mut u8 = 0xC as *mut u8;
2296
2297/// Bitfield on register `DPDS0`
2298pub const PBDRV: *mut u8 = 0x3 as *mut u8;
2299
2300/// Bitfield on register `DPDS1`
2301pub const PGDRV: *mut u8 = 0x3 as *mut u8;
2302
2303/// Bitfield on register `EECR`
2304pub const EEPM: *mut u8 = 0x30 as *mut u8;
2305
2306/// Bitfield on register `EECR`
2307pub const EEPE: *mut u8 = 0x2 as *mut u8;
2308
2309/// Bitfield on register `EECR`
2310pub const EEMPE: *mut u8 = 0x4 as *mut u8;
2311
2312/// Bitfield on register `EECR`
2313pub const EERE: *mut u8 = 0x1 as *mut u8;
2314
2315/// Bitfield on register `EECR`
2316pub const EERIE: *mut u8 = 0x8 as *mut u8;
2317
2318/// Bitfield on register `EICRA`
2319pub const ISC1: *mut u8 = 0xC as *mut u8;
2320
2321/// Bitfield on register `EICRA`
2322pub const ISC0: *mut u8 = 0x3 as *mut u8;
2323
2324/// Bitfield on register `EICRA`
2325pub const ISC3: *mut u8 = 0xC0 as *mut u8;
2326
2327/// Bitfield on register `EICRA`
2328pub const ISC2: *mut u8 = 0x30 as *mut u8;
2329
2330/// Bitfield on register `EICRB`
2331pub const ISC5: *mut u8 = 0xC as *mut u8;
2332
2333/// Bitfield on register `EICRB`
2334pub const ISC7: *mut u8 = 0xC0 as *mut u8;
2335
2336/// Bitfield on register `EICRB`
2337pub const ISC4: *mut u8 = 0x3 as *mut u8;
2338
2339/// Bitfield on register `EICRB`
2340pub const ISC6: *mut u8 = 0x30 as *mut u8;
2341
2342/// Bitfield on register `EXTENDED`
2343pub const BODLEVEL: *mut u8 = 0x7 as *mut u8;
2344
2345/// Bitfield on register `FTN_CTRL`
2346pub const FTN_START: *mut u8 = 0x80 as *mut u8;
2347
2348/// Bitfield on register `GPIOR0`
2349pub const GPIOR01: *mut u8 = 0x2 as *mut u8;
2350
2351/// Bitfield on register `GPIOR0`
2352pub const GPIOR00: *mut u8 = 0x1 as *mut u8;
2353
2354/// Bitfield on register `GPIOR0`
2355pub const GPIOR07: *mut u8 = 0x80 as *mut u8;
2356
2357/// Bitfield on register `GPIOR0`
2358pub const GPIOR03: *mut u8 = 0x8 as *mut u8;
2359
2360/// Bitfield on register `GPIOR0`
2361pub const GPIOR04: *mut u8 = 0x10 as *mut u8;
2362
2363/// Bitfield on register `GPIOR0`
2364pub const GPIOR05: *mut u8 = 0x20 as *mut u8;
2365
2366/// Bitfield on register `GPIOR0`
2367pub const GPIOR02: *mut u8 = 0x4 as *mut u8;
2368
2369/// Bitfield on register `GPIOR0`
2370pub const GPIOR06: *mut u8 = 0x40 as *mut u8;
2371
2372/// Bitfield on register `GTCCR`
2373pub const PSRASY: *mut u8 = 0x2 as *mut u8;
2374
2375/// Bitfield on register `GTCCR`
2376pub const TSM: *mut u8 = 0x80 as *mut u8;
2377
2378/// Bitfield on register `HIGH`
2379pub const OCDEN: *mut u8 = 0x80 as *mut u8;
2380
2381/// Bitfield on register `HIGH`
2382pub const BOOTRST: *mut u8 = 0x1 as *mut u8;
2383
2384/// Bitfield on register `HIGH`
2385pub const SPIEN: *mut u8 = 0x20 as *mut u8;
2386
2387/// Bitfield on register `HIGH`
2388pub const WDTON: *mut u8 = 0x10 as *mut u8;
2389
2390/// Bitfield on register `HIGH`
2391pub const EESAVE: *mut u8 = 0x8 as *mut u8;
2392
2393/// Bitfield on register `HIGH`
2394pub const JTAGEN: *mut u8 = 0x40 as *mut u8;
2395
2396/// Bitfield on register `HIGH`
2397pub const BOOTSZ: *mut u8 = 0x6 as *mut u8;
2398
2399/// Bitfield on register `IEEE_ADDR_0`
2400pub const IEEE_ADDR_00: *mut u8 = 0x1 as *mut u8;
2401
2402/// Bitfield on register `IEEE_ADDR_0`
2403pub const IEEE_ADDR_01: *mut u8 = 0x2 as *mut u8;
2404
2405/// Bitfield on register `IEEE_ADDR_0`
2406pub const IEEE_ADDR_02: *mut u8 = 0x4 as *mut u8;
2407
2408/// Bitfield on register `IEEE_ADDR_0`
2409pub const IEEE_ADDR_03: *mut u8 = 0x8 as *mut u8;
2410
2411/// Bitfield on register `IEEE_ADDR_0`
2412pub const IEEE_ADDR_06: *mut u8 = 0x40 as *mut u8;
2413
2414/// Bitfield on register `IEEE_ADDR_0`
2415pub const IEEE_ADDR_05: *mut u8 = 0x20 as *mut u8;
2416
2417/// Bitfield on register `IEEE_ADDR_0`
2418pub const IEEE_ADDR_07: *mut u8 = 0x80 as *mut u8;
2419
2420/// Bitfield on register `IEEE_ADDR_0`
2421pub const IEEE_ADDR_04: *mut u8 = 0x10 as *mut u8;
2422
2423/// Bitfield on register `IRQ_MASK`
2424pub const RX_START_EN: *mut u8 = 0x4 as *mut u8;
2425
2426/// Bitfield on register `IRQ_MASK`
2427pub const PLL_UNLOCK_EN: *mut u8 = 0x2 as *mut u8;
2428
2429/// Bitfield on register `IRQ_MASK`
2430pub const AWAKE_EN: *mut u8 = 0x80 as *mut u8;
2431
2432/// Bitfield on register `IRQ_MASK`
2433pub const CCA_ED_DONE_EN: *mut u8 = 0x10 as *mut u8;
2434
2435/// Bitfield on register `IRQ_MASK`
2436pub const RX_END_EN: *mut u8 = 0x8 as *mut u8;
2437
2438/// Bitfield on register `IRQ_MASK`
2439pub const PLL_LOCK_EN: *mut u8 = 0x1 as *mut u8;
2440
2441/// Bitfield on register `IRQ_MASK`
2442pub const TX_END_EN: *mut u8 = 0x40 as *mut u8;
2443
2444/// Bitfield on register `IRQ_MASK`
2445pub const AMI_EN: *mut u8 = 0x20 as *mut u8;
2446
2447/// Bitfield on register `IRQ_MASK1`
2448pub const MAF_2_AMI_EN: *mut u8 = 0x8 as *mut u8;
2449
2450/// Bitfield on register `IRQ_MASK1`
2451pub const TX_START_EN: *mut u8 = 0x1 as *mut u8;
2452
2453/// Bitfield on register `IRQ_MASK1`
2454pub const MAF_3_AMI_EN: *mut u8 = 0x10 as *mut u8;
2455
2456/// Bitfield on register `IRQ_MASK1`
2457pub const MAF_1_AMI_EN: *mut u8 = 0x4 as *mut u8;
2458
2459/// Bitfield on register `IRQ_MASK1`
2460pub const MAF_0_AMI_EN: *mut u8 = 0x2 as *mut u8;
2461
2462/// Bitfield on register `IRQ_STATUS`
2463pub const CCA_ED_DONE: *mut u8 = 0x10 as *mut u8;
2464
2465/// Bitfield on register `IRQ_STATUS`
2466pub const AWAKE: *mut u8 = 0x80 as *mut u8;
2467
2468/// Bitfield on register `IRQ_STATUS`
2469pub const RX_START: *mut u8 = 0x4 as *mut u8;
2470
2471/// Bitfield on register `IRQ_STATUS`
2472pub const PLL_LOCK: *mut u8 = 0x1 as *mut u8;
2473
2474/// Bitfield on register `IRQ_STATUS`
2475pub const TX_END: *mut u8 = 0x40 as *mut u8;
2476
2477/// Bitfield on register `IRQ_STATUS`
2478pub const AMI: *mut u8 = 0x20 as *mut u8;
2479
2480/// Bitfield on register `IRQ_STATUS`
2481pub const PLL_UNLOCK: *mut u8 = 0x2 as *mut u8;
2482
2483/// Bitfield on register `IRQ_STATUS`
2484pub const RX_END: *mut u8 = 0x8 as *mut u8;
2485
2486/// Bitfield on register `IRQ_STATUS1`
2487pub const MAF_3_AMI: *mut u8 = 0x10 as *mut u8;
2488
2489/// Bitfield on register `IRQ_STATUS1`
2490pub const MAF_1_AMI: *mut u8 = 0x4 as *mut u8;
2491
2492/// Bitfield on register `IRQ_STATUS1`
2493pub const TX_START: *mut u8 = 0x1 as *mut u8;
2494
2495/// Bitfield on register `IRQ_STATUS1`
2496pub const MAF_2_AMI: *mut u8 = 0x8 as *mut u8;
2497
2498/// Bitfield on register `IRQ_STATUS1`
2499pub const MAF_0_AMI: *mut u8 = 0x2 as *mut u8;
2500
2501/// Bitfield on register `LLCR`
2502pub const LLTCO: *mut u8 = 0x4 as *mut u8;
2503
2504/// Bitfield on register `LLCR`
2505pub const LLCAL: *mut u8 = 0x8 as *mut u8;
2506
2507/// Bitfield on register `LLCR`
2508pub const LLDONE: *mut u8 = 0x20 as *mut u8;
2509
2510/// Bitfield on register `LLCR`
2511pub const LLCOMP: *mut u8 = 0x10 as *mut u8;
2512
2513/// Bitfield on register `LLCR`
2514pub const LLENCAL: *mut u8 = 0x1 as *mut u8;
2515
2516/// Bitfield on register `LLCR`
2517pub const LLSHORT: *mut u8 = 0x2 as *mut u8;
2518
2519/// Bitfield on register `LOCKBIT`
2520pub const BLB1: *mut u8 = 0x30 as *mut u8;
2521
2522/// Bitfield on register `LOCKBIT`
2523pub const LB: *mut u8 = 0x3 as *mut u8;
2524
2525/// Bitfield on register `LOCKBIT`
2526pub const BLB0: *mut u8 = 0xC as *mut u8;
2527
2528/// Bitfield on register `LOW`
2529pub const CKOUT: *mut u8 = 0x40 as *mut u8;
2530
2531/// Bitfield on register `LOW`
2532pub const CKSEL_SUT: *mut u8 = 0x3F as *mut u8;
2533
2534/// Bitfield on register `LOW`
2535pub const CKDIV8: *mut u8 = 0x80 as *mut u8;
2536
2537/// Bitfield on register `MAFCR0`
2538pub const MAF0EN: *mut u8 = 0x1 as *mut u8;
2539
2540/// Bitfield on register `MAFCR0`
2541pub const MAF2EN: *mut u8 = 0x4 as *mut u8;
2542
2543/// Bitfield on register `MAFCR0`
2544pub const MAF3EN: *mut u8 = 0x8 as *mut u8;
2545
2546/// Bitfield on register `MAFCR0`
2547pub const MAF1EN: *mut u8 = 0x2 as *mut u8;
2548
2549/// Bitfield on register `MAFCR1`
2550pub const AACK_2_I_AM_COORD: *mut u8 = 0x10 as *mut u8;
2551
2552/// Bitfield on register `MAFCR1`
2553pub const AACK_3_SET_PD: *mut u8 = 0x80 as *mut u8;
2554
2555/// Bitfield on register `MAFCR1`
2556pub const AACK_0_I_AM_COORD: *mut u8 = 0x1 as *mut u8;
2557
2558/// Bitfield on register `MAFCR1`
2559pub const AACK_1_I_AM_COORD: *mut u8 = 0x4 as *mut u8;
2560
2561/// Bitfield on register `MAFCR1`
2562pub const AACK_1_SET_PD: *mut u8 = 0x8 as *mut u8;
2563
2564/// Bitfield on register `MAFCR1`
2565pub const AACK_0_SET_PD: *mut u8 = 0x2 as *mut u8;
2566
2567/// Bitfield on register `MAFCR1`
2568pub const AACK_2_SET_PD: *mut u8 = 0x20 as *mut u8;
2569
2570/// Bitfield on register `MAFCR1`
2571pub const AACK_3_I_AM_COORD: *mut u8 = 0x40 as *mut u8;
2572
2573/// Bitfield on register `MAN_ID_0`
2574pub const MAN_ID_03: *mut u8 = 0x8 as *mut u8;
2575
2576/// Bitfield on register `MAN_ID_0`
2577pub const MAN_ID_04: *mut u8 = 0x10 as *mut u8;
2578
2579/// Bitfield on register `MAN_ID_0`
2580pub const MAN_ID_02: *mut u8 = 0x4 as *mut u8;
2581
2582/// Bitfield on register `MAN_ID_0`
2583pub const MAN_ID_07: *mut u8 = 0x80 as *mut u8;
2584
2585/// Bitfield on register `MAN_ID_0`
2586pub const MAN_ID_01: *mut u8 = 0x2 as *mut u8;
2587
2588/// Bitfield on register `MAN_ID_0`
2589pub const MAN_ID_00: *mut u8 = 0x1 as *mut u8;
2590
2591/// Bitfield on register `MAN_ID_0`
2592pub const MAN_ID_06: *mut u8 = 0x40 as *mut u8;
2593
2594/// Bitfield on register `MAN_ID_0`
2595pub const MAN_ID_05: *mut u8 = 0x20 as *mut u8;
2596
2597/// Bitfield on register `MCUCR`
2598pub const PUD: *mut u8 = 0x10 as *mut u8;
2599
2600/// Bitfield on register `MCUSR`
2601pub const JTRF: *mut u8 = 0x10 as *mut u8;
2602
2603/// Bitfield on register `MCUSR`
2604pub const EXTRF: *mut u8 = 0x2 as *mut u8;
2605
2606/// Bitfield on register `MCUSR`
2607pub const WDRF: *mut u8 = 0x8 as *mut u8;
2608
2609/// Bitfield on register `MCUSR`
2610pub const BORF: *mut u8 = 0x4 as *mut u8;
2611
2612/// Bitfield on register `MCUSR`
2613pub const PORF: *mut u8 = 0x1 as *mut u8;
2614
2615/// Bitfield on register `NEMCR`
2616pub const ENEAM: *mut u8 = 0x40 as *mut u8;
2617
2618/// Bitfield on register `NEMCR`
2619pub const AEAM: *mut u8 = 0x30 as *mut u8;
2620
2621/// Bitfield on register `PAN_ID_0`
2622pub const PAN_ID_00: *mut u8 = 0x1 as *mut u8;
2623
2624/// Bitfield on register `PAN_ID_0`
2625pub const PAN_ID_06: *mut u8 = 0x40 as *mut u8;
2626
2627/// Bitfield on register `PAN_ID_0`
2628pub const PAN_ID_03: *mut u8 = 0x8 as *mut u8;
2629
2630/// Bitfield on register `PAN_ID_0`
2631pub const PAN_ID_01: *mut u8 = 0x2 as *mut u8;
2632
2633/// Bitfield on register `PAN_ID_0`
2634pub const PAN_ID_02: *mut u8 = 0x4 as *mut u8;
2635
2636/// Bitfield on register `PAN_ID_0`
2637pub const PAN_ID_05: *mut u8 = 0x20 as *mut u8;
2638
2639/// Bitfield on register `PAN_ID_0`
2640pub const PAN_ID_04: *mut u8 = 0x10 as *mut u8;
2641
2642/// Bitfield on register `PAN_ID_0`
2643pub const PAN_ID_07: *mut u8 = 0x80 as *mut u8;
2644
2645/// Bitfield on register `PARCR`
2646pub const PARDFI: *mut u8 = 0x2 as *mut u8;
2647
2648/// Bitfield on register `PARCR`
2649pub const PARUFI: *mut u8 = 0x1 as *mut u8;
2650
2651/// Bitfield on register `PARCR`
2652pub const PALTU: *mut u8 = 0x1C as *mut u8;
2653
2654/// Bitfield on register `PARCR`
2655pub const PALTD: *mut u8 = 0xE0 as *mut u8;
2656
2657/// Bitfield on register `PCICR`
2658pub const PCIE: *mut u8 = 0x7 as *mut u8;
2659
2660/// Bitfield on register `PCIFR`
2661pub const PCIF: *mut u8 = 0x7 as *mut u8;
2662
2663/// Bitfield on register `PHY_CC_CCA`
2664pub const CCA_REQUEST: *mut u8 = 0x80 as *mut u8;
2665
2666/// Bitfield on register `PHY_CC_CCA`
2667pub const CHANNEL: *mut u8 = 0x1F as *mut u8;
2668
2669/// Bitfield on register `PHY_CC_CCA`
2670pub const CCA_MODE: *mut u8 = 0x60 as *mut u8;
2671
2672/// Bitfield on register `PHY_RSSI`
2673pub const RSSI: *mut u8 = 0x1F as *mut u8;
2674
2675/// Bitfield on register `PHY_RSSI`
2676pub const RND_VALUE: *mut u8 = 0x60 as *mut u8;
2677
2678/// Bitfield on register `PHY_RSSI`
2679pub const RX_CRC_VALID: *mut u8 = 0x80 as *mut u8;
2680
2681/// Bitfield on register `PHY_TX_PWR`
2682pub const TX_PWR: *mut u8 = 0xF as *mut u8;
2683
2684/// Bitfield on register `PLL_CF`
2685pub const PLL_CF_START: *mut u8 = 0x80 as *mut u8;
2686
2687/// Bitfield on register `PLL_DCU`
2688pub const PLL_DCU_START: *mut u8 = 0x80 as *mut u8;
2689
2690/// Bitfield on register `PRR0`
2691pub const PRPGA: *mut u8 = 0x10 as *mut u8;
2692
2693/// Bitfield on register `PRR0`
2694pub const PRSPI: *mut u8 = 0x4 as *mut u8;
2695
2696/// Bitfield on register `PRR0`
2697pub const PRTWI: *mut u8 = 0x80 as *mut u8;
2698
2699/// Bitfield on register `PRR0`
2700pub const PRTIM1: *mut u8 = 0x8 as *mut u8;
2701
2702/// Bitfield on register `PRR0`
2703pub const PRUSART0: *mut u8 = 0x2 as *mut u8;
2704
2705/// Bitfield on register `PRR0`
2706pub const PRTIM0: *mut u8 = 0x20 as *mut u8;
2707
2708/// Bitfield on register `PRR0`
2709pub const PRADC: *mut u8 = 0x1 as *mut u8;
2710
2711/// Bitfield on register `PRR0`
2712pub const PRTIM2: *mut u8 = 0x40 as *mut u8;
2713
2714/// Bitfield on register `PRR1`
2715pub const PRTIM5: *mut u8 = 0x20 as *mut u8;
2716
2717/// Bitfield on register `PRR1`
2718pub const PRUSART1: *mut u8 = 0x1 as *mut u8;
2719
2720/// Bitfield on register `PRR1`
2721pub const PRTRX24: *mut u8 = 0x40 as *mut u8;
2722
2723/// Bitfield on register `PRR1`
2724pub const PRTIM3: *mut u8 = 0x8 as *mut u8;
2725
2726/// Bitfield on register `PRR1`
2727pub const PRTIM4: *mut u8 = 0x10 as *mut u8;
2728
2729/// Bitfield on register `PRR2`
2730pub const PRRAM2: *mut u8 = 0x4 as *mut u8;
2731
2732/// Bitfield on register `PRR2`
2733pub const PRRAM1: *mut u8 = 0x2 as *mut u8;
2734
2735/// Bitfield on register `PRR2`
2736pub const PRRAM3: *mut u8 = 0x8 as *mut u8;
2737
2738/// Bitfield on register `PRR2`
2739pub const PRRAM0: *mut u8 = 0x1 as *mut u8;
2740
2741/// Bitfield on register `RX_CTRL`
2742pub const PDT_THRES: *mut u8 = 0xF as *mut u8;
2743
2744/// Bitfield on register `RX_SYN`
2745pub const RX_PDT_DIS: *mut u8 = 0x80 as *mut u8;
2746
2747/// Bitfield on register `RX_SYN`
2748pub const RX_OVERRIDE: *mut u8 = 0x40 as *mut u8;
2749
2750/// Bitfield on register `RX_SYN`
2751pub const RX_PDT_LEVEL: *mut u8 = 0xF as *mut u8;
2752
2753/// Bitfield on register `SCCR0`
2754pub const SCCMP: *mut u8 = 0x7 as *mut u8;
2755
2756/// Bitfield on register `SCCR0`
2757pub const SCRES: *mut u8 = 0x80 as *mut u8;
2758
2759/// Bitfield on register `SCCR0`
2760pub const SCTSE: *mut u8 = 0x8 as *mut u8;
2761
2762/// Bitfield on register `SCCR0`
2763pub const SCEN: *mut u8 = 0x20 as *mut u8;
2764
2765/// Bitfield on register `SCCR0`
2766pub const SCMBTS: *mut u8 = 0x40 as *mut u8;
2767
2768/// Bitfield on register `SCCR0`
2769pub const SCCKSEL: *mut u8 = 0x10 as *mut u8;
2770
2771/// Bitfield on register `SCCR1`
2772pub const SCENBO: *mut u8 = 0x1 as *mut u8;
2773
2774/// Bitfield on register `SCCR1`
2775pub const SCCKDIV: *mut u8 = 0x1C as *mut u8;
2776
2777/// Bitfield on register `SCCR1`
2778pub const SCBTSM: *mut u8 = 0x20 as *mut u8;
2779
2780/// Bitfield on register `SCCR1`
2781pub const SCEECLK: *mut u8 = 0x2 as *mut u8;
2782
2783/// Bitfield on register `SCCSR`
2784pub const SCCS2: *mut u8 = 0xC as *mut u8;
2785
2786/// Bitfield on register `SCCSR`
2787pub const SCCS3: *mut u8 = 0x30 as *mut u8;
2788
2789/// Bitfield on register `SCCSR`
2790pub const SCCS1: *mut u8 = 0x3 as *mut u8;
2791
2792/// Bitfield on register `SCIRQM`
2793pub const IRQMBO: *mut u8 = 0x10 as *mut u8;
2794
2795/// Bitfield on register `SCIRQM`
2796pub const IRQMOF: *mut u8 = 0x8 as *mut u8;
2797
2798/// Bitfield on register `SCIRQM`
2799pub const IRQMCP: *mut u8 = 0x7 as *mut u8;
2800
2801/// Bitfield on register `SCIRQS`
2802pub const IRQSCP: *mut u8 = 0x7 as *mut u8;
2803
2804/// Bitfield on register `SCIRQS`
2805pub const IRQSBO: *mut u8 = 0x10 as *mut u8;
2806
2807/// Bitfield on register `SCIRQS`
2808pub const IRQSOF: *mut u8 = 0x8 as *mut u8;
2809
2810/// Bitfield on register `SCSR`
2811pub const SCBSY: *mut u8 = 0x1 as *mut u8;
2812
2813/// Bitfield on register `SHORT_ADDR_0`
2814pub const SHORT_ADDR_04: *mut u8 = 0x10 as *mut u8;
2815
2816/// Bitfield on register `SHORT_ADDR_0`
2817pub const SHORT_ADDR_00: *mut u8 = 0x1 as *mut u8;
2818
2819/// Bitfield on register `SHORT_ADDR_0`
2820pub const SHORT_ADDR_05: *mut u8 = 0x20 as *mut u8;
2821
2822/// Bitfield on register `SHORT_ADDR_0`
2823pub const SHORT_ADDR_02: *mut u8 = 0x4 as *mut u8;
2824
2825/// Bitfield on register `SHORT_ADDR_0`
2826pub const SHORT_ADDR_06: *mut u8 = 0x40 as *mut u8;
2827
2828/// Bitfield on register `SHORT_ADDR_0`
2829pub const SHORT_ADDR_03: *mut u8 = 0x8 as *mut u8;
2830
2831/// Bitfield on register `SHORT_ADDR_0`
2832pub const SHORT_ADDR_01: *mut u8 = 0x2 as *mut u8;
2833
2834/// Bitfield on register `SHORT_ADDR_0`
2835pub const SHORT_ADDR_07: *mut u8 = 0x80 as *mut u8;
2836
2837/// Bitfield on register `SMCR`
2838pub const SE: *mut u8 = 0x1 as *mut u8;
2839
2840/// Bitfield on register `SMCR`
2841pub const SM: *mut u8 = 0xE as *mut u8;
2842
2843/// Bitfield on register `SPCR`
2844pub const SPR: *mut u8 = 0x3 as *mut u8;
2845
2846/// Bitfield on register `SPCR`
2847pub const SPE: *mut u8 = 0x40 as *mut u8;
2848
2849/// Bitfield on register `SPCR`
2850pub const DORD: *mut u8 = 0x20 as *mut u8;
2851
2852/// Bitfield on register `SPCR`
2853pub const CPOL: *mut u8 = 0x8 as *mut u8;
2854
2855/// Bitfield on register `SPCR`
2856pub const CPHA: *mut u8 = 0x4 as *mut u8;
2857
2858/// Bitfield on register `SPCR`
2859pub const SPIE: *mut u8 = 0x80 as *mut u8;
2860
2861/// Bitfield on register `SPCR`
2862pub const MSTR: *mut u8 = 0x10 as *mut u8;
2863
2864/// Bitfield on register `SPMCSR`
2865pub const PGWRT: *mut u8 = 0x4 as *mut u8;
2866
2867/// Bitfield on register `SPMCSR`
2868pub const RWWSB: *mut u8 = 0x40 as *mut u8;
2869
2870/// Bitfield on register `SPMCSR`
2871pub const PGERS: *mut u8 = 0x2 as *mut u8;
2872
2873/// Bitfield on register `SPMCSR`
2874pub const BLBSET: *mut u8 = 0x8 as *mut u8;
2875
2876/// Bitfield on register `SPMCSR`
2877pub const RWWSRE: *mut u8 = 0x10 as *mut u8;
2878
2879/// Bitfield on register `SPMCSR`
2880pub const SPMEN: *mut u8 = 0x1 as *mut u8;
2881
2882/// Bitfield on register `SPMCSR`
2883pub const SIGRD: *mut u8 = 0x20 as *mut u8;
2884
2885/// Bitfield on register `SPMCSR`
2886pub const SPMIE: *mut u8 = 0x80 as *mut u8;
2887
2888/// Bitfield on register `SPSR`
2889pub const WCOL: *mut u8 = 0x40 as *mut u8;
2890
2891/// Bitfield on register `SPSR`
2892pub const SPIF: *mut u8 = 0x80 as *mut u8;
2893
2894/// Bitfield on register `SPSR`
2895pub const SPI2X: *mut u8 = 0x1 as *mut u8;
2896
2897/// Bitfield on register `SREG`
2898pub const S: *mut u8 = 0x10 as *mut u8;
2899
2900/// Bitfield on register `SREG`
2901pub const N: *mut u8 = 0x4 as *mut u8;
2902
2903/// Bitfield on register `SREG`
2904pub const V: *mut u8 = 0x8 as *mut u8;
2905
2906/// Bitfield on register `SREG`
2907pub const C: *mut u8 = 0x1 as *mut u8;
2908
2909/// Bitfield on register `SREG`
2910pub const H: *mut u8 = 0x20 as *mut u8;
2911
2912/// Bitfield on register `SREG`
2913pub const I: *mut u8 = 0x80 as *mut u8;
2914
2915/// Bitfield on register `SREG`
2916pub const T: *mut u8 = 0x40 as *mut u8;
2917
2918/// Bitfield on register `SREG`
2919pub const Z: *mut u8 = 0x2 as *mut u8;
2920
2921/// Bitfield on register `TCCR0A`
2922pub const COM0B: *mut u8 = 0x30 as *mut u8;
2923
2924/// Bitfield on register `TCCR0A`
2925pub const WGM0: *mut u8 = 0x3 as *mut u8;
2926
2927/// Bitfield on register `TCCR0A`
2928pub const COM0A: *mut u8 = 0xC0 as *mut u8;
2929
2930/// Bitfield on register `TCCR0B`
2931pub const CS0: *mut u8 = 0x7 as *mut u8;
2932
2933/// Bitfield on register `TCCR0B`
2934pub const WGM02: *mut u8 = 0x8 as *mut u8;
2935
2936/// Bitfield on register `TCCR0B`
2937pub const FOC0A: *mut u8 = 0x80 as *mut u8;
2938
2939/// Bitfield on register `TCCR0B`
2940pub const FOC0B: *mut u8 = 0x40 as *mut u8;
2941
2942/// Bitfield on register `TCCR1A`
2943pub const COM1C: *mut u8 = 0xC as *mut u8;
2944
2945/// Bitfield on register `TCCR1A`
2946pub const COM1B: *mut u8 = 0x30 as *mut u8;
2947
2948/// Bitfield on register `TCCR1A`
2949pub const COM1A: *mut u8 = 0xC0 as *mut u8;
2950
2951/// Bitfield on register `TCCR1B`
2952pub const ICNC1: *mut u8 = 0x80 as *mut u8;
2953
2954/// Bitfield on register `TCCR1B`
2955pub const CS1: *mut u8 = 0x7 as *mut u8;
2956
2957/// Bitfield on register `TCCR1B`
2958pub const ICES1: *mut u8 = 0x40 as *mut u8;
2959
2960/// Bitfield on register `TCCR1C`
2961pub const FOC1A: *mut u8 = 0x80 as *mut u8;
2962
2963/// Bitfield on register `TCCR1C`
2964pub const FOC1B: *mut u8 = 0x40 as *mut u8;
2965
2966/// Bitfield on register `TCCR1C`
2967pub const FOC1C: *mut u8 = 0x20 as *mut u8;
2968
2969/// Bitfield on register `TCCR2A`
2970pub const WGM2: *mut u8 = 0x3 as *mut u8;
2971
2972/// Bitfield on register `TCCR2A`
2973pub const COM2A: *mut u8 = 0xC0 as *mut u8;
2974
2975/// Bitfield on register `TCCR2A`
2976pub const COM2B: *mut u8 = 0x30 as *mut u8;
2977
2978/// Bitfield on register `TCCR2B`
2979pub const FOC2B: *mut u8 = 0x40 as *mut u8;
2980
2981/// Bitfield on register `TCCR2B`
2982pub const WGM22: *mut u8 = 0x8 as *mut u8;
2983
2984/// Bitfield on register `TCCR2B`
2985pub const FOC2A: *mut u8 = 0x80 as *mut u8;
2986
2987/// Bitfield on register `TCCR2B`
2988pub const CS2: *mut u8 = 0x7 as *mut u8;
2989
2990/// Bitfield on register `TCCR3A`
2991pub const COM3A: *mut u8 = 0xC0 as *mut u8;
2992
2993/// Bitfield on register `TCCR3A`
2994pub const COM3C: *mut u8 = 0xC as *mut u8;
2995
2996/// Bitfield on register `TCCR3A`
2997pub const COM3B: *mut u8 = 0x30 as *mut u8;
2998
2999/// Bitfield on register `TCCR3B`
3000pub const CS3: *mut u8 = 0x7 as *mut u8;
3001
3002/// Bitfield on register `TCCR3B`
3003pub const ICNC3: *mut u8 = 0x80 as *mut u8;
3004
3005/// Bitfield on register `TCCR3B`
3006pub const ICES3: *mut u8 = 0x40 as *mut u8;
3007
3008/// Bitfield on register `TCCR3C`
3009pub const FOC3A: *mut u8 = 0x80 as *mut u8;
3010
3011/// Bitfield on register `TCCR3C`
3012pub const FOC3C: *mut u8 = 0x20 as *mut u8;
3013
3014/// Bitfield on register `TCCR3C`
3015pub const FOC3B: *mut u8 = 0x40 as *mut u8;
3016
3017/// Bitfield on register `TCCR4A`
3018pub const COM4A: *mut u8 = 0xC0 as *mut u8;
3019
3020/// Bitfield on register `TCCR4A`
3021pub const COM4C: *mut u8 = 0xC as *mut u8;
3022
3023/// Bitfield on register `TCCR4A`
3024pub const COM4B: *mut u8 = 0x30 as *mut u8;
3025
3026/// Bitfield on register `TCCR4B`
3027pub const ICNC4: *mut u8 = 0x80 as *mut u8;
3028
3029/// Bitfield on register `TCCR4B`
3030pub const ICES4: *mut u8 = 0x40 as *mut u8;
3031
3032/// Bitfield on register `TCCR4B`
3033pub const CS4: *mut u8 = 0x7 as *mut u8;
3034
3035/// Bitfield on register `TCCR4C`
3036pub const FOC4A: *mut u8 = 0x80 as *mut u8;
3037
3038/// Bitfield on register `TCCR4C`
3039pub const FOC4B: *mut u8 = 0x40 as *mut u8;
3040
3041/// Bitfield on register `TCCR4C`
3042pub const FOC4C: *mut u8 = 0x20 as *mut u8;
3043
3044/// Bitfield on register `TCCR5A`
3045pub const COM5A: *mut u8 = 0xC0 as *mut u8;
3046
3047/// Bitfield on register `TCCR5A`
3048pub const COM5B: *mut u8 = 0x30 as *mut u8;
3049
3050/// Bitfield on register `TCCR5A`
3051pub const COM5C: *mut u8 = 0xC as *mut u8;
3052
3053/// Bitfield on register `TCCR5B`
3054pub const ICNC5: *mut u8 = 0x80 as *mut u8;
3055
3056/// Bitfield on register `TCCR5B`
3057pub const CS5: *mut u8 = 0x7 as *mut u8;
3058
3059/// Bitfield on register `TCCR5B`
3060pub const ICES5: *mut u8 = 0x40 as *mut u8;
3061
3062/// Bitfield on register `TCCR5C`
3063pub const FOC5C: *mut u8 = 0x20 as *mut u8;
3064
3065/// Bitfield on register `TCCR5C`
3066pub const FOC5B: *mut u8 = 0x40 as *mut u8;
3067
3068/// Bitfield on register `TCCR5C`
3069pub const FOC5A: *mut u8 = 0x80 as *mut u8;
3070
3071/// Bitfield on register `TIFR0`
3072pub const OCF0A: *mut u8 = 0x2 as *mut u8;
3073
3074/// Bitfield on register `TIFR0`
3075pub const OCF0B: *mut u8 = 0x4 as *mut u8;
3076
3077/// Bitfield on register `TIFR0`
3078pub const TOV0: *mut u8 = 0x1 as *mut u8;
3079
3080/// Bitfield on register `TIFR1`
3081pub const OCF1C: *mut u8 = 0x8 as *mut u8;
3082
3083/// Bitfield on register `TIFR1`
3084pub const TOV1: *mut u8 = 0x1 as *mut u8;
3085
3086/// Bitfield on register `TIFR1`
3087pub const ICF1: *mut u8 = 0x20 as *mut u8;
3088
3089/// Bitfield on register `TIFR1`
3090pub const OCF1A: *mut u8 = 0x2 as *mut u8;
3091
3092/// Bitfield on register `TIFR1`
3093pub const OCF1B: *mut u8 = 0x4 as *mut u8;
3094
3095/// Bitfield on register `TIFR2`
3096pub const TOV2: *mut u8 = 0x1 as *mut u8;
3097
3098/// Bitfield on register `TIFR2`
3099pub const OCF2A: *mut u8 = 0x2 as *mut u8;
3100
3101/// Bitfield on register `TIFR2`
3102pub const OCF2B: *mut u8 = 0x4 as *mut u8;
3103
3104/// Bitfield on register `TIFR3`
3105pub const ICF3: *mut u8 = 0x20 as *mut u8;
3106
3107/// Bitfield on register `TIFR3`
3108pub const OCF3A: *mut u8 = 0x2 as *mut u8;
3109
3110/// Bitfield on register `TIFR3`
3111pub const OCF3B: *mut u8 = 0x4 as *mut u8;
3112
3113/// Bitfield on register `TIFR3`
3114pub const TOV3: *mut u8 = 0x1 as *mut u8;
3115
3116/// Bitfield on register `TIFR3`
3117pub const OCF3C: *mut u8 = 0x8 as *mut u8;
3118
3119/// Bitfield on register `TIFR4`
3120pub const OCF4C: *mut u8 = 0x8 as *mut u8;
3121
3122/// Bitfield on register `TIFR4`
3123pub const TOV4: *mut u8 = 0x1 as *mut u8;
3124
3125/// Bitfield on register `TIFR4`
3126pub const ICF4: *mut u8 = 0x20 as *mut u8;
3127
3128/// Bitfield on register `TIFR4`
3129pub const OCF4A: *mut u8 = 0x2 as *mut u8;
3130
3131/// Bitfield on register `TIFR4`
3132pub const OCF4B: *mut u8 = 0x4 as *mut u8;
3133
3134/// Bitfield on register `TIFR5`
3135pub const OCF5A: *mut u8 = 0x2 as *mut u8;
3136
3137/// Bitfield on register `TIFR5`
3138pub const OCF5B: *mut u8 = 0x4 as *mut u8;
3139
3140/// Bitfield on register `TIFR5`
3141pub const ICF5: *mut u8 = 0x20 as *mut u8;
3142
3143/// Bitfield on register `TIFR5`
3144pub const TOV5: *mut u8 = 0x1 as *mut u8;
3145
3146/// Bitfield on register `TIFR5`
3147pub const OCF5C: *mut u8 = 0x8 as *mut u8;
3148
3149/// Bitfield on register `TIMSK0`
3150pub const OCIE0A: *mut u8 = 0x2 as *mut u8;
3151
3152/// Bitfield on register `TIMSK0`
3153pub const OCIE0B: *mut u8 = 0x4 as *mut u8;
3154
3155/// Bitfield on register `TIMSK0`
3156pub const TOIE0: *mut u8 = 0x1 as *mut u8;
3157
3158/// Bitfield on register `TIMSK1`
3159pub const OCIE1B: *mut u8 = 0x4 as *mut u8;
3160
3161/// Bitfield on register `TIMSK1`
3162pub const ICIE1: *mut u8 = 0x20 as *mut u8;
3163
3164/// Bitfield on register `TIMSK1`
3165pub const OCIE1C: *mut u8 = 0x8 as *mut u8;
3166
3167/// Bitfield on register `TIMSK1`
3168pub const TOIE1: *mut u8 = 0x1 as *mut u8;
3169
3170/// Bitfield on register `TIMSK1`
3171pub const OCIE1A: *mut u8 = 0x2 as *mut u8;
3172
3173/// Bitfield on register `TIMSK2`
3174pub const TOIE2: *mut u8 = 0x1 as *mut u8;
3175
3176/// Bitfield on register `TIMSK2`
3177pub const OCIE2A: *mut u8 = 0x2 as *mut u8;
3178
3179/// Bitfield on register `TIMSK2`
3180pub const OCIE2B: *mut u8 = 0x4 as *mut u8;
3181
3182/// Bitfield on register `TIMSK3`
3183pub const TOIE3: *mut u8 = 0x1 as *mut u8;
3184
3185/// Bitfield on register `TIMSK3`
3186pub const ICIE3: *mut u8 = 0x20 as *mut u8;
3187
3188/// Bitfield on register `TIMSK3`
3189pub const OCIE3A: *mut u8 = 0x2 as *mut u8;
3190
3191/// Bitfield on register `TIMSK3`
3192pub const OCIE3C: *mut u8 = 0x8 as *mut u8;
3193
3194/// Bitfield on register `TIMSK3`
3195pub const OCIE3B: *mut u8 = 0x4 as *mut u8;
3196
3197/// Bitfield on register `TIMSK4`
3198pub const OCIE4B: *mut u8 = 0x4 as *mut u8;
3199
3200/// Bitfield on register `TIMSK4`
3201pub const ICIE4: *mut u8 = 0x20 as *mut u8;
3202
3203/// Bitfield on register `TIMSK4`
3204pub const OCIE4A: *mut u8 = 0x2 as *mut u8;
3205
3206/// Bitfield on register `TIMSK4`
3207pub const OCIE4C: *mut u8 = 0x8 as *mut u8;
3208
3209/// Bitfield on register `TIMSK4`
3210pub const TOIE4: *mut u8 = 0x1 as *mut u8;
3211
3212/// Bitfield on register `TIMSK5`
3213pub const OCIE5A: *mut u8 = 0x2 as *mut u8;
3214
3215/// Bitfield on register `TIMSK5`
3216pub const OCIE5C: *mut u8 = 0x8 as *mut u8;
3217
3218/// Bitfield on register `TIMSK5`
3219pub const ICIE5: *mut u8 = 0x20 as *mut u8;
3220
3221/// Bitfield on register `TIMSK5`
3222pub const OCIE5B: *mut u8 = 0x4 as *mut u8;
3223
3224/// Bitfield on register `TIMSK5`
3225pub const TOIE5: *mut u8 = 0x1 as *mut u8;
3226
3227/// Bitfield on register `TRXPR`
3228pub const SLPTR: *mut u8 = 0x2 as *mut u8;
3229
3230/// Bitfield on register `TRXPR`
3231pub const TRXRST: *mut u8 = 0x1 as *mut u8;
3232
3233/// Bitfield on register `TRX_CTRL_0`
3234pub const PMU_START: *mut u8 = 0x20 as *mut u8;
3235
3236/// Bitfield on register `TRX_CTRL_0`
3237pub const PMU_EN: *mut u8 = 0x40 as *mut u8;
3238
3239/// Bitfield on register `TRX_CTRL_0`
3240pub const Res7: *mut u8 = 0x80 as *mut u8;
3241
3242/// Bitfield on register `TRX_CTRL_0`
3243pub const PMU_IF_INV: *mut u8 = 0x10 as *mut u8;
3244
3245/// Bitfield on register `TRX_CTRL_1`
3246pub const TX_AUTO_CRC_ON: *mut u8 = 0x20 as *mut u8;
3247
3248/// Bitfield on register `TRX_CTRL_1`
3249pub const IRQ_2_EXT_EN: *mut u8 = 0x40 as *mut u8;
3250
3251/// Bitfield on register `TRX_CTRL_1`
3252pub const PLL_TX_FLT: *mut u8 = 0x10 as *mut u8;
3253
3254/// Bitfield on register `TRX_CTRL_1`
3255pub const PA_EXT_EN: *mut u8 = 0x80 as *mut u8;
3256
3257/// Bitfield on register `TRX_CTRL_2`
3258pub const RX_SAFE_MODE: *mut u8 = 0x80 as *mut u8;
3259
3260/// Bitfield on register `TRX_CTRL_2`
3261pub const OQPSK_DATA_RATE: *mut u8 = 0x3 as *mut u8;
3262
3263/// Bitfield on register `TRX_RPC`
3264pub const PLL_RPC_EN: *mut u8 = 0x8 as *mut u8;
3265
3266/// Bitfield on register `TRX_RPC`
3267pub const RX_RPC_CTRL: *mut u8 = 0xC0 as *mut u8;
3268
3269/// Bitfield on register `TRX_RPC`
3270pub const IPAN_RPC_EN: *mut u8 = 0x2 as *mut u8;
3271
3272/// Bitfield on register `TRX_RPC`
3273pub const PDT_RPC_EN: *mut u8 = 0x10 as *mut u8;
3274
3275/// Bitfield on register `TRX_RPC`
3276pub const XAH_RPC_EN: *mut u8 = 0x1 as *mut u8;
3277
3278/// Bitfield on register `TRX_RPC`
3279pub const RX_RPC_EN: *mut u8 = 0x20 as *mut u8;
3280
3281/// Bitfield on register `TRX_STATE`
3282pub const TRAC_STATUS: *mut u8 = 0xE0 as *mut u8;
3283
3284/// Bitfield on register `TRX_STATE`
3285pub const TRX_CMD: *mut u8 = 0x1F as *mut u8;
3286
3287/// Bitfield on register `TRX_STATUS`
3288pub const CCA_DONE: *mut u8 = 0x80 as *mut u8;
3289
3290/// Bitfield on register `TRX_STATUS`
3291pub const TST_STATUS: *mut u8 = 0x20 as *mut u8;
3292
3293/// Bitfield on register `TRX_STATUS`
3294pub const CCA_STATUS: *mut u8 = 0x40 as *mut u8;
3295
3296/// Bitfield on register `TST_CTRL_DIGI`
3297pub const TST_CTRL_DIG: *mut u8 = 0xF as *mut u8;
3298
3299/// Bitfield on register `TWAMR`
3300pub const TWAM: *mut u8 = 0xFE as *mut u8;
3301
3302/// Bitfield on register `TWAR`
3303pub const TWA: *mut u8 = 0xFE as *mut u8;
3304
3305/// Bitfield on register `TWAR`
3306pub const TWGCE: *mut u8 = 0x1 as *mut u8;
3307
3308/// Bitfield on register `TWCR`
3309pub const TWEA: *mut u8 = 0x40 as *mut u8;
3310
3311/// Bitfield on register `TWCR`
3312pub const TWSTO: *mut u8 = 0x10 as *mut u8;
3313
3314/// Bitfield on register `TWCR`
3315pub const TWIE: *mut u8 = 0x1 as *mut u8;
3316
3317/// Bitfield on register `TWCR`
3318pub const TWINT: *mut u8 = 0x80 as *mut u8;
3319
3320/// Bitfield on register `TWCR`
3321pub const TWWC: *mut u8 = 0x8 as *mut u8;
3322
3323/// Bitfield on register `TWCR`
3324pub const TWEN: *mut u8 = 0x4 as *mut u8;
3325
3326/// Bitfield on register `TWCR`
3327pub const TWSTA: *mut u8 = 0x20 as *mut u8;
3328
3329/// Bitfield on register `TWSR`
3330pub const TWS: *mut u8 = 0xF8 as *mut u8;
3331
3332/// Bitfield on register `TWSR`
3333pub const TWPS: *mut u8 = 0x3 as *mut u8;
3334
3335/// Bitfield on register `UCSR0A`
3336pub const TXC0: *mut u8 = 0x40 as *mut u8;
3337
3338/// Bitfield on register `UCSR0A`
3339pub const UDRE0: *mut u8 = 0x20 as *mut u8;
3340
3341/// Bitfield on register `UCSR0A`
3342pub const RXC0: *mut u8 = 0x80 as *mut u8;
3343
3344/// Bitfield on register `UCSR0B`
3345pub const UDRIE0: *mut u8 = 0x20 as *mut u8;
3346
3347/// Bitfield on register `UCSR0B`
3348pub const TXEN0: *mut u8 = 0x8 as *mut u8;
3349
3350/// Bitfield on register `UCSR0B`
3351pub const RXEN0: *mut u8 = 0x10 as *mut u8;
3352
3353/// Bitfield on register `UCSR0B`
3354pub const RXCIE0: *mut u8 = 0x80 as *mut u8;
3355
3356/// Bitfield on register `UCSR0B`
3357pub const TXCIE0: *mut u8 = 0x40 as *mut u8;
3358
3359/// Bitfield on register `UCSR0C`
3360pub const UDORD0: *mut u8 = 0x4 as *mut u8;
3361
3362/// Bitfield on register `UCSR0C`
3363pub const UCPOL0: *mut u8 = 0x1 as *mut u8;
3364
3365/// Bitfield on register `UCSR0C`
3366pub const UCPHA0: *mut u8 = 0x2 as *mut u8;
3367
3368/// Bitfield on register `UCSR1A`
3369pub const RXC1: *mut u8 = 0x80 as *mut u8;
3370
3371/// Bitfield on register `UCSR1A`
3372pub const UDRE1: *mut u8 = 0x20 as *mut u8;
3373
3374/// Bitfield on register `UCSR1A`
3375pub const TXC1: *mut u8 = 0x40 as *mut u8;
3376
3377/// Bitfield on register `UCSR1B`
3378pub const TXCIE1: *mut u8 = 0x40 as *mut u8;
3379
3380/// Bitfield on register `UCSR1B`
3381pub const UDRIE1: *mut u8 = 0x20 as *mut u8;
3382
3383/// Bitfield on register `UCSR1B`
3384pub const TXEN1: *mut u8 = 0x8 as *mut u8;
3385
3386/// Bitfield on register `UCSR1B`
3387pub const RXEN1: *mut u8 = 0x10 as *mut u8;
3388
3389/// Bitfield on register `UCSR1B`
3390pub const RXCIE1: *mut u8 = 0x80 as *mut u8;
3391
3392/// Bitfield on register `UCSR1C`
3393pub const UCPHA1: *mut u8 = 0x2 as *mut u8;
3394
3395/// Bitfield on register `UCSR1C`
3396pub const UDORD1: *mut u8 = 0x4 as *mut u8;
3397
3398/// Bitfield on register `UCSR1C`
3399pub const UCPOL1: *mut u8 = 0x1 as *mut u8;
3400
3401/// Bitfield on register `VREG_CTRL`
3402pub const DVREG_EXT: *mut u8 = 0x8 as *mut u8;
3403
3404/// Bitfield on register `VREG_CTRL`
3405pub const DVDD_OK: *mut u8 = 0x4 as *mut u8;
3406
3407/// Bitfield on register `VREG_CTRL`
3408pub const AVREG_EXT: *mut u8 = 0x80 as *mut u8;
3409
3410/// Bitfield on register `VREG_CTRL`
3411pub const AVDD_OK: *mut u8 = 0x40 as *mut u8;
3412
3413/// Bitfield on register `WDTCSR`
3414pub const WDCE: *mut u8 = 0x10 as *mut u8;
3415
3416/// Bitfield on register `WDTCSR`
3417pub const WDP: *mut u8 = 0x27 as *mut u8;
3418
3419/// Bitfield on register `WDTCSR`
3420pub const WDIE: *mut u8 = 0x40 as *mut u8;
3421
3422/// Bitfield on register `WDTCSR`
3423pub const WDE: *mut u8 = 0x8 as *mut u8;
3424
3425/// Bitfield on register `WDTCSR`
3426pub const WDIF: *mut u8 = 0x80 as *mut u8;
3427
3428/// Bitfield on register `XAH_CTRL_0`
3429pub const MAX_CSMA_RETRIES: *mut u8 = 0xE as *mut u8;
3430
3431/// Bitfield on register `XAH_CTRL_0`
3432pub const SLOTTED_OPERATION: *mut u8 = 0x1 as *mut u8;
3433
3434/// Bitfield on register `XAH_CTRL_0`
3435pub const MAX_FRAME_RETRIES: *mut u8 = 0xF0 as *mut u8;
3436
3437/// Bitfield on register `XAH_CTRL_1`
3438pub const AACK_UPLD_RES_FT: *mut u8 = 0x10 as *mut u8;
3439
3440/// Bitfield on register `XAH_CTRL_1`
3441pub const AACK_PROM_MODE: *mut u8 = 0x2 as *mut u8;
3442
3443/// Bitfield on register `XAH_CTRL_1`
3444pub const AACK_FLTR_RES_FT: *mut u8 = 0x20 as *mut u8;
3445
3446/// Bitfield on register `XAH_CTRL_1`
3447pub const AACK_ACK_TIME: *mut u8 = 0x4 as *mut u8;
3448
3449/// Bitfield on register `XOSC_CTRL`
3450pub const XTAL_TRIM: *mut u8 = 0xF as *mut u8;
3451
3452/// Bitfield on register `XOSC_CTRL`
3453pub const XTAL_MODE: *mut u8 = 0xF0 as *mut u8;
3454
3455/// `AACK_ACK_TIME_bitf` value group
3456#[allow(non_upper_case_globals)]
3457pub mod aack_ack_time_bitf {
3458 /// 12 symbols acknowledgment time.
3459 pub const AACK_ACK_TIME_12_SYM: u32 = 0x0;
3460 /// 2 symbols acknowledgment time.
3461 pub const AACK_ACK_TIME_2_SYM: u32 = 0x1;
3462}
3463
3464/// `AACK_FVN_MODE_bitf` value group
3465#[allow(non_upper_case_globals)]
3466pub mod aack_fvn_mode_bitf {
3467 /// Acknowledge frames with version number 0.
3468 pub const VAL_0: u32 = 0x0;
3469 /// Acknowledge frames with version number 0 or 1.
3470 pub const VAL_1: u32 = 0x1;
3471 /// Acknowledge frames with version number 0 or 1 or 2.
3472 pub const VAL_2: u32 = 0x2;
3473 /// Acknowledge frames independent of frame version number.
3474 pub const VAL_3: u32 = 0x3;
3475}
3476
3477/// `AES_DIRECTION_BITF` value group
3478#[allow(non_upper_case_globals)]
3479pub mod aes_direction_bitf {
3480 /// AES operation is encryption.
3481 pub const AES_DIR_ENC: u32 = 0x0;
3482 /// AES operation is decryption.
3483 pub const AES_DIR_DEC: u32 = 0x1;
3484}
3485
3486/// `AES_MODE_BITF` value group
3487#[allow(non_upper_case_globals)]
3488pub mod aes_mode_bitf {
3489 /// AES Mode is ECB (Electronic Code Book).
3490 pub const AES_MODE_ECB: u32 = 0x0;
3491 /// AES Mode is CBC (Cipher Block Chaining).
3492 pub const AES_MODE_CBC: u32 = 0x1;
3493}
3494
3495/// `ANALOG_ADC_AUTO_TRIGGER` value group
3496#[allow(non_upper_case_globals)]
3497pub mod analog_adc_auto_trigger {
3498 /// Free Running mode.
3499 pub const VAL_0x00: u32 = 0x0;
3500 /// Analog Comparator.
3501 pub const VAL_0x01: u32 = 0x1;
3502 /// External Interrupt Request 0.
3503 pub const VAL_0x02: u32 = 0x2;
3504 /// Timer/Counter0 Compare Match A.
3505 pub const VAL_0x03: u32 = 0x3;
3506 /// Timer/Counter0 Overflow.
3507 pub const VAL_0x04: u32 = 0x4;
3508 /// Timer/Counter1 Compare Match B.
3509 pub const VAL_0x05: u32 = 0x5;
3510 /// Timer/Counter1 Overflow.
3511 pub const VAL_0x06: u32 = 0x6;
3512 /// Timer/Counter1 Capture Event.
3513 pub const VAL_0x07: u32 = 0x7;
3514}
3515
3516/// `ANALOG_ADC_PRESCALER` value group
3517#[allow(non_upper_case_globals)]
3518pub mod analog_adc_prescaler {
3519 /// 2.
3520 pub const VAL_0x00: u32 = 0x0;
3521 /// 2.
3522 pub const VAL_0x01: u32 = 0x1;
3523 /// 4.
3524 pub const VAL_0x02: u32 = 0x2;
3525 /// 8.
3526 pub const VAL_0x03: u32 = 0x3;
3527 /// 16.
3528 pub const VAL_0x04: u32 = 0x4;
3529 /// 32.
3530 pub const VAL_0x05: u32 = 0x5;
3531 /// 64.
3532 pub const VAL_0x06: u32 = 0x6;
3533 /// 128.
3534 pub const VAL_0x07: u32 = 0x7;
3535}
3536
3537/// `ANALOG_ADC_STARTUP_TIME` value group
3538#[allow(non_upper_case_globals)]
3539pub mod analog_adc_startup_time {
3540 /// 3 ADC clock cycles.
3541 pub const VAL_0x00: u32 = 0x0;
3542 /// 7 ADC clock cycles.
3543 pub const VAL_0x01: u32 = 0x1;
3544 /// 11 ADC clock cycles.
3545 pub const VAL_0x02: u32 = 0x2;
3546 /// 15 ADC clock cycles.
3547 pub const VAL_0x03: u32 = 0x3;
3548 /// ...
3549 pub const VAL_0x04: u32 = 0x4;
3550 /// 251 ADC clock cycles.
3551 pub const VAL_0x3E: u32 = 0x3E;
3552 /// 255 ADC clock cycles.
3553 pub const VAL_0x3F: u32 = 0x3F;
3554}
3555
3556/// `ANALOG_ADC_TRACK_AND_HOLD_TIME` value group
3557#[allow(non_upper_case_globals)]
3558pub mod analog_adc_track_and_hold_time {
3559 /// Single ended: 1, differential 3 ADC clock cycles.
3560 pub const VAL_0x00: u32 = 0x0;
3561 /// Single ended: 2, differential 5 ADC clock cycles.
3562 pub const VAL_0x01: u32 = 0x1;
3563 /// Single ended: 3, differential 7 ADC clock cycles.
3564 pub const VAL_0x02: u32 = 0x2;
3565 /// Single ended: 4, differential 9 ADC clock cycles.
3566 pub const VAL_0x03: u32 = 0x3;
3567}
3568
3569/// `ANALOG_ADC_V_REF9` value group
3570#[allow(non_upper_case_globals)]
3571pub mod analog_adc_v_ref9 {
3572 /// AREF, Internal reference voltage generation turned off.
3573 pub const VAL_0x00: u32 = 0x0;
3574 /// AVDD with external capacitor at AREF pin.
3575 pub const VAL_0x01: u32 = 0x1;
3576 /// Internal 1.5V Voltage Reference (no external capacitor at AREF pin).
3577 pub const VAL_0x02: u32 = 0x2;
3578 /// Internal 1.6V Voltage Reference (no external capacitor at AREF pin).
3579 pub const VAL_0x03: u32 = 0x3;
3580}
3581
3582/// `ANALOG_COMP_INTERRUPT` value group
3583#[allow(non_upper_case_globals)]
3584pub mod analog_comp_interrupt {
3585 /// Interrupt on Toggle.
3586 pub const VAL_0x00: u32 = 0x0;
3587 /// Reserved.
3588 pub const VAL_0x01: u32 = 0x1;
3589 /// Interrupt on Falling Edge.
3590 pub const VAL_0x02: u32 = 0x2;
3591 /// Interrupt on Rising Edge.
3592 pub const VAL_0x03: u32 = 0x3;
3593}
3594
3595/// `ANT_CTRL_bitf` value group
3596#[allow(non_upper_case_globals)]
3597pub mod ant_ctrl_bitf {
3598 /// Reserved.
3599 pub const VAL_0: u32 = 0x0;
3600 /// Antenna 1: DIG1=H, DIG2=L.
3601 pub const ANT_1: u32 = 0x1;
3602 /// Antenna 0: DIG1=L, DIG2=H.
3603 pub const ANT_0: u32 = 0x2;
3604 /// Default value for ANT_EXT_SW_EN=0; Mandatory setting for applications not using Antenna Diversity.
3605 pub const ANT_RESET: u32 = 0x3;
3606}
3607
3608/// `ANT_DIV_EN_bitf` value group
3609#[allow(non_upper_case_globals)]
3610pub mod ant_div_en_bitf {
3611 /// Antenna Diversity algorithm disabled.
3612 pub const VAL_0: u32 = 0x0;
3613 /// Antenna Diversity algorithm enabled.
3614 pub const VAL_1: u32 = 0x1;
3615}
3616
3617/// `ANT_EXT_SW_EN_bitf` value group
3618#[allow(non_upper_case_globals)]
3619pub mod ant_ext_sw_en_bitf {
3620 /// Antenna Diversity RF switch control disabled.
3621 pub const ANT_DIV_EXT_SW_DIS: u32 = 0x0;
3622 /// Antenna Diversity RF switch control enabled.
3623 pub const ANT_DIV_EXT_SW_EN: u32 = 0x1;
3624}
3625
3626/// `ANT_SEL_bitf` value group
3627#[allow(non_upper_case_globals)]
3628pub mod ant_sel_bitf {
3629 /// Antenna 0.
3630 pub const ANTENNA_0: u32 = 0x0;
3631 /// Antenna 1.
3632 pub const ANTENNA_1: u32 = 0x1;
3633}
3634
3635/// `AVDD_OK_BITF` value group
3636#[allow(non_upper_case_globals)]
3637pub mod avdd_ok_bitf {
3638 /// Analog voltage regulator disabled or supply voltage not stable.
3639 pub const VAL_0: u32 = 0x0;
3640 /// Analog supply voltage has settled.
3641 pub const VAL_1: u32 = 0x1;
3642}
3643
3644/// `AVREG_EXT_BITF` value group
3645#[allow(non_upper_case_globals)]
3646pub mod avreg_ext_bitf {
3647 /// Internal AVDD voltage regulator for the analog section is enabled.
3648 pub const AVDD_INT: u32 = 0x0;
3649 /// Internal AVDD voltage regulator is disabled; use external regulated 1.8V supply voltage for the analog section.
3650 pub const AVDD_EXT: u32 = 0x1;
3651}
3652
3653/// `BATMON_HR_bitf` value group
3654#[allow(non_upper_case_globals)]
3655pub mod batmon_hr_bitf {
3656 /// Enables the low range, see BATMON_VTH.
3657 pub const BATMON_HR_DIS: u32 = 0x0;
3658 /// Enables the high range, see BATMON_VTH.
3659 pub const BATMON_HR_EN: u32 = 0x1;
3660}
3661
3662/// `BATMON_OK_bitf` value group
3663#[allow(non_upper_case_globals)]
3664pub mod batmon_ok_bitf {
3665 /// The battery voltage is below the threshold.
3666 pub const VAL_0: u32 = 0x0;
3667 /// The battery voltage is above the threshold.
3668 pub const VAL_1: u32 = 0x1;
3669}
3670
3671/// `BATMON_VTH_bitf` value group
3672#[allow(non_upper_case_globals)]
3673pub mod batmon_vth_bitf {
3674 /// 2.550V / 1.70V (BATMON_HR=1/0).
3675 pub const VAL_0x0: u32 = 0x0;
3676 /// 2.625V / 1.75V (BATMON_HR=1/0).
3677 pub const VAL_0x1: u32 = 0x1;
3678 /// 2.700V / 1.80V (BATMON_HR=1/0).
3679 pub const VAL_0x2: u32 = 0x2;
3680 /// 2.775V / 1.85V (BATMON_HR=1/0).
3681 pub const VAL_0x3: u32 = 0x3;
3682 /// 2.850V / 1.90V (BATMON_HR=1/0).
3683 pub const VAL_0x4: u32 = 0x4;
3684 /// 2.925V / 1.95V (BATMON_HR=1/0).
3685 pub const VAL_0x5: u32 = 0x5;
3686 /// 3.000V / 2.00V (BATMON_HR=1/0).
3687 pub const VAL_0x6: u32 = 0x6;
3688 /// 3.075V / 2.05V (BATMON_HR=1/0).
3689 pub const VAL_0x7: u32 = 0x7;
3690 /// 3.150V / 2.10V (BATMON_HR=1/0).
3691 pub const VAL_0x8: u32 = 0x8;
3692 /// 3.225V / 2.15V (BATMON_HR=1/0).
3693 pub const VAL_0x9: u32 = 0x9;
3694 /// 3.300V / 2.20V (BATMON_HR=1/0).
3695 pub const VAL_0xA: u32 = 0xA;
3696 /// 3.375V / 2.25V (BATMON_HR=1/0).
3697 pub const VAL_0xB: u32 = 0xB;
3698 /// 3.450V / 2.30V (BATMON_HR=1/0).
3699 pub const VAL_0xC: u32 = 0xC;
3700 /// 3.525V / 2.35V (BATMON_HR=1/0).
3701 pub const VAL_0xD: u32 = 0xD;
3702 /// 3.600V / 2.40V (BATMON_HR=1/0).
3703 pub const VAL_0xE: u32 = 0xE;
3704 /// 3.675V / 2.45V (BATMON_HR=1/0).
3705 pub const VAL_0xF: u32 = 0xF;
3706}
3707
3708/// `BGCAL_BITF` value group
3709#[allow(non_upper_case_globals)]
3710pub mod bgcal_bitf {
3711 /// Center value.
3712 pub const VAL_4: u32 = 0x4;
3713 /// Voltage step up.
3714 pub const VAL_3: u32 = 0x3;
3715 /// Voltage step down.
3716 pub const VAL_5: u32 = 0x5;
3717 /// Setting for highest voltage.
3718 pub const VAL_0: u32 = 0x0;
3719 /// Setting for lowest voltage.
3720 pub const VAL_7: u32 = 0x7;
3721}
3722
3723/// `BGCAL_FINE_BITF` value group
3724#[allow(non_upper_case_globals)]
3725pub mod bgcal_fine_bitf {
3726 /// Center value.
3727 pub const VAL_0: u32 = 0x0;
3728 /// Voltage step up.
3729 pub const VAL_1: u32 = 0x1;
3730 /// Voltage step down.
3731 pub const VAL_8: u32 = 0x8;
3732 /// Setting for highest voltage.
3733 pub const VAL_7: u32 = 0x7;
3734 /// Setting for lowest voltage.
3735 pub const VAL_15: u32 = 0xF;
3736}
3737
3738/// `CCA_DONE_bitf` value group
3739#[allow(non_upper_case_globals)]
3740pub mod cca_done_bitf {
3741 /// CCA calculation not finished.
3742 pub const CCA_NOT_FIN: u32 = 0x0;
3743 /// CCA calculation finished.
3744 pub const CCA_FIN: u32 = 0x1;
3745}
3746
3747/// `CCA_MODE_bitf` value group
3748#[allow(non_upper_case_globals)]
3749pub mod cca_mode_bitf {
3750 /// Mode 3a, Carrier sense OR energy above threshold.
3751 pub const CCA_CS_OR_ED: u32 = 0x0;
3752 /// Mode 1, Energy above threshold.
3753 pub const CCA_ED: u32 = 0x1;
3754 /// Mode 2, Carrier sense only.
3755 pub const CCA_CS: u32 = 0x2;
3756 /// Mode 3b, Carrier sense AND energy above threshold.
3757 pub const CCA_CS_AND_ED: u32 = 0x3;
3758}
3759
3760/// `CCA_STATUS_bitf` value group
3761#[allow(non_upper_case_globals)]
3762pub mod cca_status_bitf {
3763 /// Channel indicated as busy.
3764 pub const CCA_BUSY: u32 = 0x0;
3765 /// Channel indicated as idle.
3766 pub const CCA_IDLE: u32 = 0x1;
3767}
3768
3769/// `CHANNEL_bitf` value group
3770#[allow(non_upper_case_globals)]
3771pub mod channel_bitf {
3772 /// 2405 MHz.
3773 pub const F_2405MHZ: u32 = 0xB;
3774 /// 2410 MHz.
3775 pub const F_2410MHZ: u32 = 0xC;
3776 /// 2415 MHz.
3777 pub const F_2415MHZ: u32 = 0xD;
3778 /// 2420 MHz.
3779 pub const F_2420MHZ: u32 = 0xE;
3780 /// 2425 MHz.
3781 pub const F_2425MHZ: u32 = 0xF;
3782 /// 2430 MHz.
3783 pub const F_2430MHZ: u32 = 0x10;
3784 /// 2435 MHz.
3785 pub const F_2435MHZ: u32 = 0x11;
3786 /// 2440 MHz.
3787 pub const F_2440MHZ: u32 = 0x12;
3788 /// 2445 MHz.
3789 pub const F_2445MHZ: u32 = 0x13;
3790 /// 2450 MHz.
3791 pub const F_2450MHZ: u32 = 0x14;
3792 /// 2455 MHz.
3793 pub const F_2455MHZ: u32 = 0x15;
3794 /// 2460 MHz.
3795 pub const F_2460MHZ: u32 = 0x16;
3796 /// 2465 MHz.
3797 pub const F_2465MHZ: u32 = 0x17;
3798 /// 2470 MHz.
3799 pub const F_2470MHZ: u32 = 0x18;
3800 /// 2475 MHz.
3801 pub const F_2475MHZ: u32 = 0x19;
3802 /// 2480 MHz.
3803 pub const F_2480MHZ: u32 = 0x1A;
3804}
3805
3806/// `CLK_SEL_3BIT_EXT_MEGARF` value group
3807#[allow(non_upper_case_globals)]
3808pub mod clk_sel_3bit_ext_megarf {
3809 /// No clock source (Timer/Counter stopped).
3810 pub const VAL_0x00: u32 = 0x0;
3811 /// clk_IO/1 (no prescaling).
3812 pub const VAL_0x01: u32 = 0x1;
3813 /// clk_IO/8 (from prescaler).
3814 pub const VAL_0x02: u32 = 0x2;
3815 /// clk_IO/64 (from prescaler).
3816 pub const VAL_0x03: u32 = 0x3;
3817 /// clk_IO/256 (from prescaler).
3818 pub const VAL_0x04: u32 = 0x4;
3819 /// clk_IO/1024 (from prescaler).
3820 pub const VAL_0x05: u32 = 0x5;
3821 /// External clock source on Tn pin, clock on falling edge.
3822 pub const VAL_0x06: u32 = 0x6;
3823 /// External clock source on Tn pin, clock on rising edge.
3824 pub const VAL_0x07: u32 = 0x7;
3825}
3826
3827/// `CLK_SEL_3BIT_NOEXT_MEGARF` value group
3828#[allow(non_upper_case_globals)]
3829pub mod clk_sel_3bit_noext_megarf {
3830 /// No clock source (Timer/Counter stopped).
3831 pub const VAL_0x00: u32 = 0x0;
3832 /// clk_IO/1 (no prescaling).
3833 pub const VAL_0x01: u32 = 0x1;
3834 /// clk_IO/8 (from prescaler).
3835 pub const VAL_0x02: u32 = 0x2;
3836 /// clk_IO/64 (from prescaler).
3837 pub const VAL_0x03: u32 = 0x3;
3838 /// clk_IO/256 (from prescaler).
3839 pub const VAL_0x04: u32 = 0x4;
3840 /// clk_IO/1024 (from prescaler).
3841 pub const VAL_0x05: u32 = 0x5;
3842 /// Reserved.
3843 pub const VAL_0x06: u32 = 0x6;
3844 /// Reserved.
3845 pub const VAL_0x07: u32 = 0x7;
3846}
3847
3848/// `COMM_SCK_RATE_SPI2X` value group
3849#[allow(non_upper_case_globals)]
3850pub mod comm_sck_rate_spi2x {
3851 /// fosc/4 / fosc/2 (SPI2X=0/1).
3852 pub const VAL_0x00: u32 = 0x0;
3853 /// fosc/16 / fosc/8 (SPI2X=0/1).
3854 pub const VAL_0x01: u32 = 0x1;
3855 /// fosc/64 / fosc/32 (SPI2X=0/1).
3856 pub const VAL_0x02: u32 = 0x2;
3857 /// fosc/128 / fosc/64 (SPI2X=0/1).
3858 pub const VAL_0x03: u32 = 0x3;
3859}
3860
3861/// `COMM_STOP_BIT_SEL` value group
3862#[allow(non_upper_case_globals)]
3863pub mod comm_stop_bit_sel {
3864 /// 1-bit.
3865 pub const VAL_0x00: u32 = 0x0;
3866 /// 2-bit.
3867 pub const VAL_0x01: u32 = 0x1;
3868}
3869
3870/// `COMM_TWI_PRESACLE` value group
3871#[allow(non_upper_case_globals)]
3872pub mod comm_twi_presacle {
3873 /// 1.
3874 pub const VAL_0x00: u32 = 0x0;
3875 /// 4.
3876 pub const VAL_0x01: u32 = 0x1;
3877 /// 16.
3878 pub const VAL_0x02: u32 = 0x2;
3879 /// 64.
3880 pub const VAL_0x03: u32 = 0x3;
3881}
3882
3883/// `COMM_UPM_PARITY_MODE` value group
3884#[allow(non_upper_case_globals)]
3885pub mod comm_upm_parity_mode {
3886 /// Disabled.
3887 pub const VAL_0x00: u32 = 0x0;
3888 /// Reserved.
3889 pub const VAL_0x01: u32 = 0x1;
3890 /// Enabled, Even Parity.
3891 pub const VAL_0x02: u32 = 0x2;
3892 /// Enabled, Odd Parity.
3893 pub const VAL_0x03: u32 = 0x3;
3894}
3895
3896/// `COMM_USART_MODE_2BIT_MEGARF` value group
3897#[allow(non_upper_case_globals)]
3898pub mod comm_usart_mode_2bit_megarf {
3899 /// Asynchronous USART.
3900 pub const VAL_0x00: u32 = 0x0;
3901 /// Synchronous USART.
3902 pub const VAL_0x01: u32 = 0x1;
3903 /// Reserved.
3904 pub const VAL_0x02: u32 = 0x2;
3905 /// Master SPI (MSPIM).
3906 pub const VAL_0x03: u32 = 0x3;
3907}
3908
3909/// `CPU_CLK_PRESCALE_4_BITS_SMALL_MEGARF` value group
3910#[allow(non_upper_case_globals)]
3911pub mod cpu_clk_prescale_4_bits_small_megarf {
3912 /// Division factor 1 / RC-Oscillator 2.
3913 pub const VAL_0x0: u32 = 0x0;
3914 /// Division factor 2 / RC-Oscillator 4.
3915 pub const VAL_0x1: u32 = 0x1;
3916 /// Division factor 4 / RC-Oscillator 8.
3917 pub const VAL_0x2: u32 = 0x2;
3918 /// Division factor 8 / RC-Oscillator 16.
3919 pub const VAL_0x3: u32 = 0x3;
3920 /// Division factor 16 / RC-Oscillator 32.
3921 pub const VAL_0x4: u32 = 0x4;
3922 /// Division factor 32 / RC-Oscillator 64.
3923 pub const VAL_0x5: u32 = 0x5;
3924 /// Division factor 64 / RC-Oscillator 128.
3925 pub const VAL_0x6: u32 = 0x6;
3926 /// Division factor 128 / RC-Oscillator 256.
3927 pub const VAL_0x7: u32 = 0x7;
3928 /// Division factor 256 / RC-Oscillator 512.
3929 pub const VAL_0x8: u32 = 0x8;
3930 /// Reserved.
3931 pub const VAL_0x9: u32 = 0x9;
3932 /// Reserved.
3933 pub const VAL_0xA: u32 = 0xA;
3934 /// Reserved.
3935 pub const VAL_0xB: u32 = 0xB;
3936 /// Reserved.
3937 pub const VAL_0xC: u32 = 0xC;
3938 /// Reserved.
3939 pub const VAL_0xD: u32 = 0xD;
3940 /// Reserved.
3941 pub const VAL_0xE: u32 = 0xE;
3942 /// Division factor 1 only permitted for RC-Oscillator. Flash and EEPROM programming is not allowed.
3943 pub const VAL_0xF: u32 = 0xF;
3944}
3945
3946/// `CPU_SLEEP_MODE_3BITS` value group
3947#[allow(non_upper_case_globals)]
3948pub mod cpu_sleep_mode_3bits {
3949 /// Idle.
3950 pub const IDLE: u32 = 0x0;
3951 /// ADC Noise Reduction (If Available).
3952 pub const ADC: u32 = 0x1;
3953 /// Power Down.
3954 pub const PDOWN: u32 = 0x2;
3955 /// Power Save.
3956 pub const PSAVE: u32 = 0x3;
3957 /// Reserved.
3958 pub const VAL_0x04: u32 = 0x4;
3959 /// Reserved.
3960 pub const VAL_0x05: u32 = 0x5;
3961 /// Standby.
3962 pub const STDBY: u32 = 0x6;
3963 /// Extended Standby.
3964 pub const ESTDBY: u32 = 0x7;
3965}
3966
3967/// `DVDD_OK_BITF` value group
3968#[allow(non_upper_case_globals)]
3969pub mod dvdd_ok_bitf {
3970 /// Digital voltage regulator disabled or supply voltage not stable.
3971 pub const VAL_0: u32 = 0x0;
3972 /// Digital supply voltage has settled.
3973 pub const VAL_1: u32 = 0x1;
3974}
3975
3976/// `DVREG_EXT_BITF` value group
3977#[allow(non_upper_case_globals)]
3978pub mod dvreg_ext_bitf {
3979 /// Internal DVDD voltage regulator for the digital section is enabled.
3980 pub const DVDD_INT: u32 = 0x0;
3981 /// Internal DVDD voltage regulator is disabled; use external regulated 1.8V supply voltage for the digital section.
3982 pub const DVDD_EXT: u32 = 0x1;
3983}
3984
3985/// `ED_LEVEL_BITF` value group
3986#[allow(non_upper_case_globals)]
3987pub mod ed_level_bitf {
3988 /// Minimum result of last ED measurement.
3989 pub const ED_MIN: u32 = 0x0;
3990 /// P(RF) = RSSI_BASE_VAL+ED \[dBm\].
3991 pub const ED_MIN_PLUS_1dB: u32 = 0x1;
3992 /// ...
3993 pub const VAL_0x02: u32 = 0x2;
3994 /// Maximum result of last ED measurement.
3995 pub const ED_MAX: u32 = 0x54;
3996 /// Reset value.
3997 pub const ED_RESET: u32 = 0xFF;
3998}
3999
4000/// `EEP_MODE2` value group
4001#[allow(non_upper_case_globals)]
4002pub mod eep_mode2 {
4003 /// Erase and Write in one operation (Atomic Operation).
4004 pub const VAL_0x00: u32 = 0x0;
4005 /// Erase only.
4006 pub const VAL_0x01: u32 = 0x1;
4007 /// Write only.
4008 pub const VAL_0x02: u32 = 0x2;
4009 /// Reserved for future use.
4010 pub const VAL_0x03: u32 = 0x3;
4011}
4012
4013/// `ENUM_BLB` value group
4014#[allow(non_upper_case_globals)]
4015pub mod enum_blb {
4016 /// LPM and SPM prohibited in Application Section.
4017 pub const LPM_SPM_DISABLE: u32 = 0x0;
4018 /// LPM prohibited in Application Section.
4019 pub const LPM_DISABLE: u32 = 0x1;
4020 /// SPM prohibited in Application Section.
4021 pub const SPM_DISABLE: u32 = 0x2;
4022 /// No lock on SPM and LPM in Application Section.
4023 pub const NO_LOCK: u32 = 0x3;
4024}
4025
4026/// `ENUM_BLB2` value group
4027#[allow(non_upper_case_globals)]
4028pub mod enum_blb2 {
4029 /// LPM and SPM prohibited in Boot Section.
4030 pub const LPM_SPM_DISABLE: u32 = 0x0;
4031 /// LPM prohibited in Boot Section.
4032 pub const LPM_DISABLE: u32 = 0x1;
4033 /// SPM prohibited in Boot Section.
4034 pub const SPM_DISABLE: u32 = 0x2;
4035 /// No lock on SPM and LPM in Boot Section.
4036 pub const NO_LOCK: u32 = 0x3;
4037}
4038
4039/// `ENUM_BODLEVEL` value group
4040#[allow(non_upper_case_globals)]
4041pub mod enum_bodlevel {
4042 /// Brown-out detection disabled.
4043 pub const DISABLED: u32 = 0x7;
4044 /// Brown-out detection at VCC=1.8 V.
4045 pub const _1V8: u32 = 0x6;
4046 /// Brown-out detection at VCC=1.9 V.
4047 pub const _1V9: u32 = 0x5;
4048 /// Brown-out detection at VCC=2.0 V.
4049 pub const _2V0: u32 = 0x4;
4050 /// Brown-out detection at VCC=2.1 V.
4051 pub const _2V1: u32 = 0x3;
4052 /// Brown-out detection at VCC=2.2 V.
4053 pub const _2V2: u32 = 0x2;
4054 /// Brown-out detection at VCC=2.3 V.
4055 pub const _2V3: u32 = 0x1;
4056 /// Brown-out detection at VCC=2.4 V.
4057 pub const _2V4: u32 = 0x0;
4058}
4059
4060/// `ENUM_BOOTSZ` value group
4061#[allow(non_upper_case_globals)]
4062pub mod enum_bootsz {
4063 /// Boot Flash size=512 words start address=$7E00.
4064 pub const _512W_7E00: u32 = 0x3;
4065 /// Boot Flash size=1024 words start address=$7C00.
4066 pub const _1024W_7C00: u32 = 0x2;
4067 /// Boot Flash size=2048 words start address=$7800.
4068 pub const _2048W_7800: u32 = 0x1;
4069 /// Boot Flash size=4096 words start address=$7000.
4070 pub const _4096W_7000: u32 = 0x0;
4071}
4072
4073/// `ENUM_LB` value group
4074#[allow(non_upper_case_globals)]
4075pub mod enum_lb {
4076 /// Further programming and verification disabled.
4077 pub const PROG_VER_DISABLED: u32 = 0x0;
4078 /// Further programming disabled.
4079 pub const PROG_DISABLED: u32 = 0x2;
4080 /// No memory lock features enabled.
4081 pub const NO_LOCK: u32 = 0x3;
4082}
4083
4084/// `ENUM_SUT_CKSEL` value group
4085#[allow(non_upper_case_globals)]
4086pub mod enum_sut_cksel {
4087 /// Ext. Clock; Start-up time: 6 CK + 0 ms.
4088 pub const EXTCLK_6CK_0MS: u32 = 0x0;
4089 /// Ext. Clock; Start-up time: 6 CK + 4.1 ms.
4090 pub const EXTCLK_6CK_4MS1: u32 = 0x10;
4091 /// Ext. Clock; Start-up time: 6 CK + 65 ms.
4092 pub const EXTCLK_6CK_65MS: u32 = 0x20;
4093 /// Int. RC Osc.; Start-up time: 6 CK + 0 ms.
4094 pub const INTRCOSC_6CK_0MS: u32 = 0x2;
4095 /// Int. RC Osc.; Start-up time: 6 CK + 4.1 ms.
4096 pub const INTRCOSC_6CK_4MS1: u32 = 0x12;
4097 /// Int. RC Osc.; Start-up time: 6 CK + 65 ms.
4098 pub const INTRCOSC_6CK_65MS: u32 = 0x22;
4099 /// Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms.
4100 pub const INTRCOSC_128KHZ_6CK_0MS: u32 = 0x3;
4101 /// Int. 128kHz RC Osc.; Start-up time: 6 CK + 4.1 ms.
4102 pub const INTRCOSC_128KHZ_6CK_4MS1: u32 = 0x13;
4103 /// Int. 128kHz RC Osc.; Start-up time: 6 CK + 65 ms.
4104 pub const INTRCOSC_128KHZ_6CK_65MS: u32 = 0x23;
4105}
4106
4107/// `INTERRUPT_EXT_FLAG_BITF` value group
4108#[allow(non_upper_case_globals)]
4109pub mod interrupt_ext_flag_bitf {
4110 /// No edge or logic change on INT7:0 occurred.
4111 pub const VAL_0x00: u32 = 0x0;
4112 /// A edge or logic change on INT0 occurred and triggered an interrupt request.
4113 pub const VAL_0x01: u32 = 0x1;
4114 /// ...
4115 pub const VAL_0x02: u32 = 0x2;
4116 /// A edge or logic change on INT7 occurred and triggered an interrupt request.
4117 pub const VAL_0x80: u32 = 0x80;
4118}
4119
4120/// `INTERRUPT_REQ_ENABLE_BITF` value group
4121#[allow(non_upper_case_globals)]
4122pub mod interrupt_req_enable_bitf {
4123 /// All external pin interrupts are disabled.
4124 pub const VAL_0x00: u32 = 0x0;
4125 /// All external pin interrupts are enabled.
4126 pub const VAL_0xff: u32 = 0xFF;
4127}
4128
4129/// `INTERRUPT_SENSE_CONTROL3` value group
4130#[allow(non_upper_case_globals)]
4131pub mod interrupt_sense_control3 {
4132 /// The low level of INTn generates an interrupt request.
4133 pub const VAL_0x00: u32 = 0x0;
4134 /// Any edge of INTn generates asynchronously an interrupt request.
4135 pub const VAL_0x01: u32 = 0x1;
4136 /// The falling edge of INTn generates asynchronously an interrupt request.
4137 pub const VAL_0x02: u32 = 0x2;
4138 /// The rising edge of INTn generates asynchronously an interrupt request.
4139 pub const VAL_0x03: u32 = 0x3;
4140}
4141
4142/// `LLDRH_VALUE_BITF` value group
4143#[allow(non_upper_case_globals)]
4144pub mod lldrh_value_bitf {
4145 /// Calibration limit for fast process corner/high output voltage.
4146 pub const VAL_0x00: u32 = 0x0;
4147 /// Calibration limit for slow process corner/low output voltage.
4148 pub const VAL_0x10: u32 = 0x10;
4149}
4150
4151/// `LLDRL_VALUE_BITF` value group
4152#[allow(non_upper_case_globals)]
4153pub mod lldrl_value_bitf {
4154 /// Calibration limit for fast process corner/high output voltage.
4155 pub const VAL_0x00: u32 = 0x0;
4156 /// Calibration limit for slow process corner/low output voltage.
4157 pub const VAL_0x08: u32 = 0x8;
4158}
4159
4160/// `MAN_ID_0_BITF` value group
4161#[allow(non_upper_case_globals)]
4162pub mod man_id_0_bitf {
4163 /// Atmel JEDEC manufacturer ID, bits \[7:0\] of 32 bit manufacturer ID: 00 00 00 1F.
4164 pub const ATMEL_BYTE_0: u32 = 0x1F;
4165}
4166
4167/// `MAN_ID_1_BITF` value group
4168#[allow(non_upper_case_globals)]
4169pub mod man_id_1_bitf {
4170 /// Atmel JEDEC manufacturer ID, bits \[15:8\] of 32 bit manufacturer ID: 00 00 00 1F.
4171 pub const ATMEL_BYTE_1: u32 = 0x0;
4172}
4173
4174/// `MAX_BE_bitf` value group
4175#[allow(non_upper_case_globals)]
4176pub mod max_be_bitf {
4177 /// This value is not valid for the maximum back-off exponent.
4178 pub const VAL_1: u32 = 0x1;
4179 /// This value is not valid for the maximum back-off exponent.
4180 pub const VAL_2: u32 = 0x2;
4181 /// Minimum, IEEE compliant value for the maximum back-off exponent.
4182 pub const VAL_3: u32 = 0x3;
4183 /// ...
4184 pub const VAL_4: u32 = 0x4;
4185 /// Maximum, IEEE compliant value for the maximum back-off exponent.
4186 pub const VAL_8: u32 = 0x8;
4187}
4188
4189/// `MAX_CSMA_RETRIES_bitf` value group
4190#[allow(non_upper_case_globals)]
4191pub mod max_csma_retries_bitf {
4192 /// No repetition of CSMA-CA procedure.
4193 pub const VAL_0x0: u32 = 0x0;
4194 /// One repetition of CSMA-CA procedure.
4195 pub const VAL_0x1: u32 = 0x1;
4196 /// ...
4197 pub const VAL_0x2: u32 = 0x2;
4198 /// Five repetitions (highest IEEE 802.15.4 compliant value).
4199 pub const VAL_0x5: u32 = 0x5;
4200 /// Reserved.
4201 pub const VAL_0x6: u32 = 0x6;
4202 /// Immediate frame re-transmission without performing CSMA-CA.
4203 pub const VAL_0x7: u32 = 0x7;
4204}
4205
4206/// `MAX_FRAME_RETRIES_bitf` value group
4207#[allow(non_upper_case_globals)]
4208pub mod max_frame_retries_bitf {
4209 /// Retransmission of frame is not attempted.
4210 pub const VAL_0x0: u32 = 0x0;
4211 /// Retransmission of frame is attempted once.
4212 pub const VAL_0x1: u32 = 0x1;
4213 /// ...
4214 pub const VAL_0x2: u32 = 0x2;
4215 /// Retransmission of frame is attempted 15 times.
4216 pub const VAL_0xF: u32 = 0xF;
4217}
4218
4219/// `MIN_BE_bitf` value group
4220#[allow(non_upper_case_globals)]
4221pub mod min_be_bitf {
4222 /// Minimum value of minimum back-off exponent.
4223 pub const VAL_0: u32 = 0x0;
4224 /// ...
4225 pub const VAL_1: u32 = 0x1;
4226 /// Maximum value of minimum back-off exponent. MIN_BE must be smaller or equal to MAX_BE.
4227 pub const VAL_8: u32 = 0x8;
4228}
4229
4230/// `NEMCR_ADDRESS_BITF` value group
4231#[allow(non_upper_case_globals)]
4232pub mod nemcr_address_bitf {
4233 /// Factory Row.
4234 pub const VAL_0: u32 = 0x0;
4235 /// User Row 1.
4236 pub const VAL_1: u32 = 0x1;
4237 /// User Row 2.
4238 pub const VAL_2: u32 = 0x2;
4239 /// User Row 3.
4240 pub const VAL_3: u32 = 0x3;
4241}
4242
4243/// `OCDR_DATA_BITF` value group
4244#[allow(non_upper_case_globals)]
4245pub mod ocdr_data_bitf {
4246 /// Refer to the debugger documentation for further information on how to use this register.
4247 pub const VAL_0: u32 = 0x0;
4248}
4249
4250/// `OQPSK_DATA_RATE_bitf` value group
4251#[allow(non_upper_case_globals)]
4252pub mod oqpsk_data_rate_bitf {
4253 /// 250 kb/s (IEEE 802.15.4 compliant).
4254 pub const RATE_250KB: u32 = 0x0;
4255 /// 500 kb/s.
4256 pub const RATE_500KB: u32 = 0x1;
4257 /// 1000 kb/s.
4258 pub const RATE_1000KB: u32 = 0x2;
4259 /// 2000 kb/s.
4260 pub const RATE_2000KB: u32 = 0x3;
4261}
4262
4263/// `OSCCAL_BITF` value group
4264#[allow(non_upper_case_globals)]
4265pub mod osccal_bitf {
4266 /// Calibration value for lowest oscillator frequency.
4267 pub const VAL_0x00: u32 = 0x0;
4268 /// End value of low frequency range calibration.
4269 pub const VAL_0x7f: u32 = 0x7F;
4270 /// Start value of high frequency range calibration.
4271 pub const VAL_0x80: u32 = 0x80;
4272 /// Calibration value for highest oscillator frequency.
4273 pub const VAL_0xff: u32 = 0xFF;
4274}
4275
4276/// Oscillator Calibration Values
4277#[allow(non_upper_case_globals)]
4278pub mod osccal_value_addresses {
4279 /// 16.0 MHz.
4280 pub const _16_0_MHz: u32 = 0x0;
4281}
4282
4283/// `PAD_IO_bitf` value group
4284#[allow(non_upper_case_globals)]
4285pub mod pad_io_bitf {
4286 /// 2 mA.
4287 pub const PAD_IO_2MA: u32 = 0x0;
4288 /// 4 mA.
4289 pub const PAD_IO_4MA: u32 = 0x1;
4290 /// 6 mA.
4291 pub const PAD_IO_6MA: u32 = 0x2;
4292 /// 8 mA.
4293 pub const PAD_IO_8MA: u32 = 0x3;
4294}
4295
4296/// `PALTD_bitf` value group
4297#[allow(non_upper_case_globals)]
4298pub mod paltd_bitf {
4299 /// -3us.
4300 pub const PALTD_MINUS_3US: u32 = 0x0;
4301 /// -2us.
4302 pub const PALTD_MINUS_2US: u32 = 0x1;
4303 /// -1us.
4304 pub const PALTD_MINUS_1US: u32 = 0x2;
4305 /// 0us.
4306 pub const PALTD_0US: u32 = 0x3;
4307 /// 1us.
4308 pub const PALTD_1US: u32 = 0x4;
4309 /// 2us.
4310 pub const PALTD_2US: u32 = 0x5;
4311 /// 3us.
4312 pub const PALTD_3US: u32 = 0x6;
4313 /// 4us.
4314 pub const PALTD_4US: u32 = 0x7;
4315}
4316
4317/// `PALTU_bitf` value group
4318#[allow(non_upper_case_globals)]
4319pub mod paltu_bitf {
4320 /// -3us.
4321 pub const PALTU_MINUS_3US: u32 = 0x0;
4322 /// -2us.
4323 pub const PALTU_MINUS_2US: u32 = 0x1;
4324 /// -1us.
4325 pub const PALTU_MINUS_1US: u32 = 0x2;
4326 /// 0us.
4327 pub const PALTU_0US: u32 = 0x3;
4328 /// 1us.
4329 pub const PALTU_1US: u32 = 0x4;
4330 /// 2us.
4331 pub const PALTU_2US: u32 = 0x5;
4332 /// 3us.
4333 pub const PALTU_3US: u32 = 0x6;
4334 /// 4us.
4335 pub const PALTU_4US: u32 = 0x7;
4336}
4337
4338/// `PART_NUM_bitf` value group
4339#[allow(non_upper_case_globals)]
4340pub mod part_num_bitf {
4341 /// ATmega128RFA1 part number.
4342 pub const P_ATmega128RFA1: u32 = 0x83;
4343 /// RFA2 family.
4344 pub const P_RFA2: u32 = 0x93;
4345 /// RFR2 family.
4346 pub const P_RFR2: u32 = 0x94;
4347}
4348
4349/// `PDT_THRES_bitf` value group
4350#[allow(non_upper_case_globals)]
4351pub mod pdt_thres_bitf {
4352 /// Reset value, to be used if Antenna Diversity algorithm is disabled.
4353 pub const PDT_THRES_ANT_DIV_OFF: u32 = 0x7;
4354 /// Recommended correlator threshold for Antenna Diversity operation.
4355 pub const PDT_THRES_ANT_DIV_ON: u32 = 0x3;
4356}
4357
4358/// `RSSI_VALUE_BITF` value group
4359#[allow(non_upper_case_globals)]
4360pub mod rssi_value_bitf {
4361 /// Minimum RSSI value: P(RF) < -90 dBm.
4362 pub const RSSI_MIN: u32 = 0x0;
4363 /// P(RF) = RSSI_BASE_VAL+3 · (RSSI-1) \[dBm\].
4364 pub const RSSI_MIN_PLUS_3dB: u32 = 0x1;
4365 /// ...
4366 pub const VAL_2: u32 = 0x2;
4367 /// Maximum RSSI value: P(RF) ≥ -10 dBm.
4368 pub const RSSI_MAX: u32 = 0x1C;
4369}
4370
4371/// `RX_CRC_VALID_bitf` value group
4372#[allow(non_upper_case_globals)]
4373pub mod rx_crc_valid_bitf {
4374 /// CRC (FCS) not valid.
4375 pub const CRC_INVALID: u32 = 0x0;
4376 /// CRC (FCS) valid.
4377 pub const CRC_VALID: u32 = 0x1;
4378}
4379
4380/// `RX_PDT_LEVEL_BITF` value group
4381#[allow(non_upper_case_globals)]
4382pub mod rx_pdt_level_bitf {
4383 /// RX_THRES ≤ RSSI_BASE_VAL (Reset value); RSSI value not considered.
4384 pub const RX_PDT_LEVEL_MIN: u32 = 0x0;
4385 /// RX_THRES > RSSI_BASE_VAL + 0 · 3; RSSI > -90 dBm.
4386 pub const VAL_0x1: u32 = 0x1;
4387 /// ...
4388 pub const VAL_0x2: u32 = 0x2;
4389 /// RX_THRES > RSSI_BASE_VAL + 13 · 3; RSSI > -51 dBm.
4390 pub const VAL_0xE: u32 = 0xE;
4391 /// RX_THRES > RSSI_BASE_VAL + 14 · 3; RSSI > -48 dBm.
4392 pub const RX_PDT_LEVEL_MAX: u32 = 0xF;
4393}
4394
4395/// `RX_RPC_CTRL_BITF` value group
4396#[allow(non_upper_case_globals)]
4397pub mod rx_rpc_ctrl_bitf {
4398 /// Activates minimum power saving behaviour for smart receiving mode.
4399 pub const VAL_0: u32 = 0x0;
4400 /// Reserved.
4401 pub const VAL_1: u32 = 0x1;
4402 /// Reserved.
4403 pub const VAL_2: u32 = 0x2;
4404 /// Activates maximum power saving behaviour for smart receiving mode.
4405 pub const VAL_3: u32 = 0x3;
4406}
4407
4408/// `SCCKDIV_BITF` value group
4409#[allow(non_upper_case_globals)]
4410pub mod scckdiv_bitf {
4411 /// Transceiver Clock divided by 256, (62.5kHz).
4412 pub const VAL_0: u32 = 0x0;
4413 /// Transceiver Clock divided by 128, (125kHz).
4414 pub const VAL_1: u32 = 0x1;
4415 /// Transceiver Clock divided by 64, (250kHz).
4416 pub const VAL_2: u32 = 0x2;
4417 /// Transceiver Clock divided by 32, (500kHz).
4418 pub const VAL_3: u32 = 0x3;
4419 /// Transceiver Clock divided by 16, (1MHz).
4420 pub const VAL_4: u32 = 0x4;
4421 /// Transceiver Clock divided by 8, (2MHz).
4422 pub const VAL_5: u32 = 0x5;
4423 /// Transceiver Clock divided by 4, (4MHz).
4424 pub const VAL_6: u32 = 0x6;
4425}
4426
4427/// `SCCS1_BITF` value group
4428#[allow(non_upper_case_globals)]
4429pub mod sccs1_bitf {
4430 /// Compare Unit 1 Relative Compare Source = Beacon Timestamp Register.
4431 pub const VAL_0: u32 = 0x0;
4432 /// Compare Unit 1 Relative Compare Source = Transmit Frame Timestamp Register.
4433 pub const VAL_1: u32 = 0x1;
4434 /// Compare Unit 1 Relative Compare Source = Received Frame Timestamp Register.
4435 pub const VAL_2: u32 = 0x2;
4436}
4437
4438/// `SCCS2_BITF` value group
4439#[allow(non_upper_case_globals)]
4440pub mod sccs2_bitf {
4441 /// Compare Unit 2 Relative Compare Source = Beacon Timestamp Register.
4442 pub const VAL_0: u32 = 0x0;
4443 /// Compare Unit 2 Relative Compare Source = Transmit Frame Timestamp Register.
4444 pub const VAL_1: u32 = 0x1;
4445 /// Compare Unit 2 Relative Compare Source = Received Frame Timestamp Register.
4446 pub const VAL_2: u32 = 0x2;
4447}
4448
4449/// `SCCS3_BITF` value group
4450#[allow(non_upper_case_globals)]
4451pub mod sccs3_bitf {
4452 /// Compare Unit 3 Relative Compare Source = Beacon Timestamp Register.
4453 pub const VAL_0: u32 = 0x0;
4454 /// Compare Unit 3 Relative Compare Source = Transmit Frame Timestamp Register.
4455 pub const VAL_1: u32 = 0x1;
4456 /// Compare Unit 3 Relative Compare Source = Received Frame Timestamp Register.
4457 pub const VAL_2: u32 = 0x2;
4458}
4459
4460/// `SFD_VALUE_BITF` value group
4461#[allow(non_upper_case_globals)]
4462pub mod sfd_value_bitf {
4463 /// IEEE 802.15.4 compliant value of the SFD.
4464 pub const IEEE_SFD: u32 = 0xA7;
4465}
4466
4467/// `SLOTTED_OPERATION_BITF` value group
4468#[allow(non_upper_case_globals)]
4469pub mod slotted_operation_bitf {
4470 /// The radio transceiver operates in unslotted mode. An acknowledgment frame is automatically sent if requested.
4471 pub const SLOTTED_OP_DIS: u32 = 0x0;
4472 /// The transmission of an acknowledgment frame has to be controlled by the microcontroller.
4473 pub const SLOTTED_OP_EN: u32 = 0x1;
4474}
4475
4476/// `SPI_CPHA_BITF` value group
4477#[allow(non_upper_case_globals)]
4478pub mod spi_cpha_bitf {
4479 /// Sample (Leading Edge), Setup (Trailing Edge).
4480 pub const VAL_0: u32 = 0x0;
4481 /// Setup (Leading Edge), Sample (Trailing Edge).
4482 pub const VAL_1: u32 = 0x1;
4483}
4484
4485/// `SPI_CPOL_BITF` value group
4486#[allow(non_upper_case_globals)]
4487pub mod spi_cpol_bitf {
4488 /// Rising (Leading Edge), Falling (Trailing Edge).
4489 pub const VAL_0: u32 = 0x0;
4490 /// Falling (Leading Egde), Rising (Trailing Edge).
4491 pub const VAL_1: u32 = 0x1;
4492}
4493
4494/// `TC0_CLK_SEL_3BIT_EXT` value group
4495#[allow(non_upper_case_globals)]
4496pub mod tc0_clk_sel_3bit_ext {
4497 /// No clock source (Timer/Counter0 stopped).
4498 pub const VAL_0x00: u32 = 0x0;
4499 /// clk_IO/1 (no prescaling).
4500 pub const VAL_0x01: u32 = 0x1;
4501 /// clk_IO/8 (from prescaler).
4502 pub const VAL_0x02: u32 = 0x2;
4503 /// clk_IO/64 (from prescaler).
4504 pub const VAL_0x03: u32 = 0x3;
4505 /// clk_IO/256 (from prescaler).
4506 pub const VAL_0x04: u32 = 0x4;
4507 /// clk_IO/1024 (from prescaler).
4508 pub const VAL_0x05: u32 = 0x5;
4509 /// External clock source on T0 pin, clock on falling edge.
4510 pub const VAL_0x06: u32 = 0x6;
4511 /// External clock source on T0 pin, clock on rising edge.
4512 pub const VAL_0x07: u32 = 0x7;
4513}
4514
4515/// `TC0_COM0A_BITF` value group
4516#[allow(non_upper_case_globals)]
4517pub mod tc0_com0a_bitf {
4518 /// Normal port operation, OC0A disconnected.
4519 pub const VAL_0: u32 = 0x0;
4520 /// Toggle OC0A on Compare Match.
4521 pub const VAL_1: u32 = 0x1;
4522 /// Clear OC0A on Compare Match.
4523 pub const VAL_2: u32 = 0x2;
4524 /// Set OC0A on Compare Match.
4525 pub const VAL_3: u32 = 0x3;
4526}
4527
4528/// `TC0_COM0B_BITF` value group
4529#[allow(non_upper_case_globals)]
4530pub mod tc0_com0b_bitf {
4531 /// Normal port operation, OC0B disconnected.
4532 pub const VAL_0: u32 = 0x0;
4533 /// Toggle OC0B on Compare Match.
4534 pub const VAL_1: u32 = 0x1;
4535 /// Clear OC0B on Compare Match.
4536 pub const VAL_2: u32 = 0x2;
4537 /// Set OC0B on Compare Match.
4538 pub const VAL_3: u32 = 0x3;
4539}
4540
4541/// `TC0_WGM_BITF` value group
4542#[allow(non_upper_case_globals)]
4543pub mod tc0_wgm_bitf {
4544 /// Normal mode of operation.
4545 pub const VAL_0x0: u32 = 0x0;
4546 /// PWM, phase correct, TOP=0xFF.
4547 pub const VAL_0x1: u32 = 0x1;
4548 /// CTC, TOP = OCRA.
4549 pub const VAL_0x2: u32 = 0x2;
4550 /// Fast PWM, TOP=0xFF.
4551 pub const VAL_0x3: u32 = 0x3;
4552 /// Reserved.
4553 pub const VAL_0x4: u32 = 0x4;
4554 /// PWM, Phase correct, TOP = OCRA.
4555 pub const VAL_0x5: u32 = 0x5;
4556 /// Reserved.
4557 pub const VAL_0x6: u32 = 0x6;
4558 /// Fast PWM, TOP=OCRA.
4559 pub const VAL_0x7: u32 = 0x7;
4560}
4561
4562/// `TC1_COMNX_BITF` value group
4563#[allow(non_upper_case_globals)]
4564pub mod tc1_comnx_bitf {
4565 /// Normal port operation, OCnA/OCnB/OCnC disconnected.
4566 pub const VAL_0: u32 = 0x0;
4567 /// Toggle OCnA/OCnB/OCnC on Compare Match.
4568 pub const VAL_1: u32 = 0x1;
4569 /// Clear OCnA/OCnB/OCnC on Compare Match (set output to low level).
4570 pub const VAL_2: u32 = 0x2;
4571 /// Set OCnA/OCnB/OCnC on Compare Match (set output to high level).
4572 pub const VAL_3: u32 = 0x3;
4573}
4574
4575/// `TC1_WGMX_BITF` value group
4576#[allow(non_upper_case_globals)]
4577pub mod tc1_wgmx_bitf {
4578 /// Normal mode of operation.
4579 pub const VAL_0x0: u32 = 0x0;
4580 /// PWM, phase correct, 8-bit.
4581 pub const VAL_0x1: u32 = 0x1;
4582 /// PWM, phase correct, 9-bit.
4583 pub const VAL_0x2: u32 = 0x2;
4584 /// PWM, phase correct, 10-bit.
4585 pub const VAL_0x3: u32 = 0x3;
4586 /// CTC, TOP = OCRnA.
4587 pub const VAL_0x4: u32 = 0x4;
4588 /// Fast PWM, 8-bit.
4589 pub const VAL_0x5: u32 = 0x5;
4590 /// Fast PWM, 9-bit.
4591 pub const VAL_0x6: u32 = 0x6;
4592 /// Fast PWM, 10-bit.
4593 pub const VAL_0x7: u32 = 0x7;
4594 /// PWM, Phase and frequency correct, TOP = ICRn.
4595 pub const VAL_0x8: u32 = 0x8;
4596 /// PWM, Phase and frequency correct, TOP = OCRnA.
4597 pub const VAL_0x9: u32 = 0x9;
4598 /// PWM, Phase correct, TOP = ICRn.
4599 pub const VAL_0xA: u32 = 0xA;
4600 /// PWM, Phase correct, TOP = OCRnA.
4601 pub const VAL_0xB: u32 = 0xB;
4602 /// CTC, TOP = OCRnA.
4603 pub const VAL_0xC: u32 = 0xC;
4604 /// Reserved.
4605 pub const VAL_0xD: u32 = 0xD;
4606 /// Fast PWM, TOP = ICRn.
4607 pub const VAL_0xE: u32 = 0xE;
4608 /// Fast PWM, TOP = OCRnA.
4609 pub const VAL_0xF: u32 = 0xF;
4610}
4611
4612/// `TC2_CLK_SEL_3BIT` value group
4613#[allow(non_upper_case_globals)]
4614pub mod tc2_clk_sel_3bit {
4615 /// No clock source (Timer/Counter2 stopped).
4616 pub const VAL_0x00: u32 = 0x0;
4617 /// clk_T2S/1 (no prescaling).
4618 pub const VAL_0x01: u32 = 0x1;
4619 /// clk_T2S/8 (from prescaler).
4620 pub const VAL_0x02: u32 = 0x2;
4621 /// clk_T2S/32 (from prescaler).
4622 pub const VAL_0x03: u32 = 0x3;
4623 /// clk_T2S/64 (from prescaler).
4624 pub const VAL_0x04: u32 = 0x4;
4625 /// clk_T2S/128 (from prescaler).
4626 pub const VAL_0x05: u32 = 0x5;
4627 /// clk_T2S/256 (from prescaler).
4628 pub const VAL_0x06: u32 = 0x6;
4629 /// clk_T2S/1024 (from prescaler).
4630 pub const VAL_0x07: u32 = 0x7;
4631}
4632
4633/// `TC2_COM2A_BITF` value group
4634#[allow(non_upper_case_globals)]
4635pub mod tc2_com2a_bitf {
4636 /// Normal port operation, OC2A disconnected.
4637 pub const VAL_0: u32 = 0x0;
4638 /// Toggle OC2A on Compare Match.
4639 pub const VAL_1: u32 = 0x1;
4640 /// Clear OC2A on Compare Match.
4641 pub const VAL_2: u32 = 0x2;
4642 /// Set OC2A on Compare Match.
4643 pub const VAL_3: u32 = 0x3;
4644}
4645
4646/// `TC2_COM2B_BITF` value group
4647#[allow(non_upper_case_globals)]
4648pub mod tc2_com2b_bitf {
4649 /// Normal port operation, OC2B disconnected.
4650 pub const VAL_0: u32 = 0x0;
4651 /// Toggle OC2B on Compare Match.
4652 pub const VAL_1: u32 = 0x1;
4653 /// Clear OC2B on Compare Match.
4654 pub const VAL_2: u32 = 0x2;
4655 /// Set OC2B on Compare Match.
4656 pub const VAL_3: u32 = 0x3;
4657}
4658
4659/// `TC4_COMNX_BITF` value group
4660#[allow(non_upper_case_globals)]
4661pub mod tc4_comnx_bitf {
4662 /// Normal operation.
4663 pub const VAL_0: u32 = 0x0;
4664 /// Reserved.
4665 pub const VAL_1: u32 = 0x1;
4666 /// Reserved.
4667 pub const VAL_2: u32 = 0x2;
4668 /// Reserved.
4669 pub const VAL_3: u32 = 0x3;
4670}
4671
4672/// `TRAC_STATUS_bitf` value group
4673#[allow(non_upper_case_globals)]
4674pub mod trac_status_bitf {
4675 /// SUCCESS (RX_AACK, TX_ARET).
4676 pub const TRAC_SUCCESS: u32 = 0x0;
4677 /// SUCCESS_DATA_PENDING (TX_ARET).
4678 pub const TRAC_SUCCESS_DATA_PENDING: u32 = 0x1;
4679 /// SUCCESS_WAIT_FOR_ACK (RX_AACK).
4680 pub const TRAC_SUCCESS_WAIT_FOR_ACK: u32 = 0x2;
4681 /// CHANNEL_ACCESS_FAILURE (TX_ARET).
4682 pub const TRAC_CHANNEL_ACCESS_FAILURE: u32 = 0x3;
4683 /// NO_ACK (TX_ARET).
4684 pub const TRAC_NO_ACK: u32 = 0x5;
4685 /// INVALID (RX_AACK, TX_ARET).
4686 pub const TRAC_INVALID: u32 = 0x7;
4687}
4688
4689/// `TRX_CMD_bitf` value group
4690#[allow(non_upper_case_globals)]
4691pub mod trx_cmd_bitf {
4692 /// NOP.
4693 pub const CMD_NOP: u32 = 0x0;
4694 /// TX_START.
4695 pub const CMD_TX_START: u32 = 0x2;
4696 /// FORCE_TRX_OFF.
4697 pub const CMD_FORCE_TRX_OFF: u32 = 0x3;
4698 /// FORCE_PLL_ON.
4699 pub const CMD_FORCE_PLL_ON: u32 = 0x4;
4700 /// RX_ON.
4701 pub const CMD_RX_ON: u32 = 0x6;
4702 /// TRX_OFF.
4703 pub const CMD_TRX_OFF: u32 = 0x8;
4704 /// PLL_ON (TX_ON).
4705 pub const CMD_PLL_ON: u32 = 0x9;
4706 /// RX_AACK_ON.
4707 pub const CMD_RX_AACK_ON: u32 = 0x16;
4708 /// TX_ARET_ON.
4709 pub const CMD_TX_ARET_ON: u32 = 0x19;
4710}
4711
4712/// `TRX_STATUS_bitf` value group
4713#[allow(non_upper_case_globals)]
4714pub mod trx_status_bitf {
4715 /// P_ON.
4716 pub const P_ON: u32 = 0x0;
4717 /// BUSY_RX.
4718 pub const BUSY_RX: u32 = 0x1;
4719 /// BUSY_TX.
4720 pub const BUSY_TX: u32 = 0x2;
4721 /// RX_ON.
4722 pub const RX_ON: u32 = 0x6;
4723 /// TRX_OFF.
4724 pub const TRX_OFF: u32 = 0x8;
4725 /// PLL_ON.
4726 pub const PLL_ON: u32 = 0x9;
4727 /// SLEEP.
4728 pub const SLEEP: u32 = 0xF;
4729 /// BUSY_RX_AACK.
4730 pub const BUSY_RX_AACK: u32 = 0x11;
4731 /// BUSY_TX_ARET.
4732 pub const BUSY_TX_ARET: u32 = 0x12;
4733 /// RX_AACK_ON.
4734 pub const RX_AACK_ON: u32 = 0x16;
4735 /// TX_ARET_ON.
4736 pub const TX_ARET_ON: u32 = 0x19;
4737 /// STATE_TRANSITION_IN_PROGRESS.
4738 pub const STATE_TRANSITION_IN_PROGRESS: u32 = 0x1F;
4739}
4740
4741/// `TST_CTRL_DIG_BITF` value group
4742#[allow(non_upper_case_globals)]
4743pub mod tst_ctrl_dig_bitf {
4744 /// NORMAL (no test is active).
4745 pub const VAL_0: u32 = 0x0;
4746 /// TST_CONT_TX (continuous transmit).
4747 pub const VAL_15: u32 = 0xF;
4748}
4749
4750/// `TST_STATUS_bitf` value group
4751#[allow(non_upper_case_globals)]
4752pub mod tst_status_bitf {
4753 /// Test mode is disabled.
4754 pub const TST_DISABLED: u32 = 0x0;
4755 /// Test mode is active.
4756 pub const TST_ENABLED: u32 = 0x1;
4757}
4758
4759/// `TWI_STATUS_BITF` value group
4760#[allow(non_upper_case_globals)]
4761pub mod twi_status_bitf {
4762 /// Bus error due to illegal START or STOP condition.
4763 pub const VAL_0x00: u32 = 0x0;
4764 /// A START condition has been transmitted.
4765 pub const VAL_0x08: u32 = 0x8;
4766 /// A repeated START condition has been transmitted.
4767 pub const VAL_0x10: u32 = 0x10;
4768 /// SLA+W has been transmitted; ACK has been received.
4769 pub const VAL_0x18: u32 = 0x18;
4770 /// SLA+W has been transmitted; NOT ACK has been received.
4771 pub const VAL_0x20: u32 = 0x20;
4772 /// Data byte has been transmitted; ACK has been received.
4773 pub const VAL_0x28: u32 = 0x28;
4774 /// Data byte has been transmitted; NOT ACK has been received.
4775 pub const VAL_0x30: u32 = 0x30;
4776 /// Arbitration lost in SLA+W or data bytes (Transmitter); Arbitration lost in SLA+R or NOT ACK bit (Receiver).
4777 pub const VAL_0x38: u32 = 0x38;
4778 /// SLA+R has been transmitted; ACK has been received.
4779 pub const VAL_0x40: u32 = 0x40;
4780 /// SLA+R has been transmitted; NOT ACK has been received.
4781 pub const VAL_0x48: u32 = 0x48;
4782 /// Data byte has been received; ACK has been returned.
4783 pub const VAL_0x50: u32 = 0x50;
4784 /// Data byte has been received; NOT ACK has been returned.
4785 pub const VAL_0x58: u32 = 0x58;
4786 /// Own SLA+W has been received; ACK has been returned.
4787 pub const VAL_0x60: u32 = 0x60;
4788 /// Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned.
4789 pub const VAL_0x68: u32 = 0x68;
4790 /// General call address has been received; ACK has been returned.
4791 pub const VAL_0x70: u32 = 0x70;
4792 /// Arbitration lost in SLA+R/W as Master; general call address has been received; ACK has been returned.
4793 pub const VAL_0x78: u32 = 0x78;
4794 /// Previously addressed with own SLA+W; data has been received; ACK has been returned.
4795 pub const VAL_0x80: u32 = 0x80;
4796 /// Previously addressed with own SLA+W; data has been received; NOT ACK has been returned.
4797 pub const VAL_0x88: u32 = 0x88;
4798 /// Previously addressed with general call; data has been received; ACK has been returned.
4799 pub const VAL_0x90: u32 = 0x90;
4800 /// Previously addressed with general call; data has been received; NOT ACK has been returned.
4801 pub const VAL_0x98: u32 = 0x98;
4802 /// A STOP condition or repeated START condition has been received while still addressed as Slave.
4803 pub const VAL_0xA0: u32 = 0xA0;
4804 /// Own SLA+R has been received; ACK has been returned.
4805 pub const VAL_0xA8: u32 = 0xA8;
4806 /// Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned.
4807 pub const VAL_0xB0: u32 = 0xB0;
4808 /// Data byte in TWDR has been transmitted; ACK has been received.
4809 pub const VAL_0xB8: u32 = 0xB8;
4810 /// Data byte in TWDR has been transmitted; NO ACK has been received.
4811 pub const VAL_0xC0: u32 = 0xC0;
4812 /// Last data byte in TWDR has been transmitted (TWEA = 0); ACK has been received.
4813 pub const VAL_0xC8: u32 = 0xC8;
4814 /// No relevant state information available; TWINT = 0.
4815 pub const VAL_0xF8: u32 = 0xF8;
4816}
4817
4818/// `TX_PWR_bitf` value group
4819#[allow(non_upper_case_globals)]
4820pub mod tx_pwr_bitf {
4821 /// 3.5 dBm.
4822 pub const VAL_0: u32 = 0x0;
4823 /// 3.3 dBm.
4824 pub const VAL_1: u32 = 0x1;
4825 /// 2.8 dBm.
4826 pub const VAL_2: u32 = 0x2;
4827 /// 2.3 dBm.
4828 pub const VAL_3: u32 = 0x3;
4829 /// 1.8 dBm.
4830 pub const VAL_4: u32 = 0x4;
4831 /// 1.2 dBm.
4832 pub const VAL_5: u32 = 0x5;
4833 /// 0.5 dBm.
4834 pub const VAL_6: u32 = 0x6;
4835 /// -0.5 dBm.
4836 pub const VAL_7: u32 = 0x7;
4837 /// -1.5 dBm.
4838 pub const VAL_8: u32 = 0x8;
4839 /// -2.5 dBm.
4840 pub const VAL_9: u32 = 0x9;
4841 /// -3.5 dBm.
4842 pub const VAL_10: u32 = 0xA;
4843 /// -4.5 dBm.
4844 pub const VAL_11: u32 = 0xB;
4845 /// -6.5 dBm.
4846 pub const VAL_12: u32 = 0xC;
4847 /// -8.5 dBm.
4848 pub const VAL_13: u32 = 0xD;
4849 /// -11.5 dBm.
4850 pub const VAL_14: u32 = 0xE;
4851 /// -16.5 dBm.
4852 pub const VAL_15: u32 = 0xF;
4853}
4854
4855/// `USART_CHAR_SIZE_BITF` value group
4856#[allow(non_upper_case_globals)]
4857pub mod usart_char_size_bitf {
4858 /// 5-bit.
4859 pub const VAL_0: u32 = 0x0;
4860 /// 6-bit.
4861 pub const VAL_1: u32 = 0x1;
4862 /// 7-bit.
4863 pub const VAL_2: u32 = 0x2;
4864 /// 8-bit.
4865 pub const VAL_3: u32 = 0x3;
4866 /// Reserved.
4867 pub const VAL_4: u32 = 0x4;
4868 /// Reserved.
4869 pub const VAL_5: u32 = 0x5;
4870 /// Reserved.
4871 pub const VAL_6: u32 = 0x6;
4872 /// 9-bit.
4873 pub const VAL_7: u32 = 0x7;
4874}
4875
4876/// `USART_CLK_POLARITY_BITF` value group
4877#[allow(non_upper_case_globals)]
4878pub mod usart_clk_polarity_bitf {
4879 /// Rising XCKn Edge (Transmitted Data Changed), Falling XCKn Edge (Received Data Sampled).
4880 pub const VAL_0: u32 = 0x0;
4881 /// Falling XCKn Edge (Transmitted Data Changed), Rising XCKn Edge (Received Data Sampled).
4882 pub const VAL_1: u32 = 0x1;
4883}
4884
4885/// `VERSION_NUM_2_BITF` value group
4886#[allow(non_upper_case_globals)]
4887pub mod version_num_2_bitf {
4888 /// Revision A.
4889 pub const REV_A: u32 = 0xC;
4890 /// Revision B.
4891 pub const REV_B: u32 = 0x1;
4892 /// Revision C.
4893 pub const REV_C: u32 = 0x3;
4894 /// Revision D.
4895 pub const REV_D: u32 = 0x4;
4896}
4897
4898/// `WDOG_TIMER_PRESCALE_4BITS` value group
4899#[allow(non_upper_case_globals)]
4900pub mod wdog_timer_prescale_4bits {
4901 /// Oscillator Cycles 2K.
4902 pub const VAL_0x00: u32 = 0x0;
4903 /// Oscillator Cycles 4K.
4904 pub const VAL_0x01: u32 = 0x1;
4905 /// Oscillator Cycles 8K.
4906 pub const VAL_0x02: u32 = 0x2;
4907 /// Oscillator Cycles 16K.
4908 pub const VAL_0x03: u32 = 0x3;
4909 /// Oscillator Cycles 32K.
4910 pub const VAL_0x04: u32 = 0x4;
4911 /// Oscillator Cycles 64K.
4912 pub const VAL_0x05: u32 = 0x5;
4913 /// Oscillator Cycles 128K.
4914 pub const VAL_0x06: u32 = 0x6;
4915 /// Oscillator Cycles 256K.
4916 pub const VAL_0x07: u32 = 0x7;
4917 /// Oscillator Cycles 512K.
4918 pub const VAL_0x08: u32 = 0x8;
4919 /// Oscillator Cycles 1024K.
4920 pub const VAL_0x09: u32 = 0x9;
4921}
4922
4923/// `XTAL_MODE_BITF` value group
4924#[allow(non_upper_case_globals)]
4925pub mod xtal_mode_bitf {
4926 /// Internal crystal oscillator disabled; use external reference frequency.
4927 pub const VAL_0x4: u32 = 0x4;
4928 /// Internal crystal oscillator enabled; amplitude regulation of oscillation enabled.
4929 pub const VAL_0xF: u32 = 0xF;
4930}
4931
4932/// `XTAL_TRIM_bitf` value group
4933#[allow(non_upper_case_globals)]
4934pub mod xtal_trim_bitf {
4935 /// 0.0 pF, trimming capacitors disconnected.
4936 pub const XTAL_TRIM_MIN: u32 = 0x0;
4937 /// 0.3 pF, trimming capacitor switched on.
4938 pub const VAL_0x1: u32 = 0x1;
4939 /// ...
4940 pub const VAL_0x2: u32 = 0x2;
4941 /// 4.5 pF, trimming capacitor switched on.
4942 pub const XTAL_TRIM_MAX: u32 = 0xF;
4943}
4944