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#[doc = "Reader of register UCSR2B"]
pub type R = crate::R<u8, super::UCSR2B>;
#[doc = "Writer for register UCSR2B"]
pub type W = crate::W<u8, super::UCSR2B>;
#[doc = "Register UCSR2B `reset()`'s with value 0"]
impl crate::ResetValue for super::UCSR2B {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0
    }
}
#[doc = "Reader of field `TXB82`"]
pub type TXB82_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `TXB82`"]
pub struct TXB82_W<'a> {
    w: &'a mut W,
}
impl<'a> TXB82_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01);
        self.w
    }
}
#[doc = "Reader of field `RXB82`"]
pub type RXB82_R = crate::R<bool, bool>;
#[doc = "Reader of field `UCSZ22`"]
pub type UCSZ22_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UCSZ22`"]
pub struct UCSZ22_W<'a> {
    w: &'a mut W,
}
impl<'a> UCSZ22_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u8) & 0x01) << 2);
        self.w
    }
}
#[doc = "Reader of field `TXEN2`"]
pub type TXEN2_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `TXEN2`"]
pub struct TXEN2_W<'a> {
    w: &'a mut W,
}
impl<'a> TXEN2_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u8) & 0x01) << 3);
        self.w
    }
}
#[doc = "Reader of field `RXEN2`"]
pub type RXEN2_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `RXEN2`"]
pub struct RXEN2_W<'a> {
    w: &'a mut W,
}
impl<'a> RXEN2_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u8) & 0x01) << 4);
        self.w
    }
}
#[doc = "Reader of field `UDRIE2`"]
pub type UDRIE2_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `UDRIE2`"]
pub struct UDRIE2_W<'a> {
    w: &'a mut W,
}
impl<'a> UDRIE2_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u8) & 0x01) << 5);
        self.w
    }
}
#[doc = "Reader of field `TXCIE2`"]
pub type TXCIE2_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `TXCIE2`"]
pub struct TXCIE2_W<'a> {
    w: &'a mut W,
}
impl<'a> TXCIE2_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u8) & 0x01) << 6);
        self.w
    }
}
#[doc = "Reader of field `RXCIE2`"]
pub type RXCIE2_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `RXCIE2`"]
pub struct RXCIE2_W<'a> {
    w: &'a mut W,
}
impl<'a> RXCIE2_W<'a> {
    #[doc = r"Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }
    #[doc = r"Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u8) & 0x01) << 7);
        self.w
    }
}
impl R {
    #[doc = "Bit 0 - Transmit Data Bit 8"]
    #[inline(always)]
    pub fn txb82(&self) -> TXB82_R {
        TXB82_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Receive Data Bit 8"]
    #[inline(always)]
    pub fn rxb82(&self) -> RXB82_R {
        RXB82_R::new(((self.bits >> 1) & 0x01) != 0)
    }
    #[doc = "Bit 2 - Character Size"]
    #[inline(always)]
    pub fn ucsz22(&self) -> UCSZ22_R {
        UCSZ22_R::new(((self.bits >> 2) & 0x01) != 0)
    }
    #[doc = "Bit 3 - Transmitter Enable"]
    #[inline(always)]
    pub fn txen2(&self) -> TXEN2_R {
        TXEN2_R::new(((self.bits >> 3) & 0x01) != 0)
    }
    #[doc = "Bit 4 - Receiver Enable"]
    #[inline(always)]
    pub fn rxen2(&self) -> RXEN2_R {
        RXEN2_R::new(((self.bits >> 4) & 0x01) != 0)
    }
    #[doc = "Bit 5 - USART Data register Empty Interrupt Enable"]
    #[inline(always)]
    pub fn udrie2(&self) -> UDRIE2_R {
        UDRIE2_R::new(((self.bits >> 5) & 0x01) != 0)
    }
    #[doc = "Bit 6 - TX Complete Interrupt Enable"]
    #[inline(always)]
    pub fn txcie2(&self) -> TXCIE2_R {
        TXCIE2_R::new(((self.bits >> 6) & 0x01) != 0)
    }
    #[doc = "Bit 7 - RX Complete Interrupt Enable"]
    #[inline(always)]
    pub fn rxcie2(&self) -> RXCIE2_R {
        RXCIE2_R::new(((self.bits >> 7) & 0x01) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Transmit Data Bit 8"]
    #[inline(always)]
    pub fn txb82(&mut self) -> TXB82_W {
        TXB82_W { w: self }
    }
    #[doc = "Bit 2 - Character Size"]
    #[inline(always)]
    pub fn ucsz22(&mut self) -> UCSZ22_W {
        UCSZ22_W { w: self }
    }
    #[doc = "Bit 3 - Transmitter Enable"]
    #[inline(always)]
    pub fn txen2(&mut self) -> TXEN2_W {
        TXEN2_W { w: self }
    }
    #[doc = "Bit 4 - Receiver Enable"]
    #[inline(always)]
    pub fn rxen2(&mut self) -> RXEN2_W {
        RXEN2_W { w: self }
    }
    #[doc = "Bit 5 - USART Data register Empty Interrupt Enable"]
    #[inline(always)]
    pub fn udrie2(&mut self) -> UDRIE2_W {
        UDRIE2_W { w: self }
    }
    #[doc = "Bit 6 - TX Complete Interrupt Enable"]
    #[inline(always)]
    pub fn txcie2(&mut self) -> TXCIE2_W {
        TXCIE2_W { w: self }
    }
    #[doc = "Bit 7 - RX Complete Interrupt Enable"]
    #[inline(always)]
    pub fn rxcie2(&mut self) -> RXCIE2_W {
        RXCIE2_W { w: self }
    }
}