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// AUTO-GENERATED by `cargo xtask cpu gen-param` from
// firmware/fpga/rtl/sources_1/new/headers/params.svh and the IP .xci files. DO NOT EDIT.
// Client-facing wire constants shared with the firmware.
pub const NUM_TRANSDUCERS: usize = 249;
pub const NUM_BANKS: usize = 2;
pub const EMISSION_MAX_INDICES: u32 = 1024;
pub const EMISSION_SLOT_WORDS: usize = 256;
pub const FOCUS_WORDS: usize = 4;
pub const NUM_FOCI_MAX: u8 = 8;
pub const ULTRASOUND_FREQ_HZ: u32 = 40000;
pub const REP_INFINITE: u16 = 0xFFFF;
pub const FUNC_DYNAMIC_FREQ_BIT: u16 = 1;
pub const FUNC_EMULATOR_BIT: u16 = 7;
pub const VERSION_NUM_MAJOR: u8 = 0x0;
pub const VERSION_NUM_MINOR: u8 = 0x6;
pub const VERSION_NUM_PATCH: u8 = 0x0;
pub const FPGA_STATE_BIT_THERMAL_ASSERT: u16 = 0;
pub const FPGA_STATE_THERMAL_ASSERT: u16 = 1 << FPGA_STATE_BIT_THERMAL_ASSERT;
pub const FPGA_STATE_BIT_MOD_BANK: u16 = 1;
pub const FPGA_STATE_MOD_BANK: u16 = 1 << FPGA_STATE_BIT_MOD_BANK;
pub const FPGA_STATE_BIT_PATTERN_BANK: u16 = 2;
pub const FPGA_STATE_PATTERN_BANK: u16 = 1 << FPGA_STATE_BIT_PATTERN_BANK;
pub const FPGA_STATE_BIT_PATTERN_MODE: u16 = 3;
pub const FPGA_STATE_PATTERN_MODE: u16 = 1 << FPGA_STATE_BIT_PATTERN_MODE;
pub const FPGA_STATE_BIT_PATTERN_STOPPED: u16 = 4;
pub const FPGA_STATE_PATTERN_STOPPED: u16 = 1 << FPGA_STATE_BIT_PATTERN_STOPPED;
pub const FPGA_STATE_BIT_MOD_STOPPED: u16 = 5;
pub const FPGA_STATE_MOD_STOPPED: u16 = 1 << FPGA_STATE_BIT_MOD_STOPPED;
pub const FPGA_STATE_BIT_TRANSITION_PENDING: u16 = 6;
pub const FPGA_STATE_TRANSITION_PENDING: u16 = 1 << FPGA_STATE_BIT_TRANSITION_PENDING;
pub const FPGA_STATE_BIT_READS_ENABLED: u16 = 7;
pub const FPGA_STATE_READS_ENABLED: u16 = 1 << FPGA_STATE_BIT_READS_ENABLED;
pub const TRANSITION_MODE_SYNC_IDX: u8 = 0x0;
pub const TRANSITION_MODE_SYS_TIME: u8 = 0x1;
pub const TRANSITION_MODE_GPIO: u8 = 0x2;
pub const TRANSITION_MODE_EXT: u8 = 0xF0;
pub const TRANSITION_MODE_IMMEDIATE: u8 = 0xFF;
pub const EMISSION_TYPE_FOCI: u8 = 0x0;
pub const EMISSION_TYPE_RAW: u8 = 0x1;
pub const SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE: u8 = 0;
pub const SILENCER_FLAG_FIXED_UPDATE_RATE_MODE: u8 = 1 << SILENCER_FLAG_BIT_FIXED_UPDATE_RATE_MODE;
pub const GPIO_O_TYPE_NONE: u8 = 0x0;
pub const GPIO_O_TYPE_BASE_SIG: u8 = 0x1;
pub const GPIO_O_TYPE_THERMO: u8 = 0x2;
pub const GPIO_O_TYPE_FORCE_FAN: u8 = 0x3;
pub const GPIO_O_TYPE_SYNC: u8 = 0x10;
pub const GPIO_O_TYPE_MOD_BANK: u8 = 0x20;
pub const GPIO_O_TYPE_MOD_IDX: u8 = 0x21;
pub const GPIO_O_TYPE_PATTERN_BANK: u8 = 0x50;
pub const GPIO_O_TYPE_PATTERN_IDX: u8 = 0x51;
pub const GPIO_O_TYPE_IS_STM_MODE: u8 = 0x52;
pub const GPIO_O_TYPE_SYS_TIME_EQ: u8 = 0x60;
pub const GPIO_O_TYPE_SYNC_DIFF: u8 = 0x70;
pub const GPIO_O_TYPE_PWM_OUT: u8 = 0xE0;
pub const GPIO_O_TYPE_DIRECT: u8 = 0xF0;
pub const MOD_BUFFER_SAMPLES: usize = 65536;
pub const PWE_TABLE_SIZE: usize = 256;
pub const FOCUS_TR_X_MAX: i32 = 6909;
pub const FOCUS_TR_Y_MAX: i32 = 5283;
pub const FPGA_CLK_FREQ_HZ: u32 = 20_480_000;