#[doc = "Register `US_IER` writer"]
pub struct W(crate::W<US_IER_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<US_IER_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<US_IER_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<US_IER_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RXRDY` writer - RXRDY Interrupt Enable"]
pub struct RXRDY_W<'a> {
w: &'a mut W,
}
impl<'a> RXRDY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Field `TXRDY` writer - TXRDY Interrupt Enable"]
pub struct TXRDY_W<'a> {
w: &'a mut W,
}
impl<'a> TXRDY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `RXBRK` writer - Receiver Break Interrupt Enable"]
pub struct RXBRK_W<'a> {
w: &'a mut W,
}
impl<'a> RXBRK_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"]
pub struct OVRE_W<'a> {
w: &'a mut W,
}
impl<'a> OVRE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `FRAME` writer - Framing Error Interrupt Enable"]
pub struct FRAME_W<'a> {
w: &'a mut W,
}
impl<'a> FRAME_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `PARE` writer - Parity Error Interrupt Enable"]
pub struct PARE_W<'a> {
w: &'a mut W,
}
impl<'a> PARE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
self.w
}
}
#[doc = "Field `TIMEOUT` writer - Time-out Interrupt Enable"]
pub struct TIMEOUT_W<'a> {
w: &'a mut W,
}
impl<'a> TIMEOUT_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
#[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Enable"]
pub struct TXEMPTY_W<'a> {
w: &'a mut W,
}
impl<'a> TXEMPTY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
#[doc = "Field `ITER` writer - Max number of Repetitions Reached Interrupt Enable"]
pub struct ITER_W<'a> {
w: &'a mut W,
}
impl<'a> ITER_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
#[doc = "Field `NACK` writer - Non Acknowledge Interrupt Enable"]
pub struct NACK_W<'a> {
w: &'a mut W,
}
impl<'a> NACK_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
self.w
}
}
#[doc = "Field `RIIC` writer - Ring Indicator Input Change Enable"]
pub struct RIIC_W<'a> {
w: &'a mut W,
}
impl<'a> RIIC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Field `DSRIC` writer - Data Set Ready Input Change Enable"]
pub struct DSRIC_W<'a> {
w: &'a mut W,
}
impl<'a> DSRIC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
self.w
}
}
#[doc = "Field `DCDIC` writer - Data Carrier Detect Input Change Interrupt Enable"]
pub struct DCDIC_W<'a> {
w: &'a mut W,
}
impl<'a> DCDIC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
self.w
}
}
#[doc = "Field `CTSIC` writer - Clear to Send Input Change Interrupt Enable"]
pub struct CTSIC_W<'a> {
w: &'a mut W,
}
impl<'a> CTSIC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
self.w
}
}
#[doc = "Field `MANE` writer - Manchester Error Interrupt Enable"]
pub struct MANE_W<'a> {
w: &'a mut W,
}
impl<'a> MANE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
self.w
}
}
impl W {
#[doc = "Bit 0 - RXRDY Interrupt Enable"]
#[inline(always)]
pub fn rxrdy(&mut self) -> RXRDY_W {
RXRDY_W { w: self }
}
#[doc = "Bit 1 - TXRDY Interrupt Enable"]
#[inline(always)]
pub fn txrdy(&mut self) -> TXRDY_W {
TXRDY_W { w: self }
}
#[doc = "Bit 2 - Receiver Break Interrupt Enable"]
#[inline(always)]
pub fn rxbrk(&mut self) -> RXBRK_W {
RXBRK_W { w: self }
}
#[doc = "Bit 5 - Overrun Error Interrupt Enable"]
#[inline(always)]
pub fn ovre(&mut self) -> OVRE_W {
OVRE_W { w: self }
}
#[doc = "Bit 6 - Framing Error Interrupt Enable"]
#[inline(always)]
pub fn frame(&mut self) -> FRAME_W {
FRAME_W { w: self }
}
#[doc = "Bit 7 - Parity Error Interrupt Enable"]
#[inline(always)]
pub fn pare(&mut self) -> PARE_W {
PARE_W { w: self }
}
#[doc = "Bit 8 - Time-out Interrupt Enable"]
#[inline(always)]
pub fn timeout(&mut self) -> TIMEOUT_W {
TIMEOUT_W { w: self }
}
#[doc = "Bit 9 - TXEMPTY Interrupt Enable"]
#[inline(always)]
pub fn txempty(&mut self) -> TXEMPTY_W {
TXEMPTY_W { w: self }
}
#[doc = "Bit 10 - Max number of Repetitions Reached Interrupt Enable"]
#[inline(always)]
pub fn iter(&mut self) -> ITER_W {
ITER_W { w: self }
}
#[doc = "Bit 13 - Non Acknowledge Interrupt Enable"]
#[inline(always)]
pub fn nack(&mut self) -> NACK_W {
NACK_W { w: self }
}
#[doc = "Bit 16 - Ring Indicator Input Change Enable"]
#[inline(always)]
pub fn riic(&mut self) -> RIIC_W {
RIIC_W { w: self }
}
#[doc = "Bit 17 - Data Set Ready Input Change Enable"]
#[inline(always)]
pub fn dsric(&mut self) -> DSRIC_W {
DSRIC_W { w: self }
}
#[doc = "Bit 18 - Data Carrier Detect Input Change Interrupt Enable"]
#[inline(always)]
pub fn dcdic(&mut self) -> DCDIC_W {
DCDIC_W { w: self }
}
#[doc = "Bit 19 - Clear to Send Input Change Interrupt Enable"]
#[inline(always)]
pub fn ctsic(&mut self) -> CTSIC_W {
CTSIC_W { w: self }
}
#[doc = "Bit 24 - Manchester Error Interrupt Enable"]
#[inline(always)]
pub fn mane(&mut self) -> MANE_W {
MANE_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ier](index.html) module"]
pub struct US_IER_SPEC;
impl crate::RegisterSpec for US_IER_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [us_ier::W](W) writer structure"]
impl crate::Writable for US_IER_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets US_IER to value 0"]
impl crate::Resettable for US_IER_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}