#[doc = "Register `USBHS_HSTIDR` writer"]
pub struct W(crate::W<USBHS_HSTIDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<USBHS_HSTIDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<USBHS_HSTIDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<USBHS_HSTIDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `DCONNIEC` writer - Device Connection Interrupt Disable"]
pub struct DCONNIEC_W<'a> {
w: &'a mut W,
}
impl<'a> DCONNIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Field `DDISCIEC` writer - Device Disconnection Interrupt Disable"]
pub struct DDISCIEC_W<'a> {
w: &'a mut W,
}
impl<'a> DDISCIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `RSTIEC` writer - USB Reset Sent Interrupt Disable"]
pub struct RSTIEC_W<'a> {
w: &'a mut W,
}
impl<'a> RSTIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `RSMEDIEC` writer - Downstream Resume Sent Interrupt Disable"]
pub struct RSMEDIEC_W<'a> {
w: &'a mut W,
}
impl<'a> RSMEDIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
self.w
}
}
#[doc = "Field `RXRSMIEC` writer - Upstream Resume Received Interrupt Disable"]
pub struct RXRSMIEC_W<'a> {
w: &'a mut W,
}
impl<'a> RXRSMIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
#[doc = "Field `HSOFIEC` writer - Host Start of Frame Interrupt Disable"]
pub struct HSOFIEC_W<'a> {
w: &'a mut W,
}
impl<'a> HSOFIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `HWUPIEC` writer - Host Wake-Up Interrupt Disable"]
pub struct HWUPIEC_W<'a> {
w: &'a mut W,
}
impl<'a> HWUPIEC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `PEP_0` writer - Pipe 0 Interrupt Disable"]
pub struct PEP_0_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
#[doc = "Field `PEP_1` writer - Pipe 1 Interrupt Disable"]
pub struct PEP_1_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
#[doc = "Field `PEP_2` writer - Pipe 2 Interrupt Disable"]
pub struct PEP_2_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_2_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
#[doc = "Field `PEP_3` writer - Pipe 3 Interrupt Disable"]
pub struct PEP_3_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_3_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
self.w
}
}
#[doc = "Field `PEP_4` writer - Pipe 4 Interrupt Disable"]
pub struct PEP_4_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_4_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
self.w
}
}
#[doc = "Field `PEP_5` writer - Pipe 5 Interrupt Disable"]
pub struct PEP_5_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_5_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
self.w
}
}
#[doc = "Field `PEP_6` writer - Pipe 6 Interrupt Disable"]
pub struct PEP_6_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_6_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
self.w
}
}
#[doc = "Field `PEP_7` writer - Pipe 7 Interrupt Disable"]
pub struct PEP_7_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_7_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
self.w
}
}
#[doc = "Field `PEP_8` writer - Pipe 8 Interrupt Disable"]
pub struct PEP_8_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_8_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Field `PEP_9` writer - Pipe 9 Interrupt Disable"]
pub struct PEP_9_W<'a> {
w: &'a mut W,
}
impl<'a> PEP_9_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
self.w
}
}
#[doc = "Field `DMA_0` writer - DMA Channel 0 Interrupt Disable"]
pub struct DMA_0_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | ((value as u32 & 0x01) << 25);
self.w
}
}
#[doc = "Field `DMA_1` writer - DMA Channel 1 Interrupt Disable"]
pub struct DMA_1_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | ((value as u32 & 0x01) << 26);
self.w
}
}
#[doc = "Field `DMA_2` writer - DMA Channel 2 Interrupt Disable"]
pub struct DMA_2_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_2_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 27)) | ((value as u32 & 0x01) << 27);
self.w
}
}
#[doc = "Field `DMA_3` writer - DMA Channel 3 Interrupt Disable"]
pub struct DMA_3_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_3_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 28)) | ((value as u32 & 0x01) << 28);
self.w
}
}
#[doc = "Field `DMA_4` writer - DMA Channel 4 Interrupt Disable"]
pub struct DMA_4_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_4_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 29)) | ((value as u32 & 0x01) << 29);
self.w
}
}
#[doc = "Field `DMA_5` writer - DMA Channel 5 Interrupt Disable"]
pub struct DMA_5_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_5_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
self.w
}
}
#[doc = "Field `DMA_6` writer - DMA Channel 6 Interrupt Disable"]
pub struct DMA_6_W<'a> {
w: &'a mut W,
}
impl<'a> DMA_6_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
self.w
}
}
impl W {
#[doc = "Bit 0 - Device Connection Interrupt Disable"]
#[inline(always)]
pub fn dconniec(&mut self) -> DCONNIEC_W {
DCONNIEC_W { w: self }
}
#[doc = "Bit 1 - Device Disconnection Interrupt Disable"]
#[inline(always)]
pub fn ddisciec(&mut self) -> DDISCIEC_W {
DDISCIEC_W { w: self }
}
#[doc = "Bit 2 - USB Reset Sent Interrupt Disable"]
#[inline(always)]
pub fn rstiec(&mut self) -> RSTIEC_W {
RSTIEC_W { w: self }
}
#[doc = "Bit 3 - Downstream Resume Sent Interrupt Disable"]
#[inline(always)]
pub fn rsmediec(&mut self) -> RSMEDIEC_W {
RSMEDIEC_W { w: self }
}
#[doc = "Bit 4 - Upstream Resume Received Interrupt Disable"]
#[inline(always)]
pub fn rxrsmiec(&mut self) -> RXRSMIEC_W {
RXRSMIEC_W { w: self }
}
#[doc = "Bit 5 - Host Start of Frame Interrupt Disable"]
#[inline(always)]
pub fn hsofiec(&mut self) -> HSOFIEC_W {
HSOFIEC_W { w: self }
}
#[doc = "Bit 6 - Host Wake-Up Interrupt Disable"]
#[inline(always)]
pub fn hwupiec(&mut self) -> HWUPIEC_W {
HWUPIEC_W { w: self }
}
#[doc = "Bit 8 - Pipe 0 Interrupt Disable"]
#[inline(always)]
pub fn pep_0(&mut self) -> PEP_0_W {
PEP_0_W { w: self }
}
#[doc = "Bit 9 - Pipe 1 Interrupt Disable"]
#[inline(always)]
pub fn pep_1(&mut self) -> PEP_1_W {
PEP_1_W { w: self }
}
#[doc = "Bit 10 - Pipe 2 Interrupt Disable"]
#[inline(always)]
pub fn pep_2(&mut self) -> PEP_2_W {
PEP_2_W { w: self }
}
#[doc = "Bit 11 - Pipe 3 Interrupt Disable"]
#[inline(always)]
pub fn pep_3(&mut self) -> PEP_3_W {
PEP_3_W { w: self }
}
#[doc = "Bit 12 - Pipe 4 Interrupt Disable"]
#[inline(always)]
pub fn pep_4(&mut self) -> PEP_4_W {
PEP_4_W { w: self }
}
#[doc = "Bit 13 - Pipe 5 Interrupt Disable"]
#[inline(always)]
pub fn pep_5(&mut self) -> PEP_5_W {
PEP_5_W { w: self }
}
#[doc = "Bit 14 - Pipe 6 Interrupt Disable"]
#[inline(always)]
pub fn pep_6(&mut self) -> PEP_6_W {
PEP_6_W { w: self }
}
#[doc = "Bit 15 - Pipe 7 Interrupt Disable"]
#[inline(always)]
pub fn pep_7(&mut self) -> PEP_7_W {
PEP_7_W { w: self }
}
#[doc = "Bit 16 - Pipe 8 Interrupt Disable"]
#[inline(always)]
pub fn pep_8(&mut self) -> PEP_8_W {
PEP_8_W { w: self }
}
#[doc = "Bit 17 - Pipe 9 Interrupt Disable"]
#[inline(always)]
pub fn pep_9(&mut self) -> PEP_9_W {
PEP_9_W { w: self }
}
#[doc = "Bit 25 - DMA Channel 0 Interrupt Disable"]
#[inline(always)]
pub fn dma_0(&mut self) -> DMA_0_W {
DMA_0_W { w: self }
}
#[doc = "Bit 26 - DMA Channel 1 Interrupt Disable"]
#[inline(always)]
pub fn dma_1(&mut self) -> DMA_1_W {
DMA_1_W { w: self }
}
#[doc = "Bit 27 - DMA Channel 2 Interrupt Disable"]
#[inline(always)]
pub fn dma_2(&mut self) -> DMA_2_W {
DMA_2_W { w: self }
}
#[doc = "Bit 28 - DMA Channel 3 Interrupt Disable"]
#[inline(always)]
pub fn dma_3(&mut self) -> DMA_3_W {
DMA_3_W { w: self }
}
#[doc = "Bit 29 - DMA Channel 4 Interrupt Disable"]
#[inline(always)]
pub fn dma_4(&mut self) -> DMA_4_W {
DMA_4_W { w: self }
}
#[doc = "Bit 30 - DMA Channel 5 Interrupt Disable"]
#[inline(always)]
pub fn dma_5(&mut self) -> DMA_5_W {
DMA_5_W { w: self }
}
#[doc = "Bit 31 - DMA Channel 6 Interrupt Disable"]
#[inline(always)]
pub fn dma_6(&mut self) -> DMA_6_W {
DMA_6_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Host Global Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usbhs_hstidr](index.html) module"]
pub struct USBHS_HSTIDR_SPEC;
impl crate::RegisterSpec for USBHS_HSTIDR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [usbhs_hstidr::W](W) writer structure"]
impl crate::Writable for USBHS_HSTIDR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets USBHS_HSTIDR to value 0"]
impl crate::Resettable for USBHS_HSTIDR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}