atsaml21j18bu/dmac/
active.rs

1#[doc = "Register `ACTIVE` reader"]
2pub struct R(crate::R<ACTIVE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ACTIVE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ACTIVE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ACTIVE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"]
17pub type LVLEX0_R = crate::BitReader<bool>;
18#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"]
19pub type LVLEX1_R = crate::BitReader<bool>;
20#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"]
21pub type LVLEX2_R = crate::BitReader<bool>;
22#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"]
23pub type LVLEX3_R = crate::BitReader<bool>;
24#[doc = "Field `ID` reader - Active Channel ID"]
25pub type ID_R = crate::FieldReader<u8, u8>;
26#[doc = "Field `ABUSY` reader - Active Channel Busy"]
27pub type ABUSY_R = crate::BitReader<bool>;
28#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"]
29pub type BTCNT_R = crate::FieldReader<u16, u16>;
30impl R {
31    #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"]
32    #[inline(always)]
33    pub fn lvlex0(&self) -> LVLEX0_R {
34        LVLEX0_R::new((self.bits & 1) != 0)
35    }
36    #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"]
37    #[inline(always)]
38    pub fn lvlex1(&self) -> LVLEX1_R {
39        LVLEX1_R::new(((self.bits >> 1) & 1) != 0)
40    }
41    #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"]
42    #[inline(always)]
43    pub fn lvlex2(&self) -> LVLEX2_R {
44        LVLEX2_R::new(((self.bits >> 2) & 1) != 0)
45    }
46    #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"]
47    #[inline(always)]
48    pub fn lvlex3(&self) -> LVLEX3_R {
49        LVLEX3_R::new(((self.bits >> 3) & 1) != 0)
50    }
51    #[doc = "Bits 8:12 - Active Channel ID"]
52    #[inline(always)]
53    pub fn id(&self) -> ID_R {
54        ID_R::new(((self.bits >> 8) & 0x1f) as u8)
55    }
56    #[doc = "Bit 15 - Active Channel Busy"]
57    #[inline(always)]
58    pub fn abusy(&self) -> ABUSY_R {
59        ABUSY_R::new(((self.bits >> 15) & 1) != 0)
60    }
61    #[doc = "Bits 16:31 - Active Channel Block Transfer Count"]
62    #[inline(always)]
63    pub fn btcnt(&self) -> BTCNT_R {
64        BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16)
65    }
66}
67#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"]
68pub struct ACTIVE_SPEC;
69impl crate::RegisterSpec for ACTIVE_SPEC {
70    type Ux = u32;
71}
72#[doc = "`read()` method returns [active::R](R) reader structure"]
73impl crate::Readable for ACTIVE_SPEC {
74    type Reader = R;
75}
76#[doc = "`reset()` method sets ACTIVE to value 0"]
77impl crate::Resettable for ACTIVE_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
atsaml21j18bu/dmac/active.rs

atsaml21j18bu/dmac/
active.rs
