atsaml21j18a/eic/
ctrla.rs

1#[doc = "Register `CTRLA` reader"]
2pub struct R(crate::R<CTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRLA` writer"]
17pub struct W(crate::W<CTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SWRST` writer - Software Reset"]
38pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
39#[doc = "Field `ENABLE` reader - Enable"]
40pub type ENABLE_R = crate::BitReader<bool>;
41#[doc = "Field `ENABLE` writer - Enable"]
42pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
43#[doc = "Field `CKSEL` reader - Clock Selection"]
44pub type CKSEL_R = crate::BitReader<bool>;
45#[doc = "Field `CKSEL` writer - Clock Selection"]
46pub type CKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
47impl R {
48    #[doc = "Bit 1 - Enable"]
49    #[inline(always)]
50    pub fn enable(&self) -> ENABLE_R {
51        ENABLE_R::new(((self.bits >> 1) & 1) != 0)
52    }
53    #[doc = "Bit 4 - Clock Selection"]
54    #[inline(always)]
55    pub fn cksel(&self) -> CKSEL_R {
56        CKSEL_R::new(((self.bits >> 4) & 1) != 0)
57    }
58}
59impl W {
60    #[doc = "Bit 0 - Software Reset"]
61    #[inline(always)]
62    #[must_use]
63    pub fn swrst(&mut self) -> SWRST_W<0> {
64        SWRST_W::new(self)
65    }
66    #[doc = "Bit 1 - Enable"]
67    #[inline(always)]
68    #[must_use]
69    pub fn enable(&mut self) -> ENABLE_W<1> {
70        ENABLE_W::new(self)
71    }
72    #[doc = "Bit 4 - Clock Selection"]
73    #[inline(always)]
74    #[must_use]
75    pub fn cksel(&mut self) -> CKSEL_W<4> {
76        CKSEL_W::new(self)
77    }
78    #[doc = "Writes raw bits to the register."]
79    #[inline(always)]
80    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
81        self.0.bits(bits);
82        self
83    }
84}
85#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"]
86pub struct CTRLA_SPEC;
87impl crate::RegisterSpec for CTRLA_SPEC {
88    type Ux = u8;
89}
90#[doc = "`read()` method returns [ctrla::R](R) reader structure"]
91impl crate::Readable for CTRLA_SPEC {
92    type Reader = R;
93}
94#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"]
95impl crate::Writable for CTRLA_SPEC {
96    type Writer = W;
97    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
98    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
99}
100#[doc = "`reset()` method sets CTRLA to value 0"]
101impl crate::Resettable for CTRLA_SPEC {
102    const RESET_VALUE: Self::Ux = 0;
103}
atsaml21j18a/eic/ctrla.rs

atsaml21j18a/eic/
ctrla.rs
