atsaml21j18a/supc/
intenclr.rs

1#[doc = "Register `INTENCLR` reader"]
2pub struct R(crate::R<INTENCLR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENCLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENCLR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENCLR` writer"]
17pub struct W(crate::W<INTENCLR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENCLR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENCLR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `BOD33RDY` reader - BOD33 Ready"]
38pub type BOD33RDY_R = crate::BitReader<bool>;
39#[doc = "Field `BOD33RDY` writer - BOD33 Ready"]
40pub type BOD33RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
41#[doc = "Field `BOD33DET` reader - BOD33 Detection"]
42pub type BOD33DET_R = crate::BitReader<bool>;
43#[doc = "Field `BOD33DET` writer - BOD33 Detection"]
44pub type BOD33DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
45#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"]
46pub type B33SRDY_R = crate::BitReader<bool>;
47#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"]
48pub type B33SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
49#[doc = "Field `BOD12RDY` reader - BOD12 Ready"]
50pub type BOD12RDY_R = crate::BitReader<bool>;
51#[doc = "Field `BOD12RDY` writer - BOD12 Ready"]
52pub type BOD12RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
53#[doc = "Field `BOD12DET` reader - BOD12 Detection"]
54pub type BOD12DET_R = crate::BitReader<bool>;
55#[doc = "Field `BOD12DET` writer - BOD12 Detection"]
56pub type BOD12DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
57#[doc = "Field `B12SRDY` reader - BOD12 Synchronization Ready"]
58pub type B12SRDY_R = crate::BitReader<bool>;
59#[doc = "Field `B12SRDY` writer - BOD12 Synchronization Ready"]
60pub type B12SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
61#[doc = "Field `VREGRDY` reader - Voltage Regulator Ready"]
62pub type VREGRDY_R = crate::BitReader<bool>;
63#[doc = "Field `VREGRDY` writer - Voltage Regulator Ready"]
64pub type VREGRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
65#[doc = "Field `APWSRDY` reader - Automatic Power Switch Ready"]
66pub type APWSRDY_R = crate::BitReader<bool>;
67#[doc = "Field `APWSRDY` writer - Automatic Power Switch Ready"]
68pub type APWSRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
69#[doc = "Field `VCORERDY` reader - VDDCORE Ready"]
70pub type VCORERDY_R = crate::BitReader<bool>;
71#[doc = "Field `VCORERDY` writer - VDDCORE Ready"]
72pub type VCORERDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>;
73impl R {
74    #[doc = "Bit 0 - BOD33 Ready"]
75    #[inline(always)]
76    pub fn bod33rdy(&self) -> BOD33RDY_R {
77        BOD33RDY_R::new((self.bits & 1) != 0)
78    }
79    #[doc = "Bit 1 - BOD33 Detection"]
80    #[inline(always)]
81    pub fn bod33det(&self) -> BOD33DET_R {
82        BOD33DET_R::new(((self.bits >> 1) & 1) != 0)
83    }
84    #[doc = "Bit 2 - BOD33 Synchronization Ready"]
85    #[inline(always)]
86    pub fn b33srdy(&self) -> B33SRDY_R {
87        B33SRDY_R::new(((self.bits >> 2) & 1) != 0)
88    }
89    #[doc = "Bit 3 - BOD12 Ready"]
90    #[inline(always)]
91    pub fn bod12rdy(&self) -> BOD12RDY_R {
92        BOD12RDY_R::new(((self.bits >> 3) & 1) != 0)
93    }
94    #[doc = "Bit 4 - BOD12 Detection"]
95    #[inline(always)]
96    pub fn bod12det(&self) -> BOD12DET_R {
97        BOD12DET_R::new(((self.bits >> 4) & 1) != 0)
98    }
99    #[doc = "Bit 5 - BOD12 Synchronization Ready"]
100    #[inline(always)]
101    pub fn b12srdy(&self) -> B12SRDY_R {
102        B12SRDY_R::new(((self.bits >> 5) & 1) != 0)
103    }
104    #[doc = "Bit 8 - Voltage Regulator Ready"]
105    #[inline(always)]
106    pub fn vregrdy(&self) -> VREGRDY_R {
107        VREGRDY_R::new(((self.bits >> 8) & 1) != 0)
108    }
109    #[doc = "Bit 9 - Automatic Power Switch Ready"]
110    #[inline(always)]
111    pub fn apwsrdy(&self) -> APWSRDY_R {
112        APWSRDY_R::new(((self.bits >> 9) & 1) != 0)
113    }
114    #[doc = "Bit 10 - VDDCORE Ready"]
115    #[inline(always)]
116    pub fn vcorerdy(&self) -> VCORERDY_R {
117        VCORERDY_R::new(((self.bits >> 10) & 1) != 0)
118    }
119}
120impl W {
121    #[doc = "Bit 0 - BOD33 Ready"]
122    #[inline(always)]
123    #[must_use]
124    pub fn bod33rdy(&mut self) -> BOD33RDY_W<0> {
125        BOD33RDY_W::new(self)
126    }
127    #[doc = "Bit 1 - BOD33 Detection"]
128    #[inline(always)]
129    #[must_use]
130    pub fn bod33det(&mut self) -> BOD33DET_W<1> {
131        BOD33DET_W::new(self)
132    }
133    #[doc = "Bit 2 - BOD33 Synchronization Ready"]
134    #[inline(always)]
135    #[must_use]
136    pub fn b33srdy(&mut self) -> B33SRDY_W<2> {
137        B33SRDY_W::new(self)
138    }
139    #[doc = "Bit 3 - BOD12 Ready"]
140    #[inline(always)]
141    #[must_use]
142    pub fn bod12rdy(&mut self) -> BOD12RDY_W<3> {
143        BOD12RDY_W::new(self)
144    }
145    #[doc = "Bit 4 - BOD12 Detection"]
146    #[inline(always)]
147    #[must_use]
148    pub fn bod12det(&mut self) -> BOD12DET_W<4> {
149        BOD12DET_W::new(self)
150    }
151    #[doc = "Bit 5 - BOD12 Synchronization Ready"]
152    #[inline(always)]
153    #[must_use]
154    pub fn b12srdy(&mut self) -> B12SRDY_W<5> {
155        B12SRDY_W::new(self)
156    }
157    #[doc = "Bit 8 - Voltage Regulator Ready"]
158    #[inline(always)]
159    #[must_use]
160    pub fn vregrdy(&mut self) -> VREGRDY_W<8> {
161        VREGRDY_W::new(self)
162    }
163    #[doc = "Bit 9 - Automatic Power Switch Ready"]
164    #[inline(always)]
165    #[must_use]
166    pub fn apwsrdy(&mut self) -> APWSRDY_W<9> {
167        APWSRDY_W::new(self)
168    }
169    #[doc = "Bit 10 - VDDCORE Ready"]
170    #[inline(always)]
171    #[must_use]
172    pub fn vcorerdy(&mut self) -> VCORERDY_W<10> {
173        VCORERDY_W::new(self)
174    }
175    #[doc = "Writes raw bits to the register."]
176    #[inline(always)]
177    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
178        self.0.bits(bits);
179        self
180    }
181}
182#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
183pub struct INTENCLR_SPEC;
184impl crate::RegisterSpec for INTENCLR_SPEC {
185    type Ux = u32;
186}
187#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
188impl crate::Readable for INTENCLR_SPEC {
189    type Reader = R;
190}
191#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
192impl crate::Writable for INTENCLR_SPEC {
193    type Writer = W;
194    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196}
197#[doc = "`reset()` method sets INTENCLR to value 0"]
198impl crate::Resettable for INTENCLR_SPEC {
199    const RESET_VALUE: Self::Ux = 0;
200}
atsaml21j18a/supc/intenclr.rs

atsaml21j18a/supc/
intenclr.rs
