atsaml21j17bu/tc0/count32/
intenclr.rs

1#[doc = "Register `INTENCLR` reader"]
2pub struct R(crate::R<INTENCLR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENCLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENCLR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENCLR` writer"]
17pub struct W(crate::W<INTENCLR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENCLR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENCLR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `OVF` reader - OVF Interrupt Disable"]
38pub type OVF_R = crate::BitReader<bool>;
39#[doc = "Field `OVF` writer - OVF Interrupt Disable"]
40pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
41#[doc = "Field `ERR` reader - ERR Interrupt Disable"]
42pub type ERR_R = crate::BitReader<bool>;
43#[doc = "Field `ERR` writer - ERR Interrupt Disable"]
44pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
45#[doc = "Field `MC0` reader - MC Interrupt Disable 0"]
46pub type MC0_R = crate::BitReader<bool>;
47#[doc = "Field `MC0` writer - MC Interrupt Disable 0"]
48pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
49#[doc = "Field `MC1` reader - MC Interrupt Disable 1"]
50pub type MC1_R = crate::BitReader<bool>;
51#[doc = "Field `MC1` writer - MC Interrupt Disable 1"]
52pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
53impl R {
54    #[doc = "Bit 0 - OVF Interrupt Disable"]
55    #[inline(always)]
56    pub fn ovf(&self) -> OVF_R {
57        OVF_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - ERR Interrupt Disable"]
60    #[inline(always)]
61    pub fn err(&self) -> ERR_R {
62        ERR_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 4 - MC Interrupt Disable 0"]
65    #[inline(always)]
66    pub fn mc0(&self) -> MC0_R {
67        MC0_R::new(((self.bits >> 4) & 1) != 0)
68    }
69    #[doc = "Bit 5 - MC Interrupt Disable 1"]
70    #[inline(always)]
71    pub fn mc1(&self) -> MC1_R {
72        MC1_R::new(((self.bits >> 5) & 1) != 0)
73    }
74}
75impl W {
76    #[doc = "Bit 0 - OVF Interrupt Disable"]
77    #[inline(always)]
78    #[must_use]
79    pub fn ovf(&mut self) -> OVF_W<0> {
80        OVF_W::new(self)
81    }
82    #[doc = "Bit 1 - ERR Interrupt Disable"]
83    #[inline(always)]
84    #[must_use]
85    pub fn err(&mut self) -> ERR_W<1> {
86        ERR_W::new(self)
87    }
88    #[doc = "Bit 4 - MC Interrupt Disable 0"]
89    #[inline(always)]
90    #[must_use]
91    pub fn mc0(&mut self) -> MC0_W<4> {
92        MC0_W::new(self)
93    }
94    #[doc = "Bit 5 - MC Interrupt Disable 1"]
95    #[inline(always)]
96    #[must_use]
97    pub fn mc1(&mut self) -> MC1_W<5> {
98        MC1_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
108pub struct INTENCLR_SPEC;
109impl crate::RegisterSpec for INTENCLR_SPEC {
110    type Ux = u8;
111}
112#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
113impl crate::Readable for INTENCLR_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
117impl crate::Writable for INTENCLR_SPEC {
118    type Writer = W;
119    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121}
122#[doc = "`reset()` method sets INTENCLR to value 0"]
123impl crate::Resettable for INTENCLR_SPEC {
124    const RESET_VALUE: Self::Ux = 0;
125}
atsaml21j17bu/tc0/count32/intenclr.rs

atsaml21j17bu/tc0/count32/
intenclr.rs
