atsaml21j17bu/dmac/
chintenclr.rs

1#[doc = "Register `CHINTENCLR` reader"]
2pub struct R(crate::R<CHINTENCLR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CHINTENCLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CHINTENCLR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CHINTENCLR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CHINTENCLR` writer"]
17pub struct W(crate::W<CHINTENCLR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CHINTENCLR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CHINTENCLR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CHINTENCLR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"]
38pub type TERR_R = crate::BitReader<bool>;
39#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"]
40pub type TERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENCLR_SPEC, bool, O>;
41#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"]
42pub type TCMPL_R = crate::BitReader<bool>;
43#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"]
44pub type TCMPL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENCLR_SPEC, bool, O>;
45#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"]
46pub type SUSP_R = crate::BitReader<bool>;
47#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"]
48pub type SUSP_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENCLR_SPEC, bool, O>;
49impl R {
50    #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"]
51    #[inline(always)]
52    pub fn terr(&self) -> TERR_R {
53        TERR_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"]
56    #[inline(always)]
57    pub fn tcmpl(&self) -> TCMPL_R {
58        TCMPL_R::new(((self.bits >> 1) & 1) != 0)
59    }
60    #[doc = "Bit 2 - Channel Suspend Interrupt Enable"]
61    #[inline(always)]
62    pub fn susp(&self) -> SUSP_R {
63        SUSP_R::new(((self.bits >> 2) & 1) != 0)
64    }
65}
66impl W {
67    #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"]
68    #[inline(always)]
69    #[must_use]
70    pub fn terr(&mut self) -> TERR_W<0> {
71        TERR_W::new(self)
72    }
73    #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"]
74    #[inline(always)]
75    #[must_use]
76    pub fn tcmpl(&mut self) -> TCMPL_W<1> {
77        TCMPL_W::new(self)
78    }
79    #[doc = "Bit 2 - Channel Suspend Interrupt Enable"]
80    #[inline(always)]
81    #[must_use]
82    pub fn susp(&mut self) -> SUSP_W<2> {
83        SUSP_W::new(self)
84    }
85    #[doc = "Writes raw bits to the register."]
86    #[inline(always)]
87    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
88        self.0.bits(bits);
89        self
90    }
91}
92#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"]
93pub struct CHINTENCLR_SPEC;
94impl crate::RegisterSpec for CHINTENCLR_SPEC {
95    type Ux = u8;
96}
97#[doc = "`read()` method returns [chintenclr::R](R) reader structure"]
98impl crate::Readable for CHINTENCLR_SPEC {
99    type Reader = R;
100}
101#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"]
102impl crate::Writable for CHINTENCLR_SPEC {
103    type Writer = W;
104    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106}
107#[doc = "`reset()` method sets CHINTENCLR to value 0"]
108impl crate::Resettable for CHINTENCLR_SPEC {
109    const RESET_VALUE: Self::Ux = 0;
110}
atsaml21j17bu/dmac/chintenclr.rs

atsaml21j17bu/dmac/
chintenclr.rs
