atsaml21e18b/sercom0/usart/
intenclr.rs

1#[doc = "Register `INTENCLR` reader"]
2pub struct R(crate::R<INTENCLR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENCLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENCLR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENCLR` writer"]
17pub struct W(crate::W<INTENCLR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENCLR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENCLR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"]
38pub type DRE_R = crate::BitReader<bool>;
39#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"]
40pub type DRE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
41#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"]
42pub type TXC_R = crate::BitReader<bool>;
43#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"]
44pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
45#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"]
46pub type RXC_R = crate::BitReader<bool>;
47#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"]
48pub type RXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
49#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"]
50pub type RXS_R = crate::BitReader<bool>;
51#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"]
52pub type RXS_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
53#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"]
54pub type CTSIC_R = crate::BitReader<bool>;
55#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"]
56pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
57#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"]
58pub type RXBRK_R = crate::BitReader<bool>;
59#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"]
60pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
61#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"]
62pub type ERROR_R = crate::BitReader<bool>;
63#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"]
64pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>;
65impl R {
66    #[doc = "Bit 0 - Data Register Empty Interrupt Disable"]
67    #[inline(always)]
68    pub fn dre(&self) -> DRE_R {
69        DRE_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - Transmit Complete Interrupt Disable"]
72    #[inline(always)]
73    pub fn txc(&self) -> TXC_R {
74        TXC_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - Receive Complete Interrupt Disable"]
77    #[inline(always)]
78    pub fn rxc(&self) -> RXC_R {
79        RXC_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - Receive Start Interrupt Disable"]
82    #[inline(always)]
83    pub fn rxs(&self) -> RXS_R {
84        RXS_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"]
87    #[inline(always)]
88    pub fn ctsic(&self) -> CTSIC_R {
89        CTSIC_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - Break Received Interrupt Disable"]
92    #[inline(always)]
93    pub fn rxbrk(&self) -> RXBRK_R {
94        RXBRK_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 7 - Combined Error Interrupt Disable"]
97    #[inline(always)]
98    pub fn error(&self) -> ERROR_R {
99        ERROR_R::new(((self.bits >> 7) & 1) != 0)
100    }
101}
102impl W {
103    #[doc = "Bit 0 - Data Register Empty Interrupt Disable"]
104    #[inline(always)]
105    #[must_use]
106    pub fn dre(&mut self) -> DRE_W<0> {
107        DRE_W::new(self)
108    }
109    #[doc = "Bit 1 - Transmit Complete Interrupt Disable"]
110    #[inline(always)]
111    #[must_use]
112    pub fn txc(&mut self) -> TXC_W<1> {
113        TXC_W::new(self)
114    }
115    #[doc = "Bit 2 - Receive Complete Interrupt Disable"]
116    #[inline(always)]
117    #[must_use]
118    pub fn rxc(&mut self) -> RXC_W<2> {
119        RXC_W::new(self)
120    }
121    #[doc = "Bit 3 - Receive Start Interrupt Disable"]
122    #[inline(always)]
123    #[must_use]
124    pub fn rxs(&mut self) -> RXS_W<3> {
125        RXS_W::new(self)
126    }
127    #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"]
128    #[inline(always)]
129    #[must_use]
130    pub fn ctsic(&mut self) -> CTSIC_W<4> {
131        CTSIC_W::new(self)
132    }
133    #[doc = "Bit 5 - Break Received Interrupt Disable"]
134    #[inline(always)]
135    #[must_use]
136    pub fn rxbrk(&mut self) -> RXBRK_W<5> {
137        RXBRK_W::new(self)
138    }
139    #[doc = "Bit 7 - Combined Error Interrupt Disable"]
140    #[inline(always)]
141    #[must_use]
142    pub fn error(&mut self) -> ERROR_W<7> {
143        ERROR_W::new(self)
144    }
145    #[doc = "Writes raw bits to the register."]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
148        self.0.bits(bits);
149        self
150    }
151}
152#[doc = "USART Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
153pub struct INTENCLR_SPEC;
154impl crate::RegisterSpec for INTENCLR_SPEC {
155    type Ux = u8;
156}
157#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
158impl crate::Readable for INTENCLR_SPEC {
159    type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
162impl crate::Writable for INTENCLR_SPEC {
163    type Writer = W;
164    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets INTENCLR to value 0"]
168impl crate::Resettable for INTENCLR_SPEC {
169    const RESET_VALUE: Self::Ux = 0;
170}
atsaml21e18b/sercom0/usart/intenclr.rs

atsaml21e18b/sercom0/usart/
intenclr.rs
