atsaml21e17b/sercom0/i2cs/
intenset.rs

1#[doc = "Register `INTENSET` reader"]
2pub struct R(crate::R<INTENSET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTENSET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTENSET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTENSET` writer"]
17pub struct W(crate::W<INTENSET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTENSET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTENSET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"]
38pub type PREC_R = crate::BitReader<bool>;
39#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"]
40pub type PREC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>;
41#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"]
42pub type AMATCH_R = crate::BitReader<bool>;
43#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"]
44pub type AMATCH_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>;
45#[doc = "Field `DRDY` reader - Data Interrupt Enable"]
46pub type DRDY_R = crate::BitReader<bool>;
47#[doc = "Field `DRDY` writer - Data Interrupt Enable"]
48pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>;
49#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"]
50pub type ERROR_R = crate::BitReader<bool>;
51#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"]
52pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>;
53impl R {
54    #[doc = "Bit 0 - Stop Received Interrupt Enable"]
55    #[inline(always)]
56    pub fn prec(&self) -> PREC_R {
57        PREC_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - Address Match Interrupt Enable"]
60    #[inline(always)]
61    pub fn amatch(&self) -> AMATCH_R {
62        AMATCH_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - Data Interrupt Enable"]
65    #[inline(always)]
66    pub fn drdy(&self) -> DRDY_R {
67        DRDY_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 7 - Combined Error Interrupt Enable"]
70    #[inline(always)]
71    pub fn error(&self) -> ERROR_R {
72        ERROR_R::new(((self.bits >> 7) & 1) != 0)
73    }
74}
75impl W {
76    #[doc = "Bit 0 - Stop Received Interrupt Enable"]
77    #[inline(always)]
78    #[must_use]
79    pub fn prec(&mut self) -> PREC_W<0> {
80        PREC_W::new(self)
81    }
82    #[doc = "Bit 1 - Address Match Interrupt Enable"]
83    #[inline(always)]
84    #[must_use]
85    pub fn amatch(&mut self) -> AMATCH_W<1> {
86        AMATCH_W::new(self)
87    }
88    #[doc = "Bit 2 - Data Interrupt Enable"]
89    #[inline(always)]
90    #[must_use]
91    pub fn drdy(&mut self) -> DRDY_W<2> {
92        DRDY_W::new(self)
93    }
94    #[doc = "Bit 7 - Combined Error Interrupt Enable"]
95    #[inline(always)]
96    #[must_use]
97    pub fn error(&mut self) -> ERROR_W<7> {
98        ERROR_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
108pub struct INTENSET_SPEC;
109impl crate::RegisterSpec for INTENSET_SPEC {
110    type Ux = u8;
111}
112#[doc = "`read()` method returns [intenset::R](R) reader structure"]
113impl crate::Readable for INTENSET_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
117impl crate::Writable for INTENSET_SPEC {
118    type Writer = W;
119    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
120    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121}
122#[doc = "`reset()` method sets INTENSET to value 0"]
123impl crate::Resettable for INTENSET_SPEC {
124    const RESET_VALUE: Self::Ux = 0;
125}
atsaml21e17b/sercom0/i2cs/intenset.rs

atsaml21e17b/sercom0/i2cs/
intenset.rs
