#[doc = "Register `GMAC_IERPQ[%s]` writer"]
pub struct W(crate::W<GMAC_IERPQ_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<GMAC_IERPQ_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<GMAC_IERPQ_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<GMAC_IERPQ_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RCOMP` writer - Receive Complete"]
pub struct RCOMP_W<'a> {
w: &'a mut W,
}
impl<'a> RCOMP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `RXUBR` writer - RX Used Bit Read"]
pub struct RXUBR_W<'a> {
w: &'a mut W,
}
impl<'a> RXUBR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `RLEX` writer - Retry Limit Exceeded or Late Collision"]
pub struct RLEX_W<'a> {
w: &'a mut W,
}
impl<'a> RLEX_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"]
pub struct TFC_W<'a> {
w: &'a mut W,
}
impl<'a> TFC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `TCOMP` writer - Transmit Complete"]
pub struct TCOMP_W<'a> {
w: &'a mut W,
}
impl<'a> TCOMP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
self.w
}
}
#[doc = "Field `ROVR` writer - Receive Overrun"]
pub struct ROVR_W<'a> {
w: &'a mut W,
}
impl<'a> ROVR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
#[doc = "Field `HRESP` writer - HRESP Not OK"]
pub struct HRESP_W<'a> {
w: &'a mut W,
}
impl<'a> HRESP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
self.w
}
}
impl W {
#[doc = "Bit 1 - Receive Complete"]
#[inline(always)]
pub fn rcomp(&mut self) -> RCOMP_W {
RCOMP_W { w: self }
}
#[doc = "Bit 2 - RX Used Bit Read"]
#[inline(always)]
pub fn rxubr(&mut self) -> RXUBR_W {
RXUBR_W { w: self }
}
#[doc = "Bit 5 - Retry Limit Exceeded or Late Collision"]
#[inline(always)]
pub fn rlex(&mut self) -> RLEX_W {
RLEX_W { w: self }
}
#[doc = "Bit 6 - Transmit Frame Corruption Due to AHB Error"]
#[inline(always)]
pub fn tfc(&mut self) -> TFC_W {
TFC_W { w: self }
}
#[doc = "Bit 7 - Transmit Complete"]
#[inline(always)]
pub fn tcomp(&mut self) -> TCOMP_W {
TCOMP_W { w: self }
}
#[doc = "Bit 10 - Receive Overrun"]
#[inline(always)]
pub fn rovr(&mut self) -> ROVR_W {
ROVR_W { w: self }
}
#[doc = "Bit 11 - HRESP Not OK"]
#[inline(always)]
pub fn hresp(&mut self) -> HRESP_W {
HRESP_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Enable Register Priority Queue (1..5)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gmac_ierpq](index.html) module"]
pub struct GMAC_IERPQ_SPEC;
impl crate::RegisterSpec for GMAC_IERPQ_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [gmac_ierpq::W](W) writer structure"]
impl crate::Writable for GMAC_IERPQ_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets GMAC_IERPQ[%s]
to value 0"]
impl crate::Resettable for GMAC_IERPQ_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}