#[doc = "Register `TWIHS_IDR` writer"]
pub struct W(crate::W<TWIHS_IDR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<TWIHS_IDR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<TWIHS_IDR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<TWIHS_IDR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `TXCOMP` writer - Transmission Completed Interrupt Disable"]
pub struct TXCOMP_W<'a> {
w: &'a mut W,
}
impl<'a> TXCOMP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Field `RXRDY` writer - Receive Holding Register Ready Interrupt Disable"]
pub struct RXRDY_W<'a> {
w: &'a mut W,
}
impl<'a> RXRDY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `TXRDY` writer - Transmit Holding Register Ready Interrupt Disable"]
pub struct TXRDY_W<'a> {
w: &'a mut W,
}
impl<'a> TXRDY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
self.w
}
}
#[doc = "Field `SVACC` writer - Slave Access Interrupt Disable"]
pub struct SVACC_W<'a> {
w: &'a mut W,
}
impl<'a> SVACC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
#[doc = "Field `GACC` writer - General Call Access Interrupt Disable"]
pub struct GACC_W<'a> {
w: &'a mut W,
}
impl<'a> GACC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `OVRE` writer - Overrun Error Interrupt Disable"]
pub struct OVRE_W<'a> {
w: &'a mut W,
}
impl<'a> OVRE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `UNRE` writer - Underrun Error Interrupt Disable"]
pub struct UNRE_W<'a> {
w: &'a mut W,
}
impl<'a> UNRE_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
self.w
}
}
#[doc = "Field `NACK` writer - Not Acknowledge Interrupt Disable"]
pub struct NACK_W<'a> {
w: &'a mut W,
}
impl<'a> NACK_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
#[doc = "Field `ARBLST` writer - Arbitration Lost Interrupt Disable"]
pub struct ARBLST_W<'a> {
w: &'a mut W,
}
impl<'a> ARBLST_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
#[doc = "Field `SCL_WS` writer - Clock Wait State Interrupt Disable"]
pub struct SCL_WS_W<'a> {
w: &'a mut W,
}
impl<'a> SCL_WS_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
#[doc = "Field `EOSACC` writer - End Of Slave Access Interrupt Disable"]
pub struct EOSACC_W<'a> {
w: &'a mut W,
}
impl<'a> EOSACC_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
self.w
}
}
#[doc = "Field `MCACK` writer - Master Code Acknowledge Interrupt Disable"]
pub struct MCACK_W<'a> {
w: &'a mut W,
}
impl<'a> MCACK_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Field `TOUT` writer - Timeout Error Interrupt Disable"]
pub struct TOUT_W<'a> {
w: &'a mut W,
}
impl<'a> TOUT_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
self.w
}
}
#[doc = "Field `PECERR` writer - PEC Error Interrupt Disable"]
pub struct PECERR_W<'a> {
w: &'a mut W,
}
impl<'a> PECERR_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
self.w
}
}
#[doc = "Field `SMBDAM` writer - SMBus Default Address Match Interrupt Disable"]
pub struct SMBDAM_W<'a> {
w: &'a mut W,
}
impl<'a> SMBDAM_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
self.w
}
}
#[doc = "Field `SMBHHM` writer - SMBus Host Header Address Match Interrupt Disable"]
pub struct SMBHHM_W<'a> {
w: &'a mut W,
}
impl<'a> SMBHHM_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
self.w
}
}
impl W {
#[doc = "Bit 0 - Transmission Completed Interrupt Disable"]
#[inline(always)]
pub fn txcomp(&mut self) -> TXCOMP_W {
TXCOMP_W { w: self }
}
#[doc = "Bit 1 - Receive Holding Register Ready Interrupt Disable"]
#[inline(always)]
pub fn rxrdy(&mut self) -> RXRDY_W {
RXRDY_W { w: self }
}
#[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Disable"]
#[inline(always)]
pub fn txrdy(&mut self) -> TXRDY_W {
TXRDY_W { w: self }
}
#[doc = "Bit 4 - Slave Access Interrupt Disable"]
#[inline(always)]
pub fn svacc(&mut self) -> SVACC_W {
SVACC_W { w: self }
}
#[doc = "Bit 5 - General Call Access Interrupt Disable"]
#[inline(always)]
pub fn gacc(&mut self) -> GACC_W {
GACC_W { w: self }
}
#[doc = "Bit 6 - Overrun Error Interrupt Disable"]
#[inline(always)]
pub fn ovre(&mut self) -> OVRE_W {
OVRE_W { w: self }
}
#[doc = "Bit 7 - Underrun Error Interrupt Disable"]
#[inline(always)]
pub fn unre(&mut self) -> UNRE_W {
UNRE_W { w: self }
}
#[doc = "Bit 8 - Not Acknowledge Interrupt Disable"]
#[inline(always)]
pub fn nack(&mut self) -> NACK_W {
NACK_W { w: self }
}
#[doc = "Bit 9 - Arbitration Lost Interrupt Disable"]
#[inline(always)]
pub fn arblst(&mut self) -> ARBLST_W {
ARBLST_W { w: self }
}
#[doc = "Bit 10 - Clock Wait State Interrupt Disable"]
#[inline(always)]
pub fn scl_ws(&mut self) -> SCL_WS_W {
SCL_WS_W { w: self }
}
#[doc = "Bit 11 - End Of Slave Access Interrupt Disable"]
#[inline(always)]
pub fn eosacc(&mut self) -> EOSACC_W {
EOSACC_W { w: self }
}
#[doc = "Bit 16 - Master Code Acknowledge Interrupt Disable"]
#[inline(always)]
pub fn mcack(&mut self) -> MCACK_W {
MCACK_W { w: self }
}
#[doc = "Bit 18 - Timeout Error Interrupt Disable"]
#[inline(always)]
pub fn tout(&mut self) -> TOUT_W {
TOUT_W { w: self }
}
#[doc = "Bit 19 - PEC Error Interrupt Disable"]
#[inline(always)]
pub fn pecerr(&mut self) -> PECERR_W {
PECERR_W { w: self }
}
#[doc = "Bit 20 - SMBus Default Address Match Interrupt Disable"]
#[inline(always)]
pub fn smbdam(&mut self) -> SMBDAM_W {
SMBDAM_W { w: self }
}
#[doc = "Bit 21 - SMBus Host Header Address Match Interrupt Disable"]
#[inline(always)]
pub fn smbhhm(&mut self) -> SMBHHM_W {
SMBHHM_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [twihs_idr](index.html) module"]
pub struct TWIHS_IDR_SPEC;
impl crate::RegisterSpec for TWIHS_IDR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [twihs_idr::W](W) writer structure"]
impl crate::Writable for TWIHS_IDR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets TWIHS_IDR to value 0"]
impl crate::Resettable for TWIHS_IDR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}