atsame70q19/qspi/
qspi_idr.rs

1#[doc = "Register `QSPI_IDR` writer"]
2pub struct W(crate::W<QSPI_IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<QSPI_IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<QSPI_IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<QSPI_IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Disable"]
23pub struct RDRF_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> RDRF_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `TDRE` writer - Transmit Data Register Empty Interrupt Disable"]
45pub struct TDRE_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> TDRE_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
63        self.w
64    }
65}
66#[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Disable"]
67pub struct TXEMPTY_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> TXEMPTY_W<'a> {
71    #[doc = r"Sets the field bit"]
72    #[inline(always)]
73    pub fn set_bit(self) -> &'a mut W {
74        self.bit(true)
75    }
76    #[doc = r"Clears the field bit"]
77    #[inline(always)]
78    pub fn clear_bit(self) -> &'a mut W {
79        self.bit(false)
80    }
81    #[doc = r"Writes raw bits to the field"]
82    #[inline(always)]
83    pub fn bit(self, value: bool) -> &'a mut W {
84        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
85        self.w
86    }
87}
88#[doc = "Field `OVRES` writer - Overrun Error Interrupt Disable"]
89pub struct OVRES_W<'a> {
90    w: &'a mut W,
91}
92impl<'a> OVRES_W<'a> {
93    #[doc = r"Sets the field bit"]
94    #[inline(always)]
95    pub fn set_bit(self) -> &'a mut W {
96        self.bit(true)
97    }
98    #[doc = r"Clears the field bit"]
99    #[inline(always)]
100    pub fn clear_bit(self) -> &'a mut W {
101        self.bit(false)
102    }
103    #[doc = r"Writes raw bits to the field"]
104    #[inline(always)]
105    pub fn bit(self, value: bool) -> &'a mut W {
106        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
107        self.w
108    }
109}
110#[doc = "Field `CSR` writer - Chip Select Rise Interrupt Disable"]
111pub struct CSR_W<'a> {
112    w: &'a mut W,
113}
114impl<'a> CSR_W<'a> {
115    #[doc = r"Sets the field bit"]
116    #[inline(always)]
117    pub fn set_bit(self) -> &'a mut W {
118        self.bit(true)
119    }
120    #[doc = r"Clears the field bit"]
121    #[inline(always)]
122    pub fn clear_bit(self) -> &'a mut W {
123        self.bit(false)
124    }
125    #[doc = r"Writes raw bits to the field"]
126    #[inline(always)]
127    pub fn bit(self, value: bool) -> &'a mut W {
128        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
129        self.w
130    }
131}
132#[doc = "Field `CSS` writer - Chip Select Status Interrupt Disable"]
133pub struct CSS_W<'a> {
134    w: &'a mut W,
135}
136impl<'a> CSS_W<'a> {
137    #[doc = r"Sets the field bit"]
138    #[inline(always)]
139    pub fn set_bit(self) -> &'a mut W {
140        self.bit(true)
141    }
142    #[doc = r"Clears the field bit"]
143    #[inline(always)]
144    pub fn clear_bit(self) -> &'a mut W {
145        self.bit(false)
146    }
147    #[doc = r"Writes raw bits to the field"]
148    #[inline(always)]
149    pub fn bit(self, value: bool) -> &'a mut W {
150        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
151        self.w
152    }
153}
154#[doc = "Field `INSTRE` writer - Instruction End Interrupt Disable"]
155pub struct INSTRE_W<'a> {
156    w: &'a mut W,
157}
158impl<'a> INSTRE_W<'a> {
159    #[doc = r"Sets the field bit"]
160    #[inline(always)]
161    pub fn set_bit(self) -> &'a mut W {
162        self.bit(true)
163    }
164    #[doc = r"Clears the field bit"]
165    #[inline(always)]
166    pub fn clear_bit(self) -> &'a mut W {
167        self.bit(false)
168    }
169    #[doc = r"Writes raw bits to the field"]
170    #[inline(always)]
171    pub fn bit(self, value: bool) -> &'a mut W {
172        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
173        self.w
174    }
175}
176impl W {
177    #[doc = "Bit 0 - Receive Data Register Full Interrupt Disable"]
178    #[inline(always)]
179    pub fn rdrf(&mut self) -> RDRF_W {
180        RDRF_W { w: self }
181    }
182    #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Disable"]
183    #[inline(always)]
184    pub fn tdre(&mut self) -> TDRE_W {
185        TDRE_W { w: self }
186    }
187    #[doc = "Bit 2 - Transmission Registers Empty Disable"]
188    #[inline(always)]
189    pub fn txempty(&mut self) -> TXEMPTY_W {
190        TXEMPTY_W { w: self }
191    }
192    #[doc = "Bit 3 - Overrun Error Interrupt Disable"]
193    #[inline(always)]
194    pub fn ovres(&mut self) -> OVRES_W {
195        OVRES_W { w: self }
196    }
197    #[doc = "Bit 8 - Chip Select Rise Interrupt Disable"]
198    #[inline(always)]
199    pub fn csr(&mut self) -> CSR_W {
200        CSR_W { w: self }
201    }
202    #[doc = "Bit 9 - Chip Select Status Interrupt Disable"]
203    #[inline(always)]
204    pub fn css(&mut self) -> CSS_W {
205        CSS_W { w: self }
206    }
207    #[doc = "Bit 10 - Instruction End Interrupt Disable"]
208    #[inline(always)]
209    pub fn instre(&mut self) -> INSTRE_W {
210        INSTRE_W { w: self }
211    }
212    #[doc = "Writes raw bits to the register."]
213    #[inline(always)]
214    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
215        self.0.bits(bits);
216        self
217    }
218}
219#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qspi_idr](index.html) module"]
220pub struct QSPI_IDR_SPEC;
221impl crate::RegisterSpec for QSPI_IDR_SPEC {
222    type Ux = u32;
223}
224#[doc = "`write(|w| ..)` method takes [qspi_idr::W](W) writer structure"]
225impl crate::Writable for QSPI_IDR_SPEC {
226    type Writer = W;
227}
228#[doc = "`reset()` method sets QSPI_IDR to value 0"]
229impl crate::Resettable for QSPI_IDR_SPEC {
230    #[inline(always)]
231    fn reset_value() -> Self::Ux {
232        0
233    }
234}
atsame70q19/qspi/qspi_idr.rs

atsame70q19/qspi/
qspi_idr.rs
