#[doc = "Reader of register DCFGR"]
pub type R = crate::R<u32, super::DCFGR>;
#[doc = "Writer for register DCFGR"]
pub type W = crate::W<u32, super::DCFGR>;
#[doc = "Register DCFGR `reset()`'s with value 0x0002_0704"]
impl crate::ResetValue for super::DCFGR {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0x0002_0704
}
}
#[doc = "Reader of field `FBLDO`"]
pub type FBLDO_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `FBLDO`"]
pub struct FBLDO_W<'a> {
w: &'a mut W,
}
impl<'a> FBLDO_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
self.w
}
}
#[doc = "Reader of field `ESMA`"]
pub type ESMA_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `ESMA`"]
pub struct ESMA_W<'a> {
w: &'a mut W,
}
impl<'a> ESMA_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
self.w
}
}
#[doc = "Reader of field `ESPA`"]
pub type ESPA_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `ESPA`"]
pub struct ESPA_W<'a> {
w: &'a mut W,
}
impl<'a> ESPA_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "Reader of field `RXBMS`"]
pub type RXBMS_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `RXBMS`"]
pub struct RXBMS_W<'a> {
w: &'a mut W,
}
impl<'a> RXBMS_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 8)) | (((value as u32) & 0x03) << 8);
self.w
}
}
#[doc = "Reader of field `TXPBMS`"]
pub type TXPBMS_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `TXPBMS`"]
pub struct TXPBMS_W<'a> {
w: &'a mut W,
}
impl<'a> TXPBMS_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
self.w
}
}
#[doc = "Reader of field `TXCOEN`"]
pub type TXCOEN_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `TXCOEN`"]
pub struct TXCOEN_W<'a> {
w: &'a mut W,
}
impl<'a> TXCOEN_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
self.w
}
}
#[doc = "Reader of field `DRBS`"]
pub type DRBS_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `DRBS`"]
pub struct DRBS_W<'a> {
w: &'a mut W,
}
impl<'a> DRBS_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
self.w
}
}
#[doc = "Reader of field `DDRP`"]
pub type DDRP_R = crate::R<bool, bool>;
#[doc = "Write proxy for field `DDRP`"]
pub struct DDRP_W<'a> {
w: &'a mut W,
}
impl<'a> DDRP_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
self.w
}
}
impl R {
#[doc = "Bits 0:4 - Fixed Burst Length for DMA Data Operations:"]
#[inline(always)]
pub fn fbldo(&self) -> FBLDO_R {
FBLDO_R::new((self.bits & 0x1f) as u8)
}
#[doc = "Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses"]
#[inline(always)]
pub fn esma(&self) -> ESMA_R {
ESMA_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - Endian Swap Mode Enable for Packet Data Accesses"]
#[inline(always)]
pub fn espa(&self) -> ESPA_R {
ESPA_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bits 8:9 - Receiver Packet Buffer Memory Size Select"]
#[inline(always)]
pub fn rxbms(&self) -> RXBMS_R {
RXBMS_R::new(((self.bits >> 8) & 0x03) as u8)
}
#[doc = "Bit 10 - Transmitter Packet Buffer Memory Size Select"]
#[inline(always)]
pub fn txpbms(&self) -> TXPBMS_R {
TXPBMS_R::new(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bit 11 - Transmitter Checksum Generation Offload Enable"]
#[inline(always)]
pub fn txcoen(&self) -> TXCOEN_R {
TXCOEN_R::new(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bits 16:23 - DMA Receive Buffer Size"]
#[inline(always)]
pub fn drbs(&self) -> DRBS_R {
DRBS_R::new(((self.bits >> 16) & 0xff) as u8)
}
#[doc = "Bit 24 - DMA Discard Receive Packets"]
#[inline(always)]
pub fn ddrp(&self) -> DDRP_R {
DDRP_R::new(((self.bits >> 24) & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 0:4 - Fixed Burst Length for DMA Data Operations:"]
#[inline(always)]
pub fn fbldo(&mut self) -> FBLDO_W {
FBLDO_W { w: self }
}
#[doc = "Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses"]
#[inline(always)]
pub fn esma(&mut self) -> ESMA_W {
ESMA_W { w: self }
}
#[doc = "Bit 7 - Endian Swap Mode Enable for Packet Data Accesses"]
#[inline(always)]
pub fn espa(&mut self) -> ESPA_W {
ESPA_W { w: self }
}
#[doc = "Bits 8:9 - Receiver Packet Buffer Memory Size Select"]
#[inline(always)]
pub fn rxbms(&mut self) -> RXBMS_W {
RXBMS_W { w: self }
}
#[doc = "Bit 10 - Transmitter Packet Buffer Memory Size Select"]
#[inline(always)]
pub fn txpbms(&mut self) -> TXPBMS_W {
TXPBMS_W { w: self }
}
#[doc = "Bit 11 - Transmitter Checksum Generation Offload Enable"]
#[inline(always)]
pub fn txcoen(&mut self) -> TXCOEN_W {
TXCOEN_W { w: self }
}
#[doc = "Bits 16:23 - DMA Receive Buffer Size"]
#[inline(always)]
pub fn drbs(&mut self) -> DRBS_W {
DRBS_W { w: self }
}
#[doc = "Bit 24 - DMA Discard Receive Packets"]
#[inline(always)]
pub fn ddrp(&mut self) -> DDRP_W {
DDRP_W { w: self }
}
}