atsame51g18a_pac/oscctrl/
dfllsync.rs

1#[doc = "Register `DFLLSYNC` reader"]
2pub struct R(crate::R<DFLLSYNC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DFLLSYNC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DFLLSYNC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DFLLSYNC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DFLLSYNC` writer"]
17pub struct W(crate::W<DFLLSYNC_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DFLLSYNC_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DFLLSYNC_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DFLLSYNC_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"]
38pub struct ENABLE_R(crate::FieldReader<bool, bool>);
39impl ENABLE_R {
40    pub(crate) fn new(bits: bool) -> Self {
41        ENABLE_R(crate::FieldReader::new(bits))
42    }
43}
44impl core::ops::Deref for ENABLE_R {
45    type Target = crate::FieldReader<bool, bool>;
46    #[inline(always)]
47    fn deref(&self) -> &Self::Target {
48        &self.0
49    }
50}
51#[doc = "Field `ENABLE` writer - ENABLE Synchronization Busy"]
52pub struct ENABLE_W<'a> {
53    w: &'a mut W,
54}
55impl<'a> ENABLE_W<'a> {
56    #[doc = r"Sets the field bit"]
57    #[inline(always)]
58    pub fn set_bit(self) -> &'a mut W {
59        self.bit(true)
60    }
61    #[doc = r"Clears the field bit"]
62    #[inline(always)]
63    pub fn clear_bit(self) -> &'a mut W {
64        self.bit(false)
65    }
66    #[doc = r"Writes raw bits to the field"]
67    #[inline(always)]
68    pub fn bit(self, value: bool) -> &'a mut W {
69        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u8 & 0x01) << 1);
70        self.w
71    }
72}
73#[doc = "Field `DFLLCTRLB` reader - DFLLCTRLB Synchronization Busy"]
74pub struct DFLLCTRLB_R(crate::FieldReader<bool, bool>);
75impl DFLLCTRLB_R {
76    pub(crate) fn new(bits: bool) -> Self {
77        DFLLCTRLB_R(crate::FieldReader::new(bits))
78    }
79}
80impl core::ops::Deref for DFLLCTRLB_R {
81    type Target = crate::FieldReader<bool, bool>;
82    #[inline(always)]
83    fn deref(&self) -> &Self::Target {
84        &self.0
85    }
86}
87#[doc = "Field `DFLLCTRLB` writer - DFLLCTRLB Synchronization Busy"]
88pub struct DFLLCTRLB_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DFLLCTRLB_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u8 & 0x01) << 2);
106        self.w
107    }
108}
109#[doc = "Field `DFLLVAL` reader - DFLLVAL Synchronization Busy"]
110pub struct DFLLVAL_R(crate::FieldReader<bool, bool>);
111impl DFLLVAL_R {
112    pub(crate) fn new(bits: bool) -> Self {
113        DFLLVAL_R(crate::FieldReader::new(bits))
114    }
115}
116impl core::ops::Deref for DFLLVAL_R {
117    type Target = crate::FieldReader<bool, bool>;
118    #[inline(always)]
119    fn deref(&self) -> &Self::Target {
120        &self.0
121    }
122}
123#[doc = "Field `DFLLVAL` writer - DFLLVAL Synchronization Busy"]
124pub struct DFLLVAL_W<'a> {
125    w: &'a mut W,
126}
127impl<'a> DFLLVAL_W<'a> {
128    #[doc = r"Sets the field bit"]
129    #[inline(always)]
130    pub fn set_bit(self) -> &'a mut W {
131        self.bit(true)
132    }
133    #[doc = r"Clears the field bit"]
134    #[inline(always)]
135    pub fn clear_bit(self) -> &'a mut W {
136        self.bit(false)
137    }
138    #[doc = r"Writes raw bits to the field"]
139    #[inline(always)]
140    pub fn bit(self, value: bool) -> &'a mut W {
141        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u8 & 0x01) << 3);
142        self.w
143    }
144}
145#[doc = "Field `DFLLMUL` reader - DFLLMUL Synchronization Busy"]
146pub struct DFLLMUL_R(crate::FieldReader<bool, bool>);
147impl DFLLMUL_R {
148    pub(crate) fn new(bits: bool) -> Self {
149        DFLLMUL_R(crate::FieldReader::new(bits))
150    }
151}
152impl core::ops::Deref for DFLLMUL_R {
153    type Target = crate::FieldReader<bool, bool>;
154    #[inline(always)]
155    fn deref(&self) -> &Self::Target {
156        &self.0
157    }
158}
159#[doc = "Field `DFLLMUL` writer - DFLLMUL Synchronization Busy"]
160pub struct DFLLMUL_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> DFLLMUL_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u8 & 0x01) << 4);
178        self.w
179    }
180}
181impl R {
182    #[doc = "Bit 1 - ENABLE Synchronization Busy"]
183    #[inline(always)]
184    pub fn enable(&self) -> ENABLE_R {
185        ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
186    }
187    #[doc = "Bit 2 - DFLLCTRLB Synchronization Busy"]
188    #[inline(always)]
189    pub fn dfllctrlb(&self) -> DFLLCTRLB_R {
190        DFLLCTRLB_R::new(((self.bits >> 2) & 0x01) != 0)
191    }
192    #[doc = "Bit 3 - DFLLVAL Synchronization Busy"]
193    #[inline(always)]
194    pub fn dfllval(&self) -> DFLLVAL_R {
195        DFLLVAL_R::new(((self.bits >> 3) & 0x01) != 0)
196    }
197    #[doc = "Bit 4 - DFLLMUL Synchronization Busy"]
198    #[inline(always)]
199    pub fn dfllmul(&self) -> DFLLMUL_R {
200        DFLLMUL_R::new(((self.bits >> 4) & 0x01) != 0)
201    }
202}
203impl W {
204    #[doc = "Bit 1 - ENABLE Synchronization Busy"]
205    #[inline(always)]
206    pub fn enable(&mut self) -> ENABLE_W {
207        ENABLE_W { w: self }
208    }
209    #[doc = "Bit 2 - DFLLCTRLB Synchronization Busy"]
210    #[inline(always)]
211    pub fn dfllctrlb(&mut self) -> DFLLCTRLB_W {
212        DFLLCTRLB_W { w: self }
213    }
214    #[doc = "Bit 3 - DFLLVAL Synchronization Busy"]
215    #[inline(always)]
216    pub fn dfllval(&mut self) -> DFLLVAL_W {
217        DFLLVAL_W { w: self }
218    }
219    #[doc = "Bit 4 - DFLLMUL Synchronization Busy"]
220    #[inline(always)]
221    pub fn dfllmul(&mut self) -> DFLLMUL_W {
222        DFLLMUL_W { w: self }
223    }
224    #[doc = "Writes raw bits to the register."]
225    #[inline(always)]
226    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
227        self.0.bits(bits);
228        self
229    }
230}
231#[doc = "DFLL48M Synchronization\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllsync](index.html) module"]
232pub struct DFLLSYNC_SPEC;
233impl crate::RegisterSpec for DFLLSYNC_SPEC {
234    type Ux = u8;
235}
236#[doc = "`read()` method returns [dfllsync::R](R) reader structure"]
237impl crate::Readable for DFLLSYNC_SPEC {
238    type Reader = R;
239}
240#[doc = "`write(|w| ..)` method takes [dfllsync::W](W) writer structure"]
241impl crate::Writable for DFLLSYNC_SPEC {
242    type Writer = W;
243}
244#[doc = "`reset()` method sets DFLLSYNC to value 0"]
245impl crate::Resettable for DFLLSYNC_SPEC {
246    #[inline(always)]
247    fn reset_value() -> Self::Ux {
248        0
249    }
250}
atsame51g18a_pac/oscctrl/dfllsync.rs

atsame51g18a_pac/oscctrl/
dfllsync.rs
