atsamd51p20a/ccl/
seqctrl.rs

1#[doc = "Reader of register SEQCTRL[%s]"]
2pub type R = crate::R<u8, super::SEQCTRL>;
3#[doc = "Writer for register SEQCTRL[%s]"]
4pub type W = crate::W<u8, super::SEQCTRL>;
5#[doc = "Register SEQCTRL[%s]
6`reset()`'s with value 0"]
7impl crate::ResetValue for super::SEQCTRL {
8    type Type = u8;
9    #[inline(always)]
10    fn reset_value() -> Self::Type {
11        0
12    }
13}
14#[doc = "Sequential Selection\n\nValue on reset: 0"]
15#[derive(Clone, Copy, Debug, PartialEq)]
16#[repr(u8)]
17pub enum SEQSEL_A {
18    #[doc = "0: Sequential logic is disabled"]
19    DISABLE = 0,
20    #[doc = "1: D flip flop"]
21    DFF = 1,
22    #[doc = "2: JK flip flop"]
23    JK = 2,
24    #[doc = "3: D latch"]
25    LATCH = 3,
26    #[doc = "4: RS latch"]
27    RS = 4,
28}
29impl From<SEQSEL_A> for u8 {
30    #[inline(always)]
31    fn from(variant: SEQSEL_A) -> Self {
32        variant as _
33    }
34}
35#[doc = "Reader of field `SEQSEL`"]
36pub type SEQSEL_R = crate::R<u8, SEQSEL_A>;
37impl SEQSEL_R {
38    #[doc = r"Get enumerated values variant"]
39    #[inline(always)]
40    pub fn variant(&self) -> crate::Variant<u8, SEQSEL_A> {
41        use crate::Variant::*;
42        match self.bits {
43            0 => Val(SEQSEL_A::DISABLE),
44            1 => Val(SEQSEL_A::DFF),
45            2 => Val(SEQSEL_A::JK),
46            3 => Val(SEQSEL_A::LATCH),
47            4 => Val(SEQSEL_A::RS),
48            i => Res(i),
49        }
50    }
51    #[doc = "Checks if the value of the field is `DISABLE`"]
52    #[inline(always)]
53    pub fn is_disable(&self) -> bool {
54        *self == SEQSEL_A::DISABLE
55    }
56    #[doc = "Checks if the value of the field is `DFF`"]
57    #[inline(always)]
58    pub fn is_dff(&self) -> bool {
59        *self == SEQSEL_A::DFF
60    }
61    #[doc = "Checks if the value of the field is `JK`"]
62    #[inline(always)]
63    pub fn is_jk(&self) -> bool {
64        *self == SEQSEL_A::JK
65    }
66    #[doc = "Checks if the value of the field is `LATCH`"]
67    #[inline(always)]
68    pub fn is_latch(&self) -> bool {
69        *self == SEQSEL_A::LATCH
70    }
71    #[doc = "Checks if the value of the field is `RS`"]
72    #[inline(always)]
73    pub fn is_rs(&self) -> bool {
74        *self == SEQSEL_A::RS
75    }
76}
77#[doc = "Write proxy for field `SEQSEL`"]
78pub struct SEQSEL_W<'a> {
79    w: &'a mut W,
80}
81impl<'a> SEQSEL_W<'a> {
82    #[doc = r"Writes `variant` to the field"]
83    #[inline(always)]
84    pub fn variant(self, variant: SEQSEL_A) -> &'a mut W {
85        unsafe { self.bits(variant.into()) }
86    }
87    #[doc = "Sequential logic is disabled"]
88    #[inline(always)]
89    pub fn disable(self) -> &'a mut W {
90        self.variant(SEQSEL_A::DISABLE)
91    }
92    #[doc = "D flip flop"]
93    #[inline(always)]
94    pub fn dff(self) -> &'a mut W {
95        self.variant(SEQSEL_A::DFF)
96    }
97    #[doc = "JK flip flop"]
98    #[inline(always)]
99    pub fn jk(self) -> &'a mut W {
100        self.variant(SEQSEL_A::JK)
101    }
102    #[doc = "D latch"]
103    #[inline(always)]
104    pub fn latch(self) -> &'a mut W {
105        self.variant(SEQSEL_A::LATCH)
106    }
107    #[doc = "RS latch"]
108    #[inline(always)]
109    pub fn rs(self) -> &'a mut W {
110        self.variant(SEQSEL_A::RS)
111    }
112    #[doc = r"Writes raw bits to the field"]
113    #[inline(always)]
114    pub unsafe fn bits(self, value: u8) -> &'a mut W {
115        self.w.bits = (self.w.bits & !0x0f) | ((value as u8) & 0x0f);
116        self.w
117    }
118}
119impl R {
120    #[doc = "Bits 0:3 - Sequential Selection"]
121    #[inline(always)]
122    pub fn seqsel(&self) -> SEQSEL_R {
123        SEQSEL_R::new((self.bits & 0x0f) as u8)
124    }
125}
126impl W {
127    #[doc = "Bits 0:3 - Sequential Selection"]
128    #[inline(always)]
129    pub fn seqsel(&mut self) -> SEQSEL_W {
130        SEQSEL_W { w: self }
131    }
132}
atsamd51p20a/ccl/seqctrl.rs

atsamd51p20a/ccl/
seqctrl.rs
