atsamd51n20a/oscctrl/
status.rs

1#[doc = "Reader of register STATUS"]
2pub type R = crate::R<u32, super::STATUS>;
3#[doc = "Reader of field `XOSCRDY0`"]
4pub type XOSCRDY0_R = crate::R<bool, bool>;
5#[doc = "Reader of field `XOSCRDY1`"]
6pub type XOSCRDY1_R = crate::R<bool, bool>;
7#[doc = "Reader of field `XOSCFAIL0`"]
8pub type XOSCFAIL0_R = crate::R<bool, bool>;
9#[doc = "Reader of field `XOSCFAIL1`"]
10pub type XOSCFAIL1_R = crate::R<bool, bool>;
11#[doc = "Reader of field `XOSCCKSW0`"]
12pub type XOSCCKSW0_R = crate::R<bool, bool>;
13#[doc = "Reader of field `XOSCCKSW1`"]
14pub type XOSCCKSW1_R = crate::R<bool, bool>;
15#[doc = "Reader of field `DFLLRDY`"]
16pub type DFLLRDY_R = crate::R<bool, bool>;
17#[doc = "Reader of field `DFLLOOB`"]
18pub type DFLLOOB_R = crate::R<bool, bool>;
19#[doc = "Reader of field `DFLLLCKF`"]
20pub type DFLLLCKF_R = crate::R<bool, bool>;
21#[doc = "Reader of field `DFLLLCKC`"]
22pub type DFLLLCKC_R = crate::R<bool, bool>;
23#[doc = "Reader of field `DFLLRCS`"]
24pub type DFLLRCS_R = crate::R<bool, bool>;
25#[doc = "Reader of field `DPLL0LCKR`"]
26pub type DPLL0LCKR_R = crate::R<bool, bool>;
27#[doc = "Reader of field `DPLL0LCKF`"]
28pub type DPLL0LCKF_R = crate::R<bool, bool>;
29#[doc = "Reader of field `DPLL0TO`"]
30pub type DPLL0TO_R = crate::R<bool, bool>;
31#[doc = "Reader of field `DPLL0LDRTO`"]
32pub type DPLL0LDRTO_R = crate::R<bool, bool>;
33#[doc = "Reader of field `DPLL1LCKR`"]
34pub type DPLL1LCKR_R = crate::R<bool, bool>;
35#[doc = "Reader of field `DPLL1LCKF`"]
36pub type DPLL1LCKF_R = crate::R<bool, bool>;
37#[doc = "Reader of field `DPLL1TO`"]
38pub type DPLL1TO_R = crate::R<bool, bool>;
39#[doc = "Reader of field `DPLL1LDRTO`"]
40pub type DPLL1LDRTO_R = crate::R<bool, bool>;
41impl R {
42    #[doc = "Bit 0 - XOSC 0 Ready"]
43    #[inline(always)]
44    pub fn xoscrdy0(&self) -> XOSCRDY0_R {
45        XOSCRDY0_R::new((self.bits & 0x01) != 0)
46    }
47    #[doc = "Bit 1 - XOSC 1 Ready"]
48    #[inline(always)]
49    pub fn xoscrdy1(&self) -> XOSCRDY1_R {
50        XOSCRDY1_R::new(((self.bits >> 1) & 0x01) != 0)
51    }
52    #[doc = "Bit 2 - XOSC 0 Clock Failure Detector"]
53    #[inline(always)]
54    pub fn xoscfail0(&self) -> XOSCFAIL0_R {
55        XOSCFAIL0_R::new(((self.bits >> 2) & 0x01) != 0)
56    }
57    #[doc = "Bit 3 - XOSC 1 Clock Failure Detector"]
58    #[inline(always)]
59    pub fn xoscfail1(&self) -> XOSCFAIL1_R {
60        XOSCFAIL1_R::new(((self.bits >> 3) & 0x01) != 0)
61    }
62    #[doc = "Bit 4 - XOSC 0 Clock Switch"]
63    #[inline(always)]
64    pub fn xosccksw0(&self) -> XOSCCKSW0_R {
65        XOSCCKSW0_R::new(((self.bits >> 4) & 0x01) != 0)
66    }
67    #[doc = "Bit 5 - XOSC 1 Clock Switch"]
68    #[inline(always)]
69    pub fn xosccksw1(&self) -> XOSCCKSW1_R {
70        XOSCCKSW1_R::new(((self.bits >> 5) & 0x01) != 0)
71    }
72    #[doc = "Bit 8 - DFLL Ready"]
73    #[inline(always)]
74    pub fn dfllrdy(&self) -> DFLLRDY_R {
75        DFLLRDY_R::new(((self.bits >> 8) & 0x01) != 0)
76    }
77    #[doc = "Bit 9 - DFLL Out Of Bounds"]
78    #[inline(always)]
79    pub fn dflloob(&self) -> DFLLOOB_R {
80        DFLLOOB_R::new(((self.bits >> 9) & 0x01) != 0)
81    }
82    #[doc = "Bit 10 - DFLL Lock Fine"]
83    #[inline(always)]
84    pub fn dflllckf(&self) -> DFLLLCKF_R {
85        DFLLLCKF_R::new(((self.bits >> 10) & 0x01) != 0)
86    }
87    #[doc = "Bit 11 - DFLL Lock Coarse"]
88    #[inline(always)]
89    pub fn dflllckc(&self) -> DFLLLCKC_R {
90        DFLLLCKC_R::new(((self.bits >> 11) & 0x01) != 0)
91    }
92    #[doc = "Bit 12 - DFLL Reference Clock Stopped"]
93    #[inline(always)]
94    pub fn dfllrcs(&self) -> DFLLRCS_R {
95        DFLLRCS_R::new(((self.bits >> 12) & 0x01) != 0)
96    }
97    #[doc = "Bit 16 - DPLL0 Lock Rise"]
98    #[inline(always)]
99    pub fn dpll0lckr(&self) -> DPLL0LCKR_R {
100        DPLL0LCKR_R::new(((self.bits >> 16) & 0x01) != 0)
101    }
102    #[doc = "Bit 17 - DPLL0 Lock Fall"]
103    #[inline(always)]
104    pub fn dpll0lckf(&self) -> DPLL0LCKF_R {
105        DPLL0LCKF_R::new(((self.bits >> 17) & 0x01) != 0)
106    }
107    #[doc = "Bit 18 - DPLL0 Timeout"]
108    #[inline(always)]
109    pub fn dpll0to(&self) -> DPLL0TO_R {
110        DPLL0TO_R::new(((self.bits >> 18) & 0x01) != 0)
111    }
112    #[doc = "Bit 19 - DPLL0 Loop Divider Ratio Update Complete"]
113    #[inline(always)]
114    pub fn dpll0ldrto(&self) -> DPLL0LDRTO_R {
115        DPLL0LDRTO_R::new(((self.bits >> 19) & 0x01) != 0)
116    }
117    #[doc = "Bit 24 - DPLL1 Lock Rise"]
118    #[inline(always)]
119    pub fn dpll1lckr(&self) -> DPLL1LCKR_R {
120        DPLL1LCKR_R::new(((self.bits >> 24) & 0x01) != 0)
121    }
122    #[doc = "Bit 25 - DPLL1 Lock Fall"]
123    #[inline(always)]
124    pub fn dpll1lckf(&self) -> DPLL1LCKF_R {
125        DPLL1LCKF_R::new(((self.bits >> 25) & 0x01) != 0)
126    }
127    #[doc = "Bit 26 - DPLL1 Timeout"]
128    #[inline(always)]
129    pub fn dpll1to(&self) -> DPLL1TO_R {
130        DPLL1TO_R::new(((self.bits >> 26) & 0x01) != 0)
131    }
132    #[doc = "Bit 27 - DPLL1 Loop Divider Ratio Update Complete"]
133    #[inline(always)]
134    pub fn dpll1ldrto(&self) -> DPLL1LDRTO_R {
135        DPLL1LDRTO_R::new(((self.bits >> 27) & 0x01) != 0)
136    }
137}
atsamd51n20a/oscctrl/status.rs

atsamd51n20a/oscctrl/
status.rs
