atsamd51n 0.14.2

Peripheral access API for ATSAMD51N microcontrollers (generated using svd2rust)
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145

#[doc = "Register `INTFLAG` reader"]
pub type R = crate::R<IntflagSpec>;
#[doc = "Register `INTFLAG` writer"]
pub type W = crate::W<IntflagSpec>;
#[doc = "Field `HSOF` reader - Host Start Of Frame"]
pub type HsofR = crate::BitReader;
#[doc = "Field `HSOF` writer - Host Start Of Frame"]
pub type HsofW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST` reader - Bus Reset"]
pub type RstR = crate::BitReader;
#[doc = "Field `RST` writer - Bus Reset"]
pub type RstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `WAKEUP` reader - Wake Up"]
pub type WakeupR = crate::BitReader;
#[doc = "Field `WAKEUP` writer - Wake Up"]
pub type WakeupW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DNRSM` reader - Downstream"]
pub type DnrsmR = crate::BitReader;
#[doc = "Field `DNRSM` writer - Downstream"]
pub type DnrsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `UPRSM` reader - Upstream Resume from the Device"]
pub type UprsmR = crate::BitReader;
#[doc = "Field `UPRSM` writer - Upstream Resume from the Device"]
pub type UprsmW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RAMACER` reader - Ram Access"]
pub type RamacerR = crate::BitReader;
#[doc = "Field `RAMACER` writer - Ram Access"]
pub type RamacerW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DCONN` reader - Device Connection"]
pub type DconnR = crate::BitReader;
#[doc = "Field `DCONN` writer - Device Connection"]
pub type DconnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DDISC` reader - Device Disconnection"]
pub type DdiscR = crate::BitReader;
#[doc = "Field `DDISC` writer - Device Disconnection"]
pub type DdiscW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 2 - Host Start Of Frame"]
    #[inline(always)]
    pub fn hsof(&self) -> HsofR {
        HsofR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Bus Reset"]
    #[inline(always)]
    pub fn rst(&self) -> RstR {
        RstR::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4 - Wake Up"]
    #[inline(always)]
    pub fn wakeup(&self) -> WakeupR {
        WakeupR::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - Downstream"]
    #[inline(always)]
    pub fn dnrsm(&self) -> DnrsmR {
        DnrsmR::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - Upstream Resume from the Device"]
    #[inline(always)]
    pub fn uprsm(&self) -> UprsmR {
        UprsmR::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - Ram Access"]
    #[inline(always)]
    pub fn ramacer(&self) -> RamacerR {
        RamacerR::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 8 - Device Connection"]
    #[inline(always)]
    pub fn dconn(&self) -> DconnR {
        DconnR::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - Device Disconnection"]
    #[inline(always)]
    pub fn ddisc(&self) -> DdiscR {
        DdiscR::new(((self.bits >> 9) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 2 - Host Start Of Frame"]
    #[inline(always)]
    #[must_use]
    pub fn hsof(&mut self) -> HsofW<IntflagSpec> {
        HsofW::new(self, 2)
    }
    #[doc = "Bit 3 - Bus Reset"]
    #[inline(always)]
    #[must_use]
    pub fn rst(&mut self) -> RstW<IntflagSpec> {
        RstW::new(self, 3)
    }
    #[doc = "Bit 4 - Wake Up"]
    #[inline(always)]
    #[must_use]
    pub fn wakeup(&mut self) -> WakeupW<IntflagSpec> {
        WakeupW::new(self, 4)
    }
    #[doc = "Bit 5 - Downstream"]
    #[inline(always)]
    #[must_use]
    pub fn dnrsm(&mut self) -> DnrsmW<IntflagSpec> {
        DnrsmW::new(self, 5)
    }
    #[doc = "Bit 6 - Upstream Resume from the Device"]
    #[inline(always)]
    #[must_use]
    pub fn uprsm(&mut self) -> UprsmW<IntflagSpec> {
        UprsmW::new(self, 6)
    }
    #[doc = "Bit 7 - Ram Access"]
    #[inline(always)]
    #[must_use]
    pub fn ramacer(&mut self) -> RamacerW<IntflagSpec> {
        RamacerW::new(self, 7)
    }
    #[doc = "Bit 8 - Device Connection"]
    #[inline(always)]
    #[must_use]
    pub fn dconn(&mut self) -> DconnW<IntflagSpec> {
        DconnW::new(self, 8)
    }
    #[doc = "Bit 9 - Device Disconnection"]
    #[inline(always)]
    #[must_use]
    pub fn ddisc(&mut self) -> DdiscW<IntflagSpec> {
        DdiscW::new(self, 9)
    }
}
#[doc = "HOST Host Interrupt Flag\n\nYou can [`read`](crate::Reg::read) this register and get [`intflag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intflag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntflagSpec;
impl crate::RegisterSpec for IntflagSpec {
    type Ux = u16;
}
#[doc = "`read()` method returns [`intflag::R`](R) reader structure"]
impl crate::Readable for IntflagSpec {}
#[doc = "`write(|w| ..)` method takes [`intflag::W`](W) writer structure"]
impl crate::Writable for IntflagSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
}
#[doc = "`reset()` method sets INTFLAG to value 0"]
impl crate::Resettable for IntflagSpec {
    const RESET_VALUE: u16 = 0;
}