atsamd51j20a/usb/host/
intenclr.rs

1#[doc = "Reader of register INTENCLR"]
2pub type R = crate::R<u16, super::INTENCLR>;
3#[doc = "Writer for register INTENCLR"]
4pub type W = crate::W<u16, super::INTENCLR>;
5#[doc = "Register INTENCLR `reset()`'s with value 0"]
6impl crate::ResetValue for super::INTENCLR {
7    type Type = u16;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `HSOF`"]
14pub type HSOF_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `HSOF`"]
16pub struct HSOF_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> HSOF_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u16) & 0x01) << 2);
34        self.w
35    }
36}
37#[doc = "Reader of field `RST`"]
38pub type RST_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `RST`"]
40pub struct RST_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> RST_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u16) & 0x01) << 3);
58        self.w
59    }
60}
61#[doc = "Reader of field `WAKEUP`"]
62pub type WAKEUP_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `WAKEUP`"]
64pub struct WAKEUP_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> WAKEUP_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u16) & 0x01) << 4);
82        self.w
83    }
84}
85#[doc = "Reader of field `DNRSM`"]
86pub type DNRSM_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DNRSM`"]
88pub struct DNRSM_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> DNRSM_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u16) & 0x01) << 5);
106        self.w
107    }
108}
109#[doc = "Reader of field `UPRSM`"]
110pub type UPRSM_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `UPRSM`"]
112pub struct UPRSM_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> UPRSM_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
130        self.w
131    }
132}
133#[doc = "Reader of field `RAMACER`"]
134pub type RAMACER_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `RAMACER`"]
136pub struct RAMACER_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> RAMACER_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
154        self.w
155    }
156}
157#[doc = "Reader of field `DCONN`"]
158pub type DCONN_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `DCONN`"]
160pub struct DCONN_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> DCONN_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u16) & 0x01) << 8);
178        self.w
179    }
180}
181#[doc = "Reader of field `DDISC`"]
182pub type DDISC_R = crate::R<bool, bool>;
183#[doc = "Write proxy for field `DDISC`"]
184pub struct DDISC_W<'a> {
185    w: &'a mut W,
186}
187impl<'a> DDISC_W<'a> {
188    #[doc = r"Sets the field bit"]
189    #[inline(always)]
190    pub fn set_bit(self) -> &'a mut W {
191        self.bit(true)
192    }
193    #[doc = r"Clears the field bit"]
194    #[inline(always)]
195    pub fn clear_bit(self) -> &'a mut W {
196        self.bit(false)
197    }
198    #[doc = r"Writes raw bits to the field"]
199    #[inline(always)]
200    pub fn bit(self, value: bool) -> &'a mut W {
201        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u16) & 0x01) << 9);
202        self.w
203    }
204}
205impl R {
206    #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"]
207    #[inline(always)]
208    pub fn hsof(&self) -> HSOF_R {
209        HSOF_R::new(((self.bits >> 2) & 0x01) != 0)
210    }
211    #[doc = "Bit 3 - BUS Reset Interrupt Disable"]
212    #[inline(always)]
213    pub fn rst(&self) -> RST_R {
214        RST_R::new(((self.bits >> 3) & 0x01) != 0)
215    }
216    #[doc = "Bit 4 - Wake Up Interrupt Disable"]
217    #[inline(always)]
218    pub fn wakeup(&self) -> WAKEUP_R {
219        WAKEUP_R::new(((self.bits >> 4) & 0x01) != 0)
220    }
221    #[doc = "Bit 5 - DownStream to Device Interrupt Disable"]
222    #[inline(always)]
223    pub fn dnrsm(&self) -> DNRSM_R {
224        DNRSM_R::new(((self.bits >> 5) & 0x01) != 0)
225    }
226    #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"]
227    #[inline(always)]
228    pub fn uprsm(&self) -> UPRSM_R {
229        UPRSM_R::new(((self.bits >> 6) & 0x01) != 0)
230    }
231    #[doc = "Bit 7 - Ram Access Interrupt Disable"]
232    #[inline(always)]
233    pub fn ramacer(&self) -> RAMACER_R {
234        RAMACER_R::new(((self.bits >> 7) & 0x01) != 0)
235    }
236    #[doc = "Bit 8 - Device Connection Interrupt Disable"]
237    #[inline(always)]
238    pub fn dconn(&self) -> DCONN_R {
239        DCONN_R::new(((self.bits >> 8) & 0x01) != 0)
240    }
241    #[doc = "Bit 9 - Device Disconnection Interrupt Disable"]
242    #[inline(always)]
243    pub fn ddisc(&self) -> DDISC_R {
244        DDISC_R::new(((self.bits >> 9) & 0x01) != 0)
245    }
246}
247impl W {
248    #[doc = "Bit 2 - Host Start Of Frame Interrupt Disable"]
249    #[inline(always)]
250    pub fn hsof(&mut self) -> HSOF_W {
251        HSOF_W { w: self }
252    }
253    #[doc = "Bit 3 - BUS Reset Interrupt Disable"]
254    #[inline(always)]
255    pub fn rst(&mut self) -> RST_W {
256        RST_W { w: self }
257    }
258    #[doc = "Bit 4 - Wake Up Interrupt Disable"]
259    #[inline(always)]
260    pub fn wakeup(&mut self) -> WAKEUP_W {
261        WAKEUP_W { w: self }
262    }
263    #[doc = "Bit 5 - DownStream to Device Interrupt Disable"]
264    #[inline(always)]
265    pub fn dnrsm(&mut self) -> DNRSM_W {
266        DNRSM_W { w: self }
267    }
268    #[doc = "Bit 6 - Upstream Resume from Device Interrupt Disable"]
269    #[inline(always)]
270    pub fn uprsm(&mut self) -> UPRSM_W {
271        UPRSM_W { w: self }
272    }
273    #[doc = "Bit 7 - Ram Access Interrupt Disable"]
274    #[inline(always)]
275    pub fn ramacer(&mut self) -> RAMACER_W {
276        RAMACER_W { w: self }
277    }
278    #[doc = "Bit 8 - Device Connection Interrupt Disable"]
279    #[inline(always)]
280    pub fn dconn(&mut self) -> DCONN_W {
281        DCONN_W { w: self }
282    }
283    #[doc = "Bit 9 - Device Disconnection Interrupt Disable"]
284    #[inline(always)]
285    pub fn ddisc(&mut self) -> DDISC_W {
286        DDISC_W { w: self }
287    }
288}
atsamd51j20a/usb/host/intenclr.rs

atsamd51j20a/usb/host/
intenclr.rs
