atsamd51j20a/rtc/mode2/
ctrlb.rs1#[doc = "Reader of register CTRLB"]
2pub type R = crate::R<u16, super::CTRLB>;
3#[doc = "Writer for register CTRLB"]
4pub type W = crate::W<u16, super::CTRLB>;
5#[doc = "Register CTRLB `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRLB {
7 type Type = u16;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Reader of field `GP0EN`"]
14pub type GP0EN_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `GP0EN`"]
16pub struct GP0EN_W<'a> {
17 w: &'a mut W,
18}
19impl<'a> GP0EN_W<'a> {
20 #[doc = r"Sets the field bit"]
21 #[inline(always)]
22 pub fn set_bit(self) -> &'a mut W {
23 self.bit(true)
24 }
25 #[doc = r"Clears the field bit"]
26 #[inline(always)]
27 pub fn clear_bit(self) -> &'a mut W {
28 self.bit(false)
29 }
30 #[doc = r"Writes raw bits to the field"]
31 #[inline(always)]
32 pub fn bit(self, value: bool) -> &'a mut W {
33 self.w.bits = (self.w.bits & !0x01) | ((value as u16) & 0x01);
34 self.w
35 }
36}
37#[doc = "Reader of field `GP2EN`"]
38pub type GP2EN_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `GP2EN`"]
40pub struct GP2EN_W<'a> {
41 w: &'a mut W,
42}
43impl<'a> GP2EN_W<'a> {
44 #[doc = r"Sets the field bit"]
45 #[inline(always)]
46 pub fn set_bit(self) -> &'a mut W {
47 self.bit(true)
48 }
49 #[doc = r"Clears the field bit"]
50 #[inline(always)]
51 pub fn clear_bit(self) -> &'a mut W {
52 self.bit(false)
53 }
54 #[doc = r"Writes raw bits to the field"]
55 #[inline(always)]
56 pub fn bit(self, value: bool) -> &'a mut W {
57 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u16) & 0x01) << 1);
58 self.w
59 }
60}
61#[doc = "Reader of field `DEBMAJ`"]
62pub type DEBMAJ_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `DEBMAJ`"]
64pub struct DEBMAJ_W<'a> {
65 w: &'a mut W,
66}
67impl<'a> DEBMAJ_W<'a> {
68 #[doc = r"Sets the field bit"]
69 #[inline(always)]
70 pub fn set_bit(self) -> &'a mut W {
71 self.bit(true)
72 }
73 #[doc = r"Clears the field bit"]
74 #[inline(always)]
75 pub fn clear_bit(self) -> &'a mut W {
76 self.bit(false)
77 }
78 #[doc = r"Writes raw bits to the field"]
79 #[inline(always)]
80 pub fn bit(self, value: bool) -> &'a mut W {
81 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u16) & 0x01) << 4);
82 self.w
83 }
84}
85#[doc = "Reader of field `DEBASYNC`"]
86pub type DEBASYNC_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `DEBASYNC`"]
88pub struct DEBASYNC_W<'a> {
89 w: &'a mut W,
90}
91impl<'a> DEBASYNC_W<'a> {
92 #[doc = r"Sets the field bit"]
93 #[inline(always)]
94 pub fn set_bit(self) -> &'a mut W {
95 self.bit(true)
96 }
97 #[doc = r"Clears the field bit"]
98 #[inline(always)]
99 pub fn clear_bit(self) -> &'a mut W {
100 self.bit(false)
101 }
102 #[doc = r"Writes raw bits to the field"]
103 #[inline(always)]
104 pub fn bit(self, value: bool) -> &'a mut W {
105 self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u16) & 0x01) << 5);
106 self.w
107 }
108}
109#[doc = "Reader of field `RTCOUT`"]
110pub type RTCOUT_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `RTCOUT`"]
112pub struct RTCOUT_W<'a> {
113 w: &'a mut W,
114}
115impl<'a> RTCOUT_W<'a> {
116 #[doc = r"Sets the field bit"]
117 #[inline(always)]
118 pub fn set_bit(self) -> &'a mut W {
119 self.bit(true)
120 }
121 #[doc = r"Clears the field bit"]
122 #[inline(always)]
123 pub fn clear_bit(self) -> &'a mut W {
124 self.bit(false)
125 }
126 #[doc = r"Writes raw bits to the field"]
127 #[inline(always)]
128 pub fn bit(self, value: bool) -> &'a mut W {
129 self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u16) & 0x01) << 6);
130 self.w
131 }
132}
133#[doc = "Reader of field `DMAEN`"]
134pub type DMAEN_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `DMAEN`"]
136pub struct DMAEN_W<'a> {
137 w: &'a mut W,
138}
139impl<'a> DMAEN_W<'a> {
140 #[doc = r"Sets the field bit"]
141 #[inline(always)]
142 pub fn set_bit(self) -> &'a mut W {
143 self.bit(true)
144 }
145 #[doc = r"Clears the field bit"]
146 #[inline(always)]
147 pub fn clear_bit(self) -> &'a mut W {
148 self.bit(false)
149 }
150 #[doc = r"Writes raw bits to the field"]
151 #[inline(always)]
152 pub fn bit(self, value: bool) -> &'a mut W {
153 self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u16) & 0x01) << 7);
154 self.w
155 }
156}
157#[doc = "Debounce Freqnuency\n\nValue on reset: 0"]
158#[derive(Clone, Copy, Debug, PartialEq)]
159#[repr(u8)]
160pub enum DEBF_A {
161 #[doc = "0: CLK_RTC_DEB = CLK_RTC/2"]
162 DIV2 = 0,
163 #[doc = "1: CLK_RTC_DEB = CLK_RTC/4"]
164 DIV4 = 1,
165 #[doc = "2: CLK_RTC_DEB = CLK_RTC/8"]
166 DIV8 = 2,
167 #[doc = "3: CLK_RTC_DEB = CLK_RTC/16"]
168 DIV16 = 3,
169 #[doc = "4: CLK_RTC_DEB = CLK_RTC/32"]
170 DIV32 = 4,
171 #[doc = "5: CLK_RTC_DEB = CLK_RTC/64"]
172 DIV64 = 5,
173 #[doc = "6: CLK_RTC_DEB = CLK_RTC/128"]
174 DIV128 = 6,
175 #[doc = "7: CLK_RTC_DEB = CLK_RTC/256"]
176 DIV256 = 7,
177}
178impl From<DEBF_A> for u8 {
179 #[inline(always)]
180 fn from(variant: DEBF_A) -> Self {
181 variant as _
182 }
183}
184#[doc = "Reader of field `DEBF`"]
185pub type DEBF_R = crate::R<u8, DEBF_A>;
186impl DEBF_R {
187 #[doc = r"Get enumerated values variant"]
188 #[inline(always)]
189 pub fn variant(&self) -> DEBF_A {
190 match self.bits {
191 0 => DEBF_A::DIV2,
192 1 => DEBF_A::DIV4,
193 2 => DEBF_A::DIV8,
194 3 => DEBF_A::DIV16,
195 4 => DEBF_A::DIV32,
196 5 => DEBF_A::DIV64,
197 6 => DEBF_A::DIV128,
198 7 => DEBF_A::DIV256,
199 _ => unreachable!(),
200 }
201 }
202 #[doc = "Checks if the value of the field is `DIV2`"]
203 #[inline(always)]
204 pub fn is_div2(&self) -> bool {
205 *self == DEBF_A::DIV2
206 }
207 #[doc = "Checks if the value of the field is `DIV4`"]
208 #[inline(always)]
209 pub fn is_div4(&self) -> bool {
210 *self == DEBF_A::DIV4
211 }
212 #[doc = "Checks if the value of the field is `DIV8`"]
213 #[inline(always)]
214 pub fn is_div8(&self) -> bool {
215 *self == DEBF_A::DIV8
216 }
217 #[doc = "Checks if the value of the field is `DIV16`"]
218 #[inline(always)]
219 pub fn is_div16(&self) -> bool {
220 *self == DEBF_A::DIV16
221 }
222 #[doc = "Checks if the value of the field is `DIV32`"]
223 #[inline(always)]
224 pub fn is_div32(&self) -> bool {
225 *self == DEBF_A::DIV32
226 }
227 #[doc = "Checks if the value of the field is `DIV64`"]
228 #[inline(always)]
229 pub fn is_div64(&self) -> bool {
230 *self == DEBF_A::DIV64
231 }
232 #[doc = "Checks if the value of the field is `DIV128`"]
233 #[inline(always)]
234 pub fn is_div128(&self) -> bool {
235 *self == DEBF_A::DIV128
236 }
237 #[doc = "Checks if the value of the field is `DIV256`"]
238 #[inline(always)]
239 pub fn is_div256(&self) -> bool {
240 *self == DEBF_A::DIV256
241 }
242}
243#[doc = "Write proxy for field `DEBF`"]
244pub struct DEBF_W<'a> {
245 w: &'a mut W,
246}
247impl<'a> DEBF_W<'a> {
248 #[doc = r"Writes `variant` to the field"]
249 #[inline(always)]
250 pub fn variant(self, variant: DEBF_A) -> &'a mut W {
251 {
252 self.bits(variant.into())
253 }
254 }
255 #[doc = "CLK_RTC_DEB = CLK_RTC/2"]
256 #[inline(always)]
257 pub fn div2(self) -> &'a mut W {
258 self.variant(DEBF_A::DIV2)
259 }
260 #[doc = "CLK_RTC_DEB = CLK_RTC/4"]
261 #[inline(always)]
262 pub fn div4(self) -> &'a mut W {
263 self.variant(DEBF_A::DIV4)
264 }
265 #[doc = "CLK_RTC_DEB = CLK_RTC/8"]
266 #[inline(always)]
267 pub fn div8(self) -> &'a mut W {
268 self.variant(DEBF_A::DIV8)
269 }
270 #[doc = "CLK_RTC_DEB = CLK_RTC/16"]
271 #[inline(always)]
272 pub fn div16(self) -> &'a mut W {
273 self.variant(DEBF_A::DIV16)
274 }
275 #[doc = "CLK_RTC_DEB = CLK_RTC/32"]
276 #[inline(always)]
277 pub fn div32(self) -> &'a mut W {
278 self.variant(DEBF_A::DIV32)
279 }
280 #[doc = "CLK_RTC_DEB = CLK_RTC/64"]
281 #[inline(always)]
282 pub fn div64(self) -> &'a mut W {
283 self.variant(DEBF_A::DIV64)
284 }
285 #[doc = "CLK_RTC_DEB = CLK_RTC/128"]
286 #[inline(always)]
287 pub fn div128(self) -> &'a mut W {
288 self.variant(DEBF_A::DIV128)
289 }
290 #[doc = "CLK_RTC_DEB = CLK_RTC/256"]
291 #[inline(always)]
292 pub fn div256(self) -> &'a mut W {
293 self.variant(DEBF_A::DIV256)
294 }
295 #[doc = r"Writes raw bits to the field"]
296 #[inline(always)]
297 pub fn bits(self, value: u8) -> &'a mut W {
298 self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u16) & 0x07) << 8);
299 self.w
300 }
301}
302#[doc = "Active Layer Freqnuency\n\nValue on reset: 0"]
303#[derive(Clone, Copy, Debug, PartialEq)]
304#[repr(u8)]
305pub enum ACTF_A {
306 #[doc = "0: CLK_RTC_OUT = CLK_RTC/2"]
307 DIV2 = 0,
308 #[doc = "1: CLK_RTC_OUT = CLK_RTC/4"]
309 DIV4 = 1,
310 #[doc = "2: CLK_RTC_OUT = CLK_RTC/8"]
311 DIV8 = 2,
312 #[doc = "3: CLK_RTC_OUT = CLK_RTC/16"]
313 DIV16 = 3,
314 #[doc = "4: CLK_RTC_OUT = CLK_RTC/32"]
315 DIV32 = 4,
316 #[doc = "5: CLK_RTC_OUT = CLK_RTC/64"]
317 DIV64 = 5,
318 #[doc = "6: CLK_RTC_OUT = CLK_RTC/128"]
319 DIV128 = 6,
320 #[doc = "7: CLK_RTC_OUT = CLK_RTC/256"]
321 DIV256 = 7,
322}
323impl From<ACTF_A> for u8 {
324 #[inline(always)]
325 fn from(variant: ACTF_A) -> Self {
326 variant as _
327 }
328}
329#[doc = "Reader of field `ACTF`"]
330pub type ACTF_R = crate::R<u8, ACTF_A>;
331impl ACTF_R {
332 #[doc = r"Get enumerated values variant"]
333 #[inline(always)]
334 pub fn variant(&self) -> ACTF_A {
335 match self.bits {
336 0 => ACTF_A::DIV2,
337 1 => ACTF_A::DIV4,
338 2 => ACTF_A::DIV8,
339 3 => ACTF_A::DIV16,
340 4 => ACTF_A::DIV32,
341 5 => ACTF_A::DIV64,
342 6 => ACTF_A::DIV128,
343 7 => ACTF_A::DIV256,
344 _ => unreachable!(),
345 }
346 }
347 #[doc = "Checks if the value of the field is `DIV2`"]
348 #[inline(always)]
349 pub fn is_div2(&self) -> bool {
350 *self == ACTF_A::DIV2
351 }
352 #[doc = "Checks if the value of the field is `DIV4`"]
353 #[inline(always)]
354 pub fn is_div4(&self) -> bool {
355 *self == ACTF_A::DIV4
356 }
357 #[doc = "Checks if the value of the field is `DIV8`"]
358 #[inline(always)]
359 pub fn is_div8(&self) -> bool {
360 *self == ACTF_A::DIV8
361 }
362 #[doc = "Checks if the value of the field is `DIV16`"]
363 #[inline(always)]
364 pub fn is_div16(&self) -> bool {
365 *self == ACTF_A::DIV16
366 }
367 #[doc = "Checks if the value of the field is `DIV32`"]
368 #[inline(always)]
369 pub fn is_div32(&self) -> bool {
370 *self == ACTF_A::DIV32
371 }
372 #[doc = "Checks if the value of the field is `DIV64`"]
373 #[inline(always)]
374 pub fn is_div64(&self) -> bool {
375 *self == ACTF_A::DIV64
376 }
377 #[doc = "Checks if the value of the field is `DIV128`"]
378 #[inline(always)]
379 pub fn is_div128(&self) -> bool {
380 *self == ACTF_A::DIV128
381 }
382 #[doc = "Checks if the value of the field is `DIV256`"]
383 #[inline(always)]
384 pub fn is_div256(&self) -> bool {
385 *self == ACTF_A::DIV256
386 }
387}
388#[doc = "Write proxy for field `ACTF`"]
389pub struct ACTF_W<'a> {
390 w: &'a mut W,
391}
392impl<'a> ACTF_W<'a> {
393 #[doc = r"Writes `variant` to the field"]
394 #[inline(always)]
395 pub fn variant(self, variant: ACTF_A) -> &'a mut W {
396 {
397 self.bits(variant.into())
398 }
399 }
400 #[doc = "CLK_RTC_OUT = CLK_RTC/2"]
401 #[inline(always)]
402 pub fn div2(self) -> &'a mut W {
403 self.variant(ACTF_A::DIV2)
404 }
405 #[doc = "CLK_RTC_OUT = CLK_RTC/4"]
406 #[inline(always)]
407 pub fn div4(self) -> &'a mut W {
408 self.variant(ACTF_A::DIV4)
409 }
410 #[doc = "CLK_RTC_OUT = CLK_RTC/8"]
411 #[inline(always)]
412 pub fn div8(self) -> &'a mut W {
413 self.variant(ACTF_A::DIV8)
414 }
415 #[doc = "CLK_RTC_OUT = CLK_RTC/16"]
416 #[inline(always)]
417 pub fn div16(self) -> &'a mut W {
418 self.variant(ACTF_A::DIV16)
419 }
420 #[doc = "CLK_RTC_OUT = CLK_RTC/32"]
421 #[inline(always)]
422 pub fn div32(self) -> &'a mut W {
423 self.variant(ACTF_A::DIV32)
424 }
425 #[doc = "CLK_RTC_OUT = CLK_RTC/64"]
426 #[inline(always)]
427 pub fn div64(self) -> &'a mut W {
428 self.variant(ACTF_A::DIV64)
429 }
430 #[doc = "CLK_RTC_OUT = CLK_RTC/128"]
431 #[inline(always)]
432 pub fn div128(self) -> &'a mut W {
433 self.variant(ACTF_A::DIV128)
434 }
435 #[doc = "CLK_RTC_OUT = CLK_RTC/256"]
436 #[inline(always)]
437 pub fn div256(self) -> &'a mut W {
438 self.variant(ACTF_A::DIV256)
439 }
440 #[doc = r"Writes raw bits to the field"]
441 #[inline(always)]
442 pub fn bits(self, value: u8) -> &'a mut W {
443 self.w.bits = (self.w.bits & !(0x07 << 12)) | (((value as u16) & 0x07) << 12);
444 self.w
445 }
446}
447impl R {
448 #[doc = "Bit 0 - General Purpose 0 Enable"]
449 #[inline(always)]
450 pub fn gp0en(&self) -> GP0EN_R {
451 GP0EN_R::new((self.bits & 0x01) != 0)
452 }
453 #[doc = "Bit 1 - General Purpose 2 Enable"]
454 #[inline(always)]
455 pub fn gp2en(&self) -> GP2EN_R {
456 GP2EN_R::new(((self.bits >> 1) & 0x01) != 0)
457 }
458 #[doc = "Bit 4 - Debouncer Majority Enable"]
459 #[inline(always)]
460 pub fn debmaj(&self) -> DEBMAJ_R {
461 DEBMAJ_R::new(((self.bits >> 4) & 0x01) != 0)
462 }
463 #[doc = "Bit 5 - Debouncer Asynchronous Enable"]
464 #[inline(always)]
465 pub fn debasync(&self) -> DEBASYNC_R {
466 DEBASYNC_R::new(((self.bits >> 5) & 0x01) != 0)
467 }
468 #[doc = "Bit 6 - RTC Output Enable"]
469 #[inline(always)]
470 pub fn rtcout(&self) -> RTCOUT_R {
471 RTCOUT_R::new(((self.bits >> 6) & 0x01) != 0)
472 }
473 #[doc = "Bit 7 - DMA Enable"]
474 #[inline(always)]
475 pub fn dmaen(&self) -> DMAEN_R {
476 DMAEN_R::new(((self.bits >> 7) & 0x01) != 0)
477 }
478 #[doc = "Bits 8:10 - Debounce Freqnuency"]
479 #[inline(always)]
480 pub fn debf(&self) -> DEBF_R {
481 DEBF_R::new(((self.bits >> 8) & 0x07) as u8)
482 }
483 #[doc = "Bits 12:14 - Active Layer Freqnuency"]
484 #[inline(always)]
485 pub fn actf(&self) -> ACTF_R {
486 ACTF_R::new(((self.bits >> 12) & 0x07) as u8)
487 }
488}
489impl W {
490 #[doc = "Bit 0 - General Purpose 0 Enable"]
491 #[inline(always)]
492 pub fn gp0en(&mut self) -> GP0EN_W {
493 GP0EN_W { w: self }
494 }
495 #[doc = "Bit 1 - General Purpose 2 Enable"]
496 #[inline(always)]
497 pub fn gp2en(&mut self) -> GP2EN_W {
498 GP2EN_W { w: self }
499 }
500 #[doc = "Bit 4 - Debouncer Majority Enable"]
501 #[inline(always)]
502 pub fn debmaj(&mut self) -> DEBMAJ_W {
503 DEBMAJ_W { w: self }
504 }
505 #[doc = "Bit 5 - Debouncer Asynchronous Enable"]
506 #[inline(always)]
507 pub fn debasync(&mut self) -> DEBASYNC_W {
508 DEBASYNC_W { w: self }
509 }
510 #[doc = "Bit 6 - RTC Output Enable"]
511 #[inline(always)]
512 pub fn rtcout(&mut self) -> RTCOUT_W {
513 RTCOUT_W { w: self }
514 }
515 #[doc = "Bit 7 - DMA Enable"]
516 #[inline(always)]
517 pub fn dmaen(&mut self) -> DMAEN_W {
518 DMAEN_W { w: self }
519 }
520 #[doc = "Bits 8:10 - Debounce Freqnuency"]
521 #[inline(always)]
522 pub fn debf(&mut self) -> DEBF_W {
523 DEBF_W { w: self }
524 }
525 #[doc = "Bits 12:14 - Active Layer Freqnuency"]
526 #[inline(always)]
527 pub fn actf(&mut self) -> ACTF_W {
528 ACTF_W { w: self }
529 }
530}