atsamd51j20a/tcc0/
ctrlbclr.rs

1#[doc = "Reader of register CTRLBCLR"]
2pub type R = crate::R<u8, super::CTRLBCLR>;
3#[doc = "Writer for register CTRLBCLR"]
4pub type W = crate::W<u8, super::CTRLBCLR>;
5#[doc = "Register CTRLBCLR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRLBCLR {
7    type Type = u8;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DIR`"]
14pub type DIR_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `DIR`"]
16pub struct DIR_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DIR_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !0x01) | ((value as u8) & 0x01);
34        self.w
35    }
36}
37#[doc = "Reader of field `LUPD`"]
38pub type LUPD_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `LUPD`"]
40pub struct LUPD_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> LUPD_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u8) & 0x01) << 1);
58        self.w
59    }
60}
61#[doc = "Reader of field `ONESHOT`"]
62pub type ONESHOT_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `ONESHOT`"]
64pub struct ONESHOT_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> ONESHOT_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u8) & 0x01) << 2);
82        self.w
83    }
84}
85#[doc = "Ramp Index Command\n\nValue on reset: 0"]
86#[derive(Clone, Copy, Debug, PartialEq)]
87#[repr(u8)]
88pub enum IDXCMD_A {
89    #[doc = "0: Command disabled: Index toggles between cycles A and B"]
90    DISABLE = 0,
91    #[doc = "1: Set index: cycle B will be forced in the next cycle"]
92    SET = 1,
93    #[doc = "2: Clear index: cycle A will be forced in the next cycle"]
94    CLEAR = 2,
95    #[doc = "3: Hold index: the next cycle will be the same as the current cycle"]
96    HOLD = 3,
97}
98impl From<IDXCMD_A> for u8 {
99    #[inline(always)]
100    fn from(variant: IDXCMD_A) -> Self {
101        variant as _
102    }
103}
104#[doc = "Reader of field `IDXCMD`"]
105pub type IDXCMD_R = crate::R<u8, IDXCMD_A>;
106impl IDXCMD_R {
107    #[doc = r"Get enumerated values variant"]
108    #[inline(always)]
109    pub fn variant(&self) -> IDXCMD_A {
110        match self.bits {
111            0 => IDXCMD_A::DISABLE,
112            1 => IDXCMD_A::SET,
113            2 => IDXCMD_A::CLEAR,
114            3 => IDXCMD_A::HOLD,
115            _ => unreachable!(),
116        }
117    }
118    #[doc = "Checks if the value of the field is `DISABLE`"]
119    #[inline(always)]
120    pub fn is_disable(&self) -> bool {
121        *self == IDXCMD_A::DISABLE
122    }
123    #[doc = "Checks if the value of the field is `SET`"]
124    #[inline(always)]
125    pub fn is_set(&self) -> bool {
126        *self == IDXCMD_A::SET
127    }
128    #[doc = "Checks if the value of the field is `CLEAR`"]
129    #[inline(always)]
130    pub fn is_clear(&self) -> bool {
131        *self == IDXCMD_A::CLEAR
132    }
133    #[doc = "Checks if the value of the field is `HOLD`"]
134    #[inline(always)]
135    pub fn is_hold(&self) -> bool {
136        *self == IDXCMD_A::HOLD
137    }
138}
139#[doc = "Write proxy for field `IDXCMD`"]
140pub struct IDXCMD_W<'a> {
141    w: &'a mut W,
142}
143impl<'a> IDXCMD_W<'a> {
144    #[doc = r"Writes `variant` to the field"]
145    #[inline(always)]
146    pub fn variant(self, variant: IDXCMD_A) -> &'a mut W {
147        {
148            self.bits(variant.into())
149        }
150    }
151    #[doc = "Command disabled: Index toggles between cycles A and B"]
152    #[inline(always)]
153    pub fn disable(self) -> &'a mut W {
154        self.variant(IDXCMD_A::DISABLE)
155    }
156    #[doc = "Set index: cycle B will be forced in the next cycle"]
157    #[inline(always)]
158    pub fn set(self) -> &'a mut W {
159        self.variant(IDXCMD_A::SET)
160    }
161    #[doc = "Clear index: cycle A will be forced in the next cycle"]
162    #[inline(always)]
163    pub fn clear(self) -> &'a mut W {
164        self.variant(IDXCMD_A::CLEAR)
165    }
166    #[doc = "Hold index: the next cycle will be the same as the current cycle"]
167    #[inline(always)]
168    pub fn hold(self) -> &'a mut W {
169        self.variant(IDXCMD_A::HOLD)
170    }
171    #[doc = r"Writes raw bits to the field"]
172    #[inline(always)]
173    pub fn bits(self, value: u8) -> &'a mut W {
174        self.w.bits = (self.w.bits & !(0x03 << 3)) | (((value as u8) & 0x03) << 3);
175        self.w
176    }
177}
178#[doc = "TCC Command\n\nValue on reset: 0"]
179#[derive(Clone, Copy, Debug, PartialEq)]
180#[repr(u8)]
181pub enum CMD_A {
182    #[doc = "0: No action"]
183    NONE = 0,
184    #[doc = "1: Clear start, restart or retrigger"]
185    RETRIGGER = 1,
186    #[doc = "2: Force stop"]
187    STOP = 2,
188    #[doc = "3: Force update or double buffered registers"]
189    UPDATE = 3,
190    #[doc = "4: Force COUNT read synchronization"]
191    READSYNC = 4,
192    #[doc = "5: One-shot DMA trigger"]
193    DMAOS = 5,
194}
195impl From<CMD_A> for u8 {
196    #[inline(always)]
197    fn from(variant: CMD_A) -> Self {
198        variant as _
199    }
200}
201#[doc = "Reader of field `CMD`"]
202pub type CMD_R = crate::R<u8, CMD_A>;
203impl CMD_R {
204    #[doc = r"Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> crate::Variant<u8, CMD_A> {
207        use crate::Variant::*;
208        match self.bits {
209            0 => Val(CMD_A::NONE),
210            1 => Val(CMD_A::RETRIGGER),
211            2 => Val(CMD_A::STOP),
212            3 => Val(CMD_A::UPDATE),
213            4 => Val(CMD_A::READSYNC),
214            5 => Val(CMD_A::DMAOS),
215            i => Res(i),
216        }
217    }
218    #[doc = "Checks if the value of the field is `NONE`"]
219    #[inline(always)]
220    pub fn is_none(&self) -> bool {
221        *self == CMD_A::NONE
222    }
223    #[doc = "Checks if the value of the field is `RETRIGGER`"]
224    #[inline(always)]
225    pub fn is_retrigger(&self) -> bool {
226        *self == CMD_A::RETRIGGER
227    }
228    #[doc = "Checks if the value of the field is `STOP`"]
229    #[inline(always)]
230    pub fn is_stop(&self) -> bool {
231        *self == CMD_A::STOP
232    }
233    #[doc = "Checks if the value of the field is `UPDATE`"]
234    #[inline(always)]
235    pub fn is_update(&self) -> bool {
236        *self == CMD_A::UPDATE
237    }
238    #[doc = "Checks if the value of the field is `READSYNC`"]
239    #[inline(always)]
240    pub fn is_readsync(&self) -> bool {
241        *self == CMD_A::READSYNC
242    }
243    #[doc = "Checks if the value of the field is `DMAOS`"]
244    #[inline(always)]
245    pub fn is_dmaos(&self) -> bool {
246        *self == CMD_A::DMAOS
247    }
248}
249#[doc = "Write proxy for field `CMD`"]
250pub struct CMD_W<'a> {
251    w: &'a mut W,
252}
253impl<'a> CMD_W<'a> {
254    #[doc = r"Writes `variant` to the field"]
255    #[inline(always)]
256    pub fn variant(self, variant: CMD_A) -> &'a mut W {
257        unsafe { self.bits(variant.into()) }
258    }
259    #[doc = "No action"]
260    #[inline(always)]
261    pub fn none(self) -> &'a mut W {
262        self.variant(CMD_A::NONE)
263    }
264    #[doc = "Clear start, restart or retrigger"]
265    #[inline(always)]
266    pub fn retrigger(self) -> &'a mut W {
267        self.variant(CMD_A::RETRIGGER)
268    }
269    #[doc = "Force stop"]
270    #[inline(always)]
271    pub fn stop(self) -> &'a mut W {
272        self.variant(CMD_A::STOP)
273    }
274    #[doc = "Force update or double buffered registers"]
275    #[inline(always)]
276    pub fn update(self) -> &'a mut W {
277        self.variant(CMD_A::UPDATE)
278    }
279    #[doc = "Force COUNT read synchronization"]
280    #[inline(always)]
281    pub fn readsync(self) -> &'a mut W {
282        self.variant(CMD_A::READSYNC)
283    }
284    #[doc = "One-shot DMA trigger"]
285    #[inline(always)]
286    pub fn dmaos(self) -> &'a mut W {
287        self.variant(CMD_A::DMAOS)
288    }
289    #[doc = r"Writes raw bits to the field"]
290    #[inline(always)]
291    pub unsafe fn bits(self, value: u8) -> &'a mut W {
292        self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u8) & 0x07) << 5);
293        self.w
294    }
295}
296impl R {
297    #[doc = "Bit 0 - Counter Direction"]
298    #[inline(always)]
299    pub fn dir(&self) -> DIR_R {
300        DIR_R::new((self.bits & 0x01) != 0)
301    }
302    #[doc = "Bit 1 - Lock Update"]
303    #[inline(always)]
304    pub fn lupd(&self) -> LUPD_R {
305        LUPD_R::new(((self.bits >> 1) & 0x01) != 0)
306    }
307    #[doc = "Bit 2 - One-Shot"]
308    #[inline(always)]
309    pub fn oneshot(&self) -> ONESHOT_R {
310        ONESHOT_R::new(((self.bits >> 2) & 0x01) != 0)
311    }
312    #[doc = "Bits 3:4 - Ramp Index Command"]
313    #[inline(always)]
314    pub fn idxcmd(&self) -> IDXCMD_R {
315        IDXCMD_R::new(((self.bits >> 3) & 0x03) as u8)
316    }
317    #[doc = "Bits 5:7 - TCC Command"]
318    #[inline(always)]
319    pub fn cmd(&self) -> CMD_R {
320        CMD_R::new(((self.bits >> 5) & 0x07) as u8)
321    }
322}
323impl W {
324    #[doc = "Bit 0 - Counter Direction"]
325    #[inline(always)]
326    pub fn dir(&mut self) -> DIR_W {
327        DIR_W { w: self }
328    }
329    #[doc = "Bit 1 - Lock Update"]
330    #[inline(always)]
331    pub fn lupd(&mut self) -> LUPD_W {
332        LUPD_W { w: self }
333    }
334    #[doc = "Bit 2 - One-Shot"]
335    #[inline(always)]
336    pub fn oneshot(&mut self) -> ONESHOT_W {
337        ONESHOT_W { w: self }
338    }
339    #[doc = "Bits 3:4 - Ramp Index Command"]
340    #[inline(always)]
341    pub fn idxcmd(&mut self) -> IDXCMD_W {
342        IDXCMD_W { w: self }
343    }
344    #[doc = "Bits 5:7 - TCC Command"]
345    #[inline(always)]
346    pub fn cmd(&mut self) -> CMD_W {
347        CMD_W { w: self }
348    }
349}
atsamd51j20a/tcc0/ctrlbclr.rs

atsamd51j20a/tcc0/
ctrlbclr.rs
