atsamd51j19a/gclk/
genctrl.rs

1#[doc = "Reader of register GENCTRL[%s]"]
2pub type R = crate::R<u32, super::GENCTRL>;
3#[doc = "Writer for register GENCTRL[%s]"]
4pub type W = crate::W<u32, super::GENCTRL>;
5#[doc = "Register GENCTRL[%s]
6`reset()`'s with value 0"]
7impl crate::ResetValue for super::GENCTRL {
8    type Type = u32;
9    #[inline(always)]
10    fn reset_value() -> Self::Type {
11        0
12    }
13}
14#[doc = "Source Select\n\nValue on reset: 0"]
15#[derive(Clone, Copy, Debug, PartialEq)]
16#[repr(u8)]
17pub enum SRC_A {
18    #[doc = "0: XOSC0 oscillator output"]
19    XOSC0 = 0,
20    #[doc = "1: XOSC1 oscillator output"]
21    XOSC1 = 1,
22    #[doc = "2: Generator input pad"]
23    GCLKIN = 2,
24    #[doc = "3: Generic clock generator 1 output"]
25    GCLKGEN1 = 3,
26    #[doc = "4: OSCULP32K oscillator output"]
27    OSCULP32K = 4,
28    #[doc = "5: XOSC32K oscillator output"]
29    XOSC32K = 5,
30    #[doc = "6: DFLL output"]
31    DFLL = 6,
32    #[doc = "7: DPLL0 output"]
33    DPLL0 = 7,
34    #[doc = "8: DPLL1 output"]
35    DPLL1 = 8,
36}
37impl From<SRC_A> for u8 {
38    #[inline(always)]
39    fn from(variant: SRC_A) -> Self {
40        variant as _
41    }
42}
43#[doc = "Reader of field `SRC`"]
44pub type SRC_R = crate::R<u8, SRC_A>;
45impl SRC_R {
46    #[doc = r"Get enumerated values variant"]
47    #[inline(always)]
48    pub fn variant(&self) -> crate::Variant<u8, SRC_A> {
49        use crate::Variant::*;
50        match self.bits {
51            0 => Val(SRC_A::XOSC0),
52            1 => Val(SRC_A::XOSC1),
53            2 => Val(SRC_A::GCLKIN),
54            3 => Val(SRC_A::GCLKGEN1),
55            4 => Val(SRC_A::OSCULP32K),
56            5 => Val(SRC_A::XOSC32K),
57            6 => Val(SRC_A::DFLL),
58            7 => Val(SRC_A::DPLL0),
59            8 => Val(SRC_A::DPLL1),
60            i => Res(i),
61        }
62    }
63    #[doc = "Checks if the value of the field is `XOSC0`"]
64    #[inline(always)]
65    pub fn is_xosc0(&self) -> bool {
66        *self == SRC_A::XOSC0
67    }
68    #[doc = "Checks if the value of the field is `XOSC1`"]
69    #[inline(always)]
70    pub fn is_xosc1(&self) -> bool {
71        *self == SRC_A::XOSC1
72    }
73    #[doc = "Checks if the value of the field is `GCLKIN`"]
74    #[inline(always)]
75    pub fn is_gclkin(&self) -> bool {
76        *self == SRC_A::GCLKIN
77    }
78    #[doc = "Checks if the value of the field is `GCLKGEN1`"]
79    #[inline(always)]
80    pub fn is_gclkgen1(&self) -> bool {
81        *self == SRC_A::GCLKGEN1
82    }
83    #[doc = "Checks if the value of the field is `OSCULP32K`"]
84    #[inline(always)]
85    pub fn is_osculp32k(&self) -> bool {
86        *self == SRC_A::OSCULP32K
87    }
88    #[doc = "Checks if the value of the field is `XOSC32K`"]
89    #[inline(always)]
90    pub fn is_xosc32k(&self) -> bool {
91        *self == SRC_A::XOSC32K
92    }
93    #[doc = "Checks if the value of the field is `DFLL`"]
94    #[inline(always)]
95    pub fn is_dfll(&self) -> bool {
96        *self == SRC_A::DFLL
97    }
98    #[doc = "Checks if the value of the field is `DPLL0`"]
99    #[inline(always)]
100    pub fn is_dpll0(&self) -> bool {
101        *self == SRC_A::DPLL0
102    }
103    #[doc = "Checks if the value of the field is `DPLL1`"]
104    #[inline(always)]
105    pub fn is_dpll1(&self) -> bool {
106        *self == SRC_A::DPLL1
107    }
108}
109#[doc = "Write proxy for field `SRC`"]
110pub struct SRC_W<'a> {
111    w: &'a mut W,
112}
113impl<'a> SRC_W<'a> {
114    #[doc = r"Writes `variant` to the field"]
115    #[inline(always)]
116    pub fn variant(self, variant: SRC_A) -> &'a mut W {
117        unsafe { self.bits(variant.into()) }
118    }
119    #[doc = "XOSC0 oscillator output"]
120    #[inline(always)]
121    pub fn xosc0(self) -> &'a mut W {
122        self.variant(SRC_A::XOSC0)
123    }
124    #[doc = "XOSC1 oscillator output"]
125    #[inline(always)]
126    pub fn xosc1(self) -> &'a mut W {
127        self.variant(SRC_A::XOSC1)
128    }
129    #[doc = "Generator input pad"]
130    #[inline(always)]
131    pub fn gclkin(self) -> &'a mut W {
132        self.variant(SRC_A::GCLKIN)
133    }
134    #[doc = "Generic clock generator 1 output"]
135    #[inline(always)]
136    pub fn gclkgen1(self) -> &'a mut W {
137        self.variant(SRC_A::GCLKGEN1)
138    }
139    #[doc = "OSCULP32K oscillator output"]
140    #[inline(always)]
141    pub fn osculp32k(self) -> &'a mut W {
142        self.variant(SRC_A::OSCULP32K)
143    }
144    #[doc = "XOSC32K oscillator output"]
145    #[inline(always)]
146    pub fn xosc32k(self) -> &'a mut W {
147        self.variant(SRC_A::XOSC32K)
148    }
149    #[doc = "DFLL output"]
150    #[inline(always)]
151    pub fn dfll(self) -> &'a mut W {
152        self.variant(SRC_A::DFLL)
153    }
154    #[doc = "DPLL0 output"]
155    #[inline(always)]
156    pub fn dpll0(self) -> &'a mut W {
157        self.variant(SRC_A::DPLL0)
158    }
159    #[doc = "DPLL1 output"]
160    #[inline(always)]
161    pub fn dpll1(self) -> &'a mut W {
162        self.variant(SRC_A::DPLL1)
163    }
164    #[doc = r"Writes raw bits to the field"]
165    #[inline(always)]
166    pub unsafe fn bits(self, value: u8) -> &'a mut W {
167        self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
168        self.w
169    }
170}
171#[doc = "Reader of field `GENEN`"]
172pub type GENEN_R = crate::R<bool, bool>;
173#[doc = "Write proxy for field `GENEN`"]
174pub struct GENEN_W<'a> {
175    w: &'a mut W,
176}
177impl<'a> GENEN_W<'a> {
178    #[doc = r"Sets the field bit"]
179    #[inline(always)]
180    pub fn set_bit(self) -> &'a mut W {
181        self.bit(true)
182    }
183    #[doc = r"Clears the field bit"]
184    #[inline(always)]
185    pub fn clear_bit(self) -> &'a mut W {
186        self.bit(false)
187    }
188    #[doc = r"Writes raw bits to the field"]
189    #[inline(always)]
190    pub fn bit(self, value: bool) -> &'a mut W {
191        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
192        self.w
193    }
194}
195#[doc = "Reader of field `IDC`"]
196pub type IDC_R = crate::R<bool, bool>;
197#[doc = "Write proxy for field `IDC`"]
198pub struct IDC_W<'a> {
199    w: &'a mut W,
200}
201impl<'a> IDC_W<'a> {
202    #[doc = r"Sets the field bit"]
203    #[inline(always)]
204    pub fn set_bit(self) -> &'a mut W {
205        self.bit(true)
206    }
207    #[doc = r"Clears the field bit"]
208    #[inline(always)]
209    pub fn clear_bit(self) -> &'a mut W {
210        self.bit(false)
211    }
212    #[doc = r"Writes raw bits to the field"]
213    #[inline(always)]
214    pub fn bit(self, value: bool) -> &'a mut W {
215        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
216        self.w
217    }
218}
219#[doc = "Reader of field `OOV`"]
220pub type OOV_R = crate::R<bool, bool>;
221#[doc = "Write proxy for field `OOV`"]
222pub struct OOV_W<'a> {
223    w: &'a mut W,
224}
225impl<'a> OOV_W<'a> {
226    #[doc = r"Sets the field bit"]
227    #[inline(always)]
228    pub fn set_bit(self) -> &'a mut W {
229        self.bit(true)
230    }
231    #[doc = r"Clears the field bit"]
232    #[inline(always)]
233    pub fn clear_bit(self) -> &'a mut W {
234        self.bit(false)
235    }
236    #[doc = r"Writes raw bits to the field"]
237    #[inline(always)]
238    pub fn bit(self, value: bool) -> &'a mut W {
239        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
240        self.w
241    }
242}
243#[doc = "Reader of field `OE`"]
244pub type OE_R = crate::R<bool, bool>;
245#[doc = "Write proxy for field `OE`"]
246pub struct OE_W<'a> {
247    w: &'a mut W,
248}
249impl<'a> OE_W<'a> {
250    #[doc = r"Sets the field bit"]
251    #[inline(always)]
252    pub fn set_bit(self) -> &'a mut W {
253        self.bit(true)
254    }
255    #[doc = r"Clears the field bit"]
256    #[inline(always)]
257    pub fn clear_bit(self) -> &'a mut W {
258        self.bit(false)
259    }
260    #[doc = r"Writes raw bits to the field"]
261    #[inline(always)]
262    pub fn bit(self, value: bool) -> &'a mut W {
263        self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
264        self.w
265    }
266}
267#[doc = "Divide Selection\n\nValue on reset: 0"]
268#[derive(Clone, Copy, Debug, PartialEq)]
269pub enum DIVSEL_A {
270    #[doc = "0: Divide input directly by divider factor"]
271    DIV1 = 0,
272    #[doc = "1: Divide input by 2^(divider factor+ 1)"]
273    DIV2 = 1,
274}
275impl From<DIVSEL_A> for bool {
276    #[inline(always)]
277    fn from(variant: DIVSEL_A) -> Self {
278        variant as u8 != 0
279    }
280}
281#[doc = "Reader of field `DIVSEL`"]
282pub type DIVSEL_R = crate::R<bool, DIVSEL_A>;
283impl DIVSEL_R {
284    #[doc = r"Get enumerated values variant"]
285    #[inline(always)]
286    pub fn variant(&self) -> DIVSEL_A {
287        match self.bits {
288            false => DIVSEL_A::DIV1,
289            true => DIVSEL_A::DIV2,
290        }
291    }
292    #[doc = "Checks if the value of the field is `DIV1`"]
293    #[inline(always)]
294    pub fn is_div1(&self) -> bool {
295        *self == DIVSEL_A::DIV1
296    }
297    #[doc = "Checks if the value of the field is `DIV2`"]
298    #[inline(always)]
299    pub fn is_div2(&self) -> bool {
300        *self == DIVSEL_A::DIV2
301    }
302}
303#[doc = "Write proxy for field `DIVSEL`"]
304pub struct DIVSEL_W<'a> {
305    w: &'a mut W,
306}
307impl<'a> DIVSEL_W<'a> {
308    #[doc = r"Writes `variant` to the field"]
309    #[inline(always)]
310    pub fn variant(self, variant: DIVSEL_A) -> &'a mut W {
311        {
312            self.bit(variant.into())
313        }
314    }
315    #[doc = "Divide input directly by divider factor"]
316    #[inline(always)]
317    pub fn div1(self) -> &'a mut W {
318        self.variant(DIVSEL_A::DIV1)
319    }
320    #[doc = "Divide input by 2^(divider factor+ 1)"]
321    #[inline(always)]
322    pub fn div2(self) -> &'a mut W {
323        self.variant(DIVSEL_A::DIV2)
324    }
325    #[doc = r"Sets the field bit"]
326    #[inline(always)]
327    pub fn set_bit(self) -> &'a mut W {
328        self.bit(true)
329    }
330    #[doc = r"Clears the field bit"]
331    #[inline(always)]
332    pub fn clear_bit(self) -> &'a mut W {
333        self.bit(false)
334    }
335    #[doc = r"Writes raw bits to the field"]
336    #[inline(always)]
337    pub fn bit(self, value: bool) -> &'a mut W {
338        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
339        self.w
340    }
341}
342#[doc = "Reader of field `RUNSTDBY`"]
343pub type RUNSTDBY_R = crate::R<bool, bool>;
344#[doc = "Write proxy for field `RUNSTDBY`"]
345pub struct RUNSTDBY_W<'a> {
346    w: &'a mut W,
347}
348impl<'a> RUNSTDBY_W<'a> {
349    #[doc = r"Sets the field bit"]
350    #[inline(always)]
351    pub fn set_bit(self) -> &'a mut W {
352        self.bit(true)
353    }
354    #[doc = r"Clears the field bit"]
355    #[inline(always)]
356    pub fn clear_bit(self) -> &'a mut W {
357        self.bit(false)
358    }
359    #[doc = r"Writes raw bits to the field"]
360    #[inline(always)]
361    pub fn bit(self, value: bool) -> &'a mut W {
362        self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
363        self.w
364    }
365}
366#[doc = "Reader of field `DIV`"]
367pub type DIV_R = crate::R<u16, u16>;
368#[doc = "Write proxy for field `DIV`"]
369pub struct DIV_W<'a> {
370    w: &'a mut W,
371}
372impl<'a> DIV_W<'a> {
373    #[doc = r"Writes raw bits to the field"]
374    #[inline(always)]
375    pub unsafe fn bits(self, value: u16) -> &'a mut W {
376        self.w.bits = (self.w.bits & !(0xffff << 16)) | (((value as u32) & 0xffff) << 16);
377        self.w
378    }
379}
380impl R {
381    #[doc = "Bits 0:3 - Source Select"]
382    #[inline(always)]
383    pub fn src(&self) -> SRC_R {
384        SRC_R::new((self.bits & 0x0f) as u8)
385    }
386    #[doc = "Bit 8 - Generic Clock Generator Enable"]
387    #[inline(always)]
388    pub fn genen(&self) -> GENEN_R {
389        GENEN_R::new(((self.bits >> 8) & 0x01) != 0)
390    }
391    #[doc = "Bit 9 - Improve Duty Cycle"]
392    #[inline(always)]
393    pub fn idc(&self) -> IDC_R {
394        IDC_R::new(((self.bits >> 9) & 0x01) != 0)
395    }
396    #[doc = "Bit 10 - Output Off Value"]
397    #[inline(always)]
398    pub fn oov(&self) -> OOV_R {
399        OOV_R::new(((self.bits >> 10) & 0x01) != 0)
400    }
401    #[doc = "Bit 11 - Output Enable"]
402    #[inline(always)]
403    pub fn oe(&self) -> OE_R {
404        OE_R::new(((self.bits >> 11) & 0x01) != 0)
405    }
406    #[doc = "Bit 12 - Divide Selection"]
407    #[inline(always)]
408    pub fn divsel(&self) -> DIVSEL_R {
409        DIVSEL_R::new(((self.bits >> 12) & 0x01) != 0)
410    }
411    #[doc = "Bit 13 - Run in Standby"]
412    #[inline(always)]
413    pub fn runstdby(&self) -> RUNSTDBY_R {
414        RUNSTDBY_R::new(((self.bits >> 13) & 0x01) != 0)
415    }
416    #[doc = "Bits 16:31 - Division Factor"]
417    #[inline(always)]
418    pub fn div(&self) -> DIV_R {
419        DIV_R::new(((self.bits >> 16) & 0xffff) as u16)
420    }
421}
422impl W {
423    #[doc = "Bits 0:3 - Source Select"]
424    #[inline(always)]
425    pub fn src(&mut self) -> SRC_W {
426        SRC_W { w: self }
427    }
428    #[doc = "Bit 8 - Generic Clock Generator Enable"]
429    #[inline(always)]
430    pub fn genen(&mut self) -> GENEN_W {
431        GENEN_W { w: self }
432    }
433    #[doc = "Bit 9 - Improve Duty Cycle"]
434    #[inline(always)]
435    pub fn idc(&mut self) -> IDC_W {
436        IDC_W { w: self }
437    }
438    #[doc = "Bit 10 - Output Off Value"]
439    #[inline(always)]
440    pub fn oov(&mut self) -> OOV_W {
441        OOV_W { w: self }
442    }
443    #[doc = "Bit 11 - Output Enable"]
444    #[inline(always)]
445    pub fn oe(&mut self) -> OE_W {
446        OE_W { w: self }
447    }
448    #[doc = "Bit 12 - Divide Selection"]
449    #[inline(always)]
450    pub fn divsel(&mut self) -> DIVSEL_W {
451        DIVSEL_W { w: self }
452    }
453    #[doc = "Bit 13 - Run in Standby"]
454    #[inline(always)]
455    pub fn runstdby(&mut self) -> RUNSTDBY_W {
456        RUNSTDBY_W { w: self }
457    }
458    #[doc = "Bits 16:31 - Division Factor"]
459    #[inline(always)]
460    pub fn div(&mut self) -> DIV_W {
461        DIV_W { w: self }
462    }
463}
atsamd51j19a/gclk/genctrl.rs

atsamd51j19a/gclk/
genctrl.rs
