1#[doc = "Reader of register CLKCTRL"]
2pub type R = crate::R<u16, super::CLKCTRL>;
3#[doc = "Writer for register CLKCTRL"]
4pub type W = crate::W<u16, super::CLKCTRL>;
5#[doc = "Register CLKCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CLKCTRL {
7 type Type = u16;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Generic Clock Selection ID\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15#[repr(u8)]
16pub enum ID_A {
17 #[doc = "0: DFLL48"]
18 DFLL48 = 0,
19 #[doc = "1: FDPLL"]
20 FDPLL = 1,
21 #[doc = "2: FDPLL32K"]
22 FDPLL32K = 2,
23 #[doc = "3: WDT"]
24 WDT = 3,
25 #[doc = "4: RTC"]
26 RTC = 4,
27 #[doc = "5: EIC"]
28 EIC = 5,
29 #[doc = "6: USB"]
30 USB = 6,
31 #[doc = "7: EVSYS_0"]
32 EVSYS_0 = 7,
33 #[doc = "8: EVSYS_1"]
34 EVSYS_1 = 8,
35 #[doc = "9: EVSYS_2"]
36 EVSYS_2 = 9,
37 #[doc = "10: EVSYS_3"]
38 EVSYS_3 = 10,
39 #[doc = "11: EVSYS_4"]
40 EVSYS_4 = 11,
41 #[doc = "12: EVSYS_5"]
42 EVSYS_5 = 12,
43 #[doc = "13: EVSYS_6"]
44 EVSYS_6 = 13,
45 #[doc = "14: EVSYS_7"]
46 EVSYS_7 = 14,
47 #[doc = "15: EVSYS_8"]
48 EVSYS_8 = 15,
49 #[doc = "16: EVSYS_9"]
50 EVSYS_9 = 16,
51 #[doc = "17: EVSYS_10"]
52 EVSYS_10 = 17,
53 #[doc = "18: EVSYS_11"]
54 EVSYS_11 = 18,
55 #[doc = "19: SERCOMX_SLOW"]
56 SERCOMX_SLOW = 19,
57 #[doc = "20: SERCOM0_CORE"]
58 SERCOM0_CORE = 20,
59 #[doc = "21: SERCOM1_CORE"]
60 SERCOM1_CORE = 21,
61 #[doc = "22: SERCOM2_CORE"]
62 SERCOM2_CORE = 22,
63 #[doc = "23: SERCOM3_CORE"]
64 SERCOM3_CORE = 23,
65 #[doc = "24: SERCOM4_CORE"]
66 SERCOM4_CORE = 24,
67 #[doc = "25: SERCOM5_CORE"]
68 SERCOM5_CORE = 25,
69 #[doc = "26: TCC0_TCC1"]
70 TCC0_TCC1 = 26,
71 #[doc = "27: TCC2_TC3"]
72 TCC2_TC3 = 27,
73 #[doc = "28: TC4_TC5"]
74 TC4_TC5 = 28,
75 #[doc = "29: TC6_TC7"]
76 TC6_TC7 = 29,
77 #[doc = "30: ADC"]
78 ADC = 30,
79 #[doc = "31: AC_DIG"]
80 AC_DIG = 31,
81 #[doc = "32: AC_ANA"]
82 AC_ANA = 32,
83 #[doc = "33: DAC"]
84 DAC = 33,
85 #[doc = "35: I2S_0"]
86 I2S_0 = 35,
87 #[doc = "36: I2S_1"]
88 I2S_1 = 36,
89}
90impl From<ID_A> for u8 {
91 #[inline(always)]
92 fn from(variant: ID_A) -> Self {
93 variant as _
94 }
95}
96#[doc = "Reader of field `ID`"]
97pub type ID_R = crate::R<u8, ID_A>;
98impl ID_R {
99 #[doc = r"Get enumerated values variant"]
100 #[inline(always)]
101 pub fn variant(&self) -> crate::Variant<u8, ID_A> {
102 use crate::Variant::*;
103 match self.bits {
104 0 => Val(ID_A::DFLL48),
105 1 => Val(ID_A::FDPLL),
106 2 => Val(ID_A::FDPLL32K),
107 3 => Val(ID_A::WDT),
108 4 => Val(ID_A::RTC),
109 5 => Val(ID_A::EIC),
110 6 => Val(ID_A::USB),
111 7 => Val(ID_A::EVSYS_0),
112 8 => Val(ID_A::EVSYS_1),
113 9 => Val(ID_A::EVSYS_2),
114 10 => Val(ID_A::EVSYS_3),
115 11 => Val(ID_A::EVSYS_4),
116 12 => Val(ID_A::EVSYS_5),
117 13 => Val(ID_A::EVSYS_6),
118 14 => Val(ID_A::EVSYS_7),
119 15 => Val(ID_A::EVSYS_8),
120 16 => Val(ID_A::EVSYS_9),
121 17 => Val(ID_A::EVSYS_10),
122 18 => Val(ID_A::EVSYS_11),
123 19 => Val(ID_A::SERCOMX_SLOW),
124 20 => Val(ID_A::SERCOM0_CORE),
125 21 => Val(ID_A::SERCOM1_CORE),
126 22 => Val(ID_A::SERCOM2_CORE),
127 23 => Val(ID_A::SERCOM3_CORE),
128 24 => Val(ID_A::SERCOM4_CORE),
129 25 => Val(ID_A::SERCOM5_CORE),
130 26 => Val(ID_A::TCC0_TCC1),
131 27 => Val(ID_A::TCC2_TC3),
132 28 => Val(ID_A::TC4_TC5),
133 29 => Val(ID_A::TC6_TC7),
134 30 => Val(ID_A::ADC),
135 31 => Val(ID_A::AC_DIG),
136 32 => Val(ID_A::AC_ANA),
137 33 => Val(ID_A::DAC),
138 35 => Val(ID_A::I2S_0),
139 36 => Val(ID_A::I2S_1),
140 i => Res(i),
141 }
142 }
143 #[doc = "Checks if the value of the field is `DFLL48`"]
144 #[inline(always)]
145 pub fn is_dfll48(&self) -> bool {
146 *self == ID_A::DFLL48
147 }
148 #[doc = "Checks if the value of the field is `FDPLL`"]
149 #[inline(always)]
150 pub fn is_fdpll(&self) -> bool {
151 *self == ID_A::FDPLL
152 }
153 #[doc = "Checks if the value of the field is `FDPLL32K`"]
154 #[inline(always)]
155 pub fn is_fdpll32k(&self) -> bool {
156 *self == ID_A::FDPLL32K
157 }
158 #[doc = "Checks if the value of the field is `WDT`"]
159 #[inline(always)]
160 pub fn is_wdt(&self) -> bool {
161 *self == ID_A::WDT
162 }
163 #[doc = "Checks if the value of the field is `RTC`"]
164 #[inline(always)]
165 pub fn is_rtc(&self) -> bool {
166 *self == ID_A::RTC
167 }
168 #[doc = "Checks if the value of the field is `EIC`"]
169 #[inline(always)]
170 pub fn is_eic(&self) -> bool {
171 *self == ID_A::EIC
172 }
173 #[doc = "Checks if the value of the field is `USB`"]
174 #[inline(always)]
175 pub fn is_usb(&self) -> bool {
176 *self == ID_A::USB
177 }
178 #[doc = "Checks if the value of the field is `EVSYS_0`"]
179 #[inline(always)]
180 pub fn is_evsys_0(&self) -> bool {
181 *self == ID_A::EVSYS_0
182 }
183 #[doc = "Checks if the value of the field is `EVSYS_1`"]
184 #[inline(always)]
185 pub fn is_evsys_1(&self) -> bool {
186 *self == ID_A::EVSYS_1
187 }
188 #[doc = "Checks if the value of the field is `EVSYS_2`"]
189 #[inline(always)]
190 pub fn is_evsys_2(&self) -> bool {
191 *self == ID_A::EVSYS_2
192 }
193 #[doc = "Checks if the value of the field is `EVSYS_3`"]
194 #[inline(always)]
195 pub fn is_evsys_3(&self) -> bool {
196 *self == ID_A::EVSYS_3
197 }
198 #[doc = "Checks if the value of the field is `EVSYS_4`"]
199 #[inline(always)]
200 pub fn is_evsys_4(&self) -> bool {
201 *self == ID_A::EVSYS_4
202 }
203 #[doc = "Checks if the value of the field is `EVSYS_5`"]
204 #[inline(always)]
205 pub fn is_evsys_5(&self) -> bool {
206 *self == ID_A::EVSYS_5
207 }
208 #[doc = "Checks if the value of the field is `EVSYS_6`"]
209 #[inline(always)]
210 pub fn is_evsys_6(&self) -> bool {
211 *self == ID_A::EVSYS_6
212 }
213 #[doc = "Checks if the value of the field is `EVSYS_7`"]
214 #[inline(always)]
215 pub fn is_evsys_7(&self) -> bool {
216 *self == ID_A::EVSYS_7
217 }
218 #[doc = "Checks if the value of the field is `EVSYS_8`"]
219 #[inline(always)]
220 pub fn is_evsys_8(&self) -> bool {
221 *self == ID_A::EVSYS_8
222 }
223 #[doc = "Checks if the value of the field is `EVSYS_9`"]
224 #[inline(always)]
225 pub fn is_evsys_9(&self) -> bool {
226 *self == ID_A::EVSYS_9
227 }
228 #[doc = "Checks if the value of the field is `EVSYS_10`"]
229 #[inline(always)]
230 pub fn is_evsys_10(&self) -> bool {
231 *self == ID_A::EVSYS_10
232 }
233 #[doc = "Checks if the value of the field is `EVSYS_11`"]
234 #[inline(always)]
235 pub fn is_evsys_11(&self) -> bool {
236 *self == ID_A::EVSYS_11
237 }
238 #[doc = "Checks if the value of the field is `SERCOMX_SLOW`"]
239 #[inline(always)]
240 pub fn is_sercomx_slow(&self) -> bool {
241 *self == ID_A::SERCOMX_SLOW
242 }
243 #[doc = "Checks if the value of the field is `SERCOM0_CORE`"]
244 #[inline(always)]
245 pub fn is_sercom0_core(&self) -> bool {
246 *self == ID_A::SERCOM0_CORE
247 }
248 #[doc = "Checks if the value of the field is `SERCOM1_CORE`"]
249 #[inline(always)]
250 pub fn is_sercom1_core(&self) -> bool {
251 *self == ID_A::SERCOM1_CORE
252 }
253 #[doc = "Checks if the value of the field is `SERCOM2_CORE`"]
254 #[inline(always)]
255 pub fn is_sercom2_core(&self) -> bool {
256 *self == ID_A::SERCOM2_CORE
257 }
258 #[doc = "Checks if the value of the field is `SERCOM3_CORE`"]
259 #[inline(always)]
260 pub fn is_sercom3_core(&self) -> bool {
261 *self == ID_A::SERCOM3_CORE
262 }
263 #[doc = "Checks if the value of the field is `SERCOM4_CORE`"]
264 #[inline(always)]
265 pub fn is_sercom4_core(&self) -> bool {
266 *self == ID_A::SERCOM4_CORE
267 }
268 #[doc = "Checks if the value of the field is `SERCOM5_CORE`"]
269 #[inline(always)]
270 pub fn is_sercom5_core(&self) -> bool {
271 *self == ID_A::SERCOM5_CORE
272 }
273 #[doc = "Checks if the value of the field is `TCC0_TCC1`"]
274 #[inline(always)]
275 pub fn is_tcc0_tcc1(&self) -> bool {
276 *self == ID_A::TCC0_TCC1
277 }
278 #[doc = "Checks if the value of the field is `TCC2_TC3`"]
279 #[inline(always)]
280 pub fn is_tcc2_tc3(&self) -> bool {
281 *self == ID_A::TCC2_TC3
282 }
283 #[doc = "Checks if the value of the field is `TC4_TC5`"]
284 #[inline(always)]
285 pub fn is_tc4_tc5(&self) -> bool {
286 *self == ID_A::TC4_TC5
287 }
288 #[doc = "Checks if the value of the field is `TC6_TC7`"]
289 #[inline(always)]
290 pub fn is_tc6_tc7(&self) -> bool {
291 *self == ID_A::TC6_TC7
292 }
293 #[doc = "Checks if the value of the field is `ADC`"]
294 #[inline(always)]
295 pub fn is_adc(&self) -> bool {
296 *self == ID_A::ADC
297 }
298 #[doc = "Checks if the value of the field is `AC_DIG`"]
299 #[inline(always)]
300 pub fn is_ac_dig(&self) -> bool {
301 *self == ID_A::AC_DIG
302 }
303 #[doc = "Checks if the value of the field is `AC_ANA`"]
304 #[inline(always)]
305 pub fn is_ac_ana(&self) -> bool {
306 *self == ID_A::AC_ANA
307 }
308 #[doc = "Checks if the value of the field is `DAC`"]
309 #[inline(always)]
310 pub fn is_dac(&self) -> bool {
311 *self == ID_A::DAC
312 }
313 #[doc = "Checks if the value of the field is `I2S_0`"]
314 #[inline(always)]
315 pub fn is_i2s_0(&self) -> bool {
316 *self == ID_A::I2S_0
317 }
318 #[doc = "Checks if the value of the field is `I2S_1`"]
319 #[inline(always)]
320 pub fn is_i2s_1(&self) -> bool {
321 *self == ID_A::I2S_1
322 }
323}
324#[doc = "Write proxy for field `ID`"]
325pub struct ID_W<'a> {
326 w: &'a mut W,
327}
328impl<'a> ID_W<'a> {
329 #[doc = r"Writes `variant` to the field"]
330 #[inline(always)]
331 pub fn variant(self, variant: ID_A) -> &'a mut W {
332 unsafe { self.bits(variant.into()) }
333 }
334 #[doc = "DFLL48"]
335 #[inline(always)]
336 pub fn dfll48(self) -> &'a mut W {
337 self.variant(ID_A::DFLL48)
338 }
339 #[doc = "FDPLL"]
340 #[inline(always)]
341 pub fn fdpll(self) -> &'a mut W {
342 self.variant(ID_A::FDPLL)
343 }
344 #[doc = "FDPLL32K"]
345 #[inline(always)]
346 pub fn fdpll32k(self) -> &'a mut W {
347 self.variant(ID_A::FDPLL32K)
348 }
349 #[doc = "WDT"]
350 #[inline(always)]
351 pub fn wdt(self) -> &'a mut W {
352 self.variant(ID_A::WDT)
353 }
354 #[doc = "RTC"]
355 #[inline(always)]
356 pub fn rtc(self) -> &'a mut W {
357 self.variant(ID_A::RTC)
358 }
359 #[doc = "EIC"]
360 #[inline(always)]
361 pub fn eic(self) -> &'a mut W {
362 self.variant(ID_A::EIC)
363 }
364 #[doc = "USB"]
365 #[inline(always)]
366 pub fn usb(self) -> &'a mut W {
367 self.variant(ID_A::USB)
368 }
369 #[doc = "EVSYS_0"]
370 #[inline(always)]
371 pub fn evsys_0(self) -> &'a mut W {
372 self.variant(ID_A::EVSYS_0)
373 }
374 #[doc = "EVSYS_1"]
375 #[inline(always)]
376 pub fn evsys_1(self) -> &'a mut W {
377 self.variant(ID_A::EVSYS_1)
378 }
379 #[doc = "EVSYS_2"]
380 #[inline(always)]
381 pub fn evsys_2(self) -> &'a mut W {
382 self.variant(ID_A::EVSYS_2)
383 }
384 #[doc = "EVSYS_3"]
385 #[inline(always)]
386 pub fn evsys_3(self) -> &'a mut W {
387 self.variant(ID_A::EVSYS_3)
388 }
389 #[doc = "EVSYS_4"]
390 #[inline(always)]
391 pub fn evsys_4(self) -> &'a mut W {
392 self.variant(ID_A::EVSYS_4)
393 }
394 #[doc = "EVSYS_5"]
395 #[inline(always)]
396 pub fn evsys_5(self) -> &'a mut W {
397 self.variant(ID_A::EVSYS_5)
398 }
399 #[doc = "EVSYS_6"]
400 #[inline(always)]
401 pub fn evsys_6(self) -> &'a mut W {
402 self.variant(ID_A::EVSYS_6)
403 }
404 #[doc = "EVSYS_7"]
405 #[inline(always)]
406 pub fn evsys_7(self) -> &'a mut W {
407 self.variant(ID_A::EVSYS_7)
408 }
409 #[doc = "EVSYS_8"]
410 #[inline(always)]
411 pub fn evsys_8(self) -> &'a mut W {
412 self.variant(ID_A::EVSYS_8)
413 }
414 #[doc = "EVSYS_9"]
415 #[inline(always)]
416 pub fn evsys_9(self) -> &'a mut W {
417 self.variant(ID_A::EVSYS_9)
418 }
419 #[doc = "EVSYS_10"]
420 #[inline(always)]
421 pub fn evsys_10(self) -> &'a mut W {
422 self.variant(ID_A::EVSYS_10)
423 }
424 #[doc = "EVSYS_11"]
425 #[inline(always)]
426 pub fn evsys_11(self) -> &'a mut W {
427 self.variant(ID_A::EVSYS_11)
428 }
429 #[doc = "SERCOMX_SLOW"]
430 #[inline(always)]
431 pub fn sercomx_slow(self) -> &'a mut W {
432 self.variant(ID_A::SERCOMX_SLOW)
433 }
434 #[doc = "SERCOM0_CORE"]
435 #[inline(always)]
436 pub fn sercom0_core(self) -> &'a mut W {
437 self.variant(ID_A::SERCOM0_CORE)
438 }
439 #[doc = "SERCOM1_CORE"]
440 #[inline(always)]
441 pub fn sercom1_core(self) -> &'a mut W {
442 self.variant(ID_A::SERCOM1_CORE)
443 }
444 #[doc = "SERCOM2_CORE"]
445 #[inline(always)]
446 pub fn sercom2_core(self) -> &'a mut W {
447 self.variant(ID_A::SERCOM2_CORE)
448 }
449 #[doc = "SERCOM3_CORE"]
450 #[inline(always)]
451 pub fn sercom3_core(self) -> &'a mut W {
452 self.variant(ID_A::SERCOM3_CORE)
453 }
454 #[doc = "SERCOM4_CORE"]
455 #[inline(always)]
456 pub fn sercom4_core(self) -> &'a mut W {
457 self.variant(ID_A::SERCOM4_CORE)
458 }
459 #[doc = "SERCOM5_CORE"]
460 #[inline(always)]
461 pub fn sercom5_core(self) -> &'a mut W {
462 self.variant(ID_A::SERCOM5_CORE)
463 }
464 #[doc = "TCC0_TCC1"]
465 #[inline(always)]
466 pub fn tcc0_tcc1(self) -> &'a mut W {
467 self.variant(ID_A::TCC0_TCC1)
468 }
469 #[doc = "TCC2_TC3"]
470 #[inline(always)]
471 pub fn tcc2_tc3(self) -> &'a mut W {
472 self.variant(ID_A::TCC2_TC3)
473 }
474 #[doc = "TC4_TC5"]
475 #[inline(always)]
476 pub fn tc4_tc5(self) -> &'a mut W {
477 self.variant(ID_A::TC4_TC5)
478 }
479 #[doc = "TC6_TC7"]
480 #[inline(always)]
481 pub fn tc6_tc7(self) -> &'a mut W {
482 self.variant(ID_A::TC6_TC7)
483 }
484 #[doc = "ADC"]
485 #[inline(always)]
486 pub fn adc(self) -> &'a mut W {
487 self.variant(ID_A::ADC)
488 }
489 #[doc = "AC_DIG"]
490 #[inline(always)]
491 pub fn ac_dig(self) -> &'a mut W {
492 self.variant(ID_A::AC_DIG)
493 }
494 #[doc = "AC_ANA"]
495 #[inline(always)]
496 pub fn ac_ana(self) -> &'a mut W {
497 self.variant(ID_A::AC_ANA)
498 }
499 #[doc = "DAC"]
500 #[inline(always)]
501 pub fn dac(self) -> &'a mut W {
502 self.variant(ID_A::DAC)
503 }
504 #[doc = "I2S_0"]
505 #[inline(always)]
506 pub fn i2s_0(self) -> &'a mut W {
507 self.variant(ID_A::I2S_0)
508 }
509 #[doc = "I2S_1"]
510 #[inline(always)]
511 pub fn i2s_1(self) -> &'a mut W {
512 self.variant(ID_A::I2S_1)
513 }
514 #[doc = r"Writes raw bits to the field"]
515 #[inline(always)]
516 pub unsafe fn bits(self, value: u8) -> &'a mut W {
517 self.w.bits = (self.w.bits & !0x3f) | ((value as u16) & 0x3f);
518 self.w
519 }
520}
521#[doc = "Generic Clock Generator\n\nValue on reset: 0"]
522#[derive(Clone, Copy, Debug, PartialEq)]
523#[repr(u8)]
524pub enum GEN_A {
525 #[doc = "0: Generic clock generator 0"]
526 GCLK0 = 0,
527 #[doc = "1: Generic clock generator 1"]
528 GCLK1 = 1,
529 #[doc = "2: Generic clock generator 2"]
530 GCLK2 = 2,
531 #[doc = "3: Generic clock generator 3"]
532 GCLK3 = 3,
533 #[doc = "4: Generic clock generator 4"]
534 GCLK4 = 4,
535 #[doc = "5: Generic clock generator 5"]
536 GCLK5 = 5,
537 #[doc = "6: Generic clock generator 6"]
538 GCLK6 = 6,
539 #[doc = "7: Generic clock generator 7"]
540 GCLK7 = 7,
541 #[doc = "8: Generic clock generator 8"]
542 GCLK8 = 8,
543}
544impl From<GEN_A> for u8 {
545 #[inline(always)]
546 fn from(variant: GEN_A) -> Self {
547 variant as _
548 }
549}
550#[doc = "Reader of field `GEN`"]
551pub type GEN_R = crate::R<u8, GEN_A>;
552impl GEN_R {
553 #[doc = r"Get enumerated values variant"]
554 #[inline(always)]
555 pub fn variant(&self) -> crate::Variant<u8, GEN_A> {
556 use crate::Variant::*;
557 match self.bits {
558 0 => Val(GEN_A::GCLK0),
559 1 => Val(GEN_A::GCLK1),
560 2 => Val(GEN_A::GCLK2),
561 3 => Val(GEN_A::GCLK3),
562 4 => Val(GEN_A::GCLK4),
563 5 => Val(GEN_A::GCLK5),
564 6 => Val(GEN_A::GCLK6),
565 7 => Val(GEN_A::GCLK7),
566 8 => Val(GEN_A::GCLK8),
567 i => Res(i),
568 }
569 }
570 #[doc = "Checks if the value of the field is `GCLK0`"]
571 #[inline(always)]
572 pub fn is_gclk0(&self) -> bool {
573 *self == GEN_A::GCLK0
574 }
575 #[doc = "Checks if the value of the field is `GCLK1`"]
576 #[inline(always)]
577 pub fn is_gclk1(&self) -> bool {
578 *self == GEN_A::GCLK1
579 }
580 #[doc = "Checks if the value of the field is `GCLK2`"]
581 #[inline(always)]
582 pub fn is_gclk2(&self) -> bool {
583 *self == GEN_A::GCLK2
584 }
585 #[doc = "Checks if the value of the field is `GCLK3`"]
586 #[inline(always)]
587 pub fn is_gclk3(&self) -> bool {
588 *self == GEN_A::GCLK3
589 }
590 #[doc = "Checks if the value of the field is `GCLK4`"]
591 #[inline(always)]
592 pub fn is_gclk4(&self) -> bool {
593 *self == GEN_A::GCLK4
594 }
595 #[doc = "Checks if the value of the field is `GCLK5`"]
596 #[inline(always)]
597 pub fn is_gclk5(&self) -> bool {
598 *self == GEN_A::GCLK5
599 }
600 #[doc = "Checks if the value of the field is `GCLK6`"]
601 #[inline(always)]
602 pub fn is_gclk6(&self) -> bool {
603 *self == GEN_A::GCLK6
604 }
605 #[doc = "Checks if the value of the field is `GCLK7`"]
606 #[inline(always)]
607 pub fn is_gclk7(&self) -> bool {
608 *self == GEN_A::GCLK7
609 }
610 #[doc = "Checks if the value of the field is `GCLK8`"]
611 #[inline(always)]
612 pub fn is_gclk8(&self) -> bool {
613 *self == GEN_A::GCLK8
614 }
615}
616#[doc = "Write proxy for field `GEN`"]
617pub struct GEN_W<'a> {
618 w: &'a mut W,
619}
620impl<'a> GEN_W<'a> {
621 #[doc = r"Writes `variant` to the field"]
622 #[inline(always)]
623 pub fn variant(self, variant: GEN_A) -> &'a mut W {
624 unsafe { self.bits(variant.into()) }
625 }
626 #[doc = "Generic clock generator 0"]
627 #[inline(always)]
628 pub fn gclk0(self) -> &'a mut W {
629 self.variant(GEN_A::GCLK0)
630 }
631 #[doc = "Generic clock generator 1"]
632 #[inline(always)]
633 pub fn gclk1(self) -> &'a mut W {
634 self.variant(GEN_A::GCLK1)
635 }
636 #[doc = "Generic clock generator 2"]
637 #[inline(always)]
638 pub fn gclk2(self) -> &'a mut W {
639 self.variant(GEN_A::GCLK2)
640 }
641 #[doc = "Generic clock generator 3"]
642 #[inline(always)]
643 pub fn gclk3(self) -> &'a mut W {
644 self.variant(GEN_A::GCLK3)
645 }
646 #[doc = "Generic clock generator 4"]
647 #[inline(always)]
648 pub fn gclk4(self) -> &'a mut W {
649 self.variant(GEN_A::GCLK4)
650 }
651 #[doc = "Generic clock generator 5"]
652 #[inline(always)]
653 pub fn gclk5(self) -> &'a mut W {
654 self.variant(GEN_A::GCLK5)
655 }
656 #[doc = "Generic clock generator 6"]
657 #[inline(always)]
658 pub fn gclk6(self) -> &'a mut W {
659 self.variant(GEN_A::GCLK6)
660 }
661 #[doc = "Generic clock generator 7"]
662 #[inline(always)]
663 pub fn gclk7(self) -> &'a mut W {
664 self.variant(GEN_A::GCLK7)
665 }
666 #[doc = "Generic clock generator 8"]
667 #[inline(always)]
668 pub fn gclk8(self) -> &'a mut W {
669 self.variant(GEN_A::GCLK8)
670 }
671 #[doc = r"Writes raw bits to the field"]
672 #[inline(always)]
673 pub unsafe fn bits(self, value: u8) -> &'a mut W {
674 self.w.bits = (self.w.bits & !(0x0f << 8)) | (((value as u16) & 0x0f) << 8);
675 self.w
676 }
677}
678#[doc = "Reader of field `CLKEN`"]
679pub type CLKEN_R = crate::R<bool, bool>;
680#[doc = "Write proxy for field `CLKEN`"]
681pub struct CLKEN_W<'a> {
682 w: &'a mut W,
683}
684impl<'a> CLKEN_W<'a> {
685 #[doc = r"Sets the field bit"]
686 #[inline(always)]
687 pub fn set_bit(self) -> &'a mut W {
688 self.bit(true)
689 }
690 #[doc = r"Clears the field bit"]
691 #[inline(always)]
692 pub fn clear_bit(self) -> &'a mut W {
693 self.bit(false)
694 }
695 #[doc = r"Writes raw bits to the field"]
696 #[inline(always)]
697 pub fn bit(self, value: bool) -> &'a mut W {
698 self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u16) & 0x01) << 14);
699 self.w
700 }
701}
702#[doc = "Reader of field `WRTLOCK`"]
703pub type WRTLOCK_R = crate::R<bool, bool>;
704#[doc = "Write proxy for field `WRTLOCK`"]
705pub struct WRTLOCK_W<'a> {
706 w: &'a mut W,
707}
708impl<'a> WRTLOCK_W<'a> {
709 #[doc = r"Sets the field bit"]
710 #[inline(always)]
711 pub fn set_bit(self) -> &'a mut W {
712 self.bit(true)
713 }
714 #[doc = r"Clears the field bit"]
715 #[inline(always)]
716 pub fn clear_bit(self) -> &'a mut W {
717 self.bit(false)
718 }
719 #[doc = r"Writes raw bits to the field"]
720 #[inline(always)]
721 pub fn bit(self, value: bool) -> &'a mut W {
722 self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u16) & 0x01) << 15);
723 self.w
724 }
725}
726impl R {
727 #[doc = "Bits 0:5 - Generic Clock Selection ID"]
728 #[inline(always)]
729 pub fn id(&self) -> ID_R {
730 ID_R::new((self.bits & 0x3f) as u8)
731 }
732 #[doc = "Bits 8:11 - Generic Clock Generator"]
733 #[inline(always)]
734 pub fn gen(&self) -> GEN_R {
735 GEN_R::new(((self.bits >> 8) & 0x0f) as u8)
736 }
737 #[doc = "Bit 14 - Clock Enable"]
738 #[inline(always)]
739 pub fn clken(&self) -> CLKEN_R {
740 CLKEN_R::new(((self.bits >> 14) & 0x01) != 0)
741 }
742 #[doc = "Bit 15 - Write Lock"]
743 #[inline(always)]
744 pub fn wrtlock(&self) -> WRTLOCK_R {
745 WRTLOCK_R::new(((self.bits >> 15) & 0x01) != 0)
746 }
747}
748impl W {
749 #[doc = "Bits 0:5 - Generic Clock Selection ID"]
750 #[inline(always)]
751 pub fn id(&mut self) -> ID_W {
752 ID_W { w: self }
753 }
754 #[doc = "Bits 8:11 - Generic Clock Generator"]
755 #[inline(always)]
756 pub fn gen(&mut self) -> GEN_W {
757 GEN_W { w: self }
758 }
759 #[doc = "Bit 14 - Clock Enable"]
760 #[inline(always)]
761 pub fn clken(&mut self) -> CLKEN_W {
762 CLKEN_W { w: self }
763 }
764 #[doc = "Bit 15 - Write Lock"]
765 #[inline(always)]
766 pub fn wrtlock(&mut self) -> WRTLOCK_W {
767 WRTLOCK_W { w: self }
768 }
769}