atsamd21e18a/tcc0/
cc_dith4.rs

1#[doc = "Reader of register CC%s_DITH4"]
2pub type R = crate::R<u32, super::CC_DITH4>;
3#[doc = "Writer for register CC%s_DITH4"]
4pub type W = crate::W<u32, super::CC_DITH4>;
5#[doc = "Register CC%s_DITH4 `reset()`'s with value 0"]
6impl crate::ResetValue for super::CC_DITH4 {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DITHERCY`"]
14pub type DITHERCY_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `DITHERCY`"]
16pub struct DITHERCY_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DITHERCY_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
24        self.w
25    }
26}
27#[doc = "Reader of field `CC`"]
28pub type CC_R = crate::R<u32, u32>;
29#[doc = "Write proxy for field `CC`"]
30pub struct CC_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> CC_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u32) -> &'a mut W {
37        self.w.bits = (self.w.bits & !(0x000f_ffff << 4)) | (((value as u32) & 0x000f_ffff) << 4);
38        self.w
39    }
40}
41impl R {
42    #[doc = "Bits 0:3 - Dithering Cycle Number"]
43    #[inline(always)]
44    pub fn dithercy(&self) -> DITHERCY_R {
45        DITHERCY_R::new((self.bits & 0x0f) as u8)
46    }
47    #[doc = "Bits 4:23 - Channel Compare/Capture Value"]
48    #[inline(always)]
49    pub fn cc(&self) -> CC_R {
50        CC_R::new(((self.bits >> 4) & 0x000f_ffff) as u32)
51    }
52}
53impl W {
54    #[doc = "Bits 0:3 - Dithering Cycle Number"]
55    #[inline(always)]
56    pub fn dithercy(&mut self) -> DITHERCY_W {
57        DITHERCY_W { w: self }
58    }
59    #[doc = "Bits 4:23 - Channel Compare/Capture Value"]
60    #[inline(always)]
61    pub fn cc(&mut self) -> CC_W {
62        CC_W { w: self }
63    }
64}
atsamd21e18a/tcc0/cc_dith4.rs

atsamd21e18a/tcc0/
cc_dith4.rs
