atsamd21e18a/sysctrl/
osc32k.rs

1#[doc = "Reader of register OSC32K"]
2pub type R = crate::R<u32, super::OSC32K>;
3#[doc = "Writer for register OSC32K"]
4pub type W = crate::W<u32, super::OSC32K>;
5#[doc = "Register OSC32K `reset()`'s with value 0x003f_0080"]
6impl crate::ResetValue for super::OSC32K {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0x003f_0080
11    }
12}
13#[doc = "Reader of field `ENABLE`"]
14pub type ENABLE_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `ENABLE`"]
16pub struct ENABLE_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> ENABLE_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
34        self.w
35    }
36}
37#[doc = "Reader of field `EN32K`"]
38pub type EN32K_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `EN32K`"]
40pub struct EN32K_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> EN32K_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
58        self.w
59    }
60}
61#[doc = "Reader of field `EN1K`"]
62pub type EN1K_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `EN1K`"]
64pub struct EN1K_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> EN1K_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
82        self.w
83    }
84}
85#[doc = "Reader of field `RUNSTDBY`"]
86pub type RUNSTDBY_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `RUNSTDBY`"]
88pub struct RUNSTDBY_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> RUNSTDBY_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
106        self.w
107    }
108}
109#[doc = "Reader of field `ONDEMAND`"]
110pub type ONDEMAND_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `ONDEMAND`"]
112pub struct ONDEMAND_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> ONDEMAND_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
130        self.w
131    }
132}
133#[doc = "Reader of field `STARTUP`"]
134pub type STARTUP_R = crate::R<u8, u8>;
135#[doc = "Write proxy for field `STARTUP`"]
136pub struct STARTUP_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> STARTUP_W<'a> {
140    #[doc = r"Writes raw bits to the field"]
141    #[inline(always)]
142    pub unsafe fn bits(self, value: u8) -> &'a mut W {
143        self.w.bits = (self.w.bits & !(0x07 << 8)) | (((value as u32) & 0x07) << 8);
144        self.w
145    }
146}
147#[doc = "Reader of field `WRTLOCK`"]
148pub type WRTLOCK_R = crate::R<bool, bool>;
149#[doc = "Write proxy for field `WRTLOCK`"]
150pub struct WRTLOCK_W<'a> {
151    w: &'a mut W,
152}
153impl<'a> WRTLOCK_W<'a> {
154    #[doc = r"Sets the field bit"]
155    #[inline(always)]
156    pub fn set_bit(self) -> &'a mut W {
157        self.bit(true)
158    }
159    #[doc = r"Clears the field bit"]
160    #[inline(always)]
161    pub fn clear_bit(self) -> &'a mut W {
162        self.bit(false)
163    }
164    #[doc = r"Writes raw bits to the field"]
165    #[inline(always)]
166    pub fn bit(self, value: bool) -> &'a mut W {
167        self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
168        self.w
169    }
170}
171#[doc = "Reader of field `CALIB`"]
172pub type CALIB_R = crate::R<u8, u8>;
173#[doc = "Write proxy for field `CALIB`"]
174pub struct CALIB_W<'a> {
175    w: &'a mut W,
176}
177impl<'a> CALIB_W<'a> {
178    #[doc = r"Writes raw bits to the field"]
179    #[inline(always)]
180    pub unsafe fn bits(self, value: u8) -> &'a mut W {
181        self.w.bits = (self.w.bits & !(0x7f << 16)) | (((value as u32) & 0x7f) << 16);
182        self.w
183    }
184}
185impl R {
186    #[doc = "Bit 1 - Oscillator Enable"]
187    #[inline(always)]
188    pub fn enable(&self) -> ENABLE_R {
189        ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
190    }
191    #[doc = "Bit 2 - 32kHz Output Enable"]
192    #[inline(always)]
193    pub fn en32k(&self) -> EN32K_R {
194        EN32K_R::new(((self.bits >> 2) & 0x01) != 0)
195    }
196    #[doc = "Bit 3 - 1kHz Output Enable"]
197    #[inline(always)]
198    pub fn en1k(&self) -> EN1K_R {
199        EN1K_R::new(((self.bits >> 3) & 0x01) != 0)
200    }
201    #[doc = "Bit 6 - Run in Standby"]
202    #[inline(always)]
203    pub fn runstdby(&self) -> RUNSTDBY_R {
204        RUNSTDBY_R::new(((self.bits >> 6) & 0x01) != 0)
205    }
206    #[doc = "Bit 7 - On Demand Control"]
207    #[inline(always)]
208    pub fn ondemand(&self) -> ONDEMAND_R {
209        ONDEMAND_R::new(((self.bits >> 7) & 0x01) != 0)
210    }
211    #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
212    #[inline(always)]
213    pub fn startup(&self) -> STARTUP_R {
214        STARTUP_R::new(((self.bits >> 8) & 0x07) as u8)
215    }
216    #[doc = "Bit 12 - Write Lock"]
217    #[inline(always)]
218    pub fn wrtlock(&self) -> WRTLOCK_R {
219        WRTLOCK_R::new(((self.bits >> 12) & 0x01) != 0)
220    }
221    #[doc = "Bits 16:22 - Oscillator Calibration"]
222    #[inline(always)]
223    pub fn calib(&self) -> CALIB_R {
224        CALIB_R::new(((self.bits >> 16) & 0x7f) as u8)
225    }
226}
227impl W {
228    #[doc = "Bit 1 - Oscillator Enable"]
229    #[inline(always)]
230    pub fn enable(&mut self) -> ENABLE_W {
231        ENABLE_W { w: self }
232    }
233    #[doc = "Bit 2 - 32kHz Output Enable"]
234    #[inline(always)]
235    pub fn en32k(&mut self) -> EN32K_W {
236        EN32K_W { w: self }
237    }
238    #[doc = "Bit 3 - 1kHz Output Enable"]
239    #[inline(always)]
240    pub fn en1k(&mut self) -> EN1K_W {
241        EN1K_W { w: self }
242    }
243    #[doc = "Bit 6 - Run in Standby"]
244    #[inline(always)]
245    pub fn runstdby(&mut self) -> RUNSTDBY_W {
246        RUNSTDBY_W { w: self }
247    }
248    #[doc = "Bit 7 - On Demand Control"]
249    #[inline(always)]
250    pub fn ondemand(&mut self) -> ONDEMAND_W {
251        ONDEMAND_W { w: self }
252    }
253    #[doc = "Bits 8:10 - Oscillator Start-Up Time"]
254    #[inline(always)]
255    pub fn startup(&mut self) -> STARTUP_W {
256        STARTUP_W { w: self }
257    }
258    #[doc = "Bit 12 - Write Lock"]
259    #[inline(always)]
260    pub fn wrtlock(&mut self) -> WRTLOCK_W {
261        WRTLOCK_W { w: self }
262    }
263    #[doc = "Bits 16:22 - Oscillator Calibration"]
264    #[inline(always)]
265    pub fn calib(&mut self) -> CALIB_W {
266        CALIB_W { w: self }
267    }
268}
atsamd21e18a/sysctrl/osc32k.rs

atsamd21e18a/sysctrl/
osc32k.rs
