atsamd21e18a 0.5.0

Peripheral access API for ATSAMD21E18A microcontrollers (generated using svd2rust)
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176

#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
    #[doc = "0x00 - Control"]
    pub ctrl: CTRL,
    #[doc = "0x01 - Status A"]
    pub statusa: STATUSA,
    #[doc = "0x02 - Status B"]
    pub statusb: STATUSB,
    _reserved3: [u8; 1usize],
    #[doc = "0x04 - Address"]
    pub addr: ADDR,
    #[doc = "0x08 - Length"]
    pub length: LENGTH,
    #[doc = "0x0c - Data"]
    pub data: DATA,
    #[doc = "0x10 - Debug Communication Channel n"]
    pub dcc: [DCC; 2],
    #[doc = "0x18 - Device Identification"]
    pub did: DID,
    _reserved8: [u8; 4068usize],
    #[doc = "0x1000 - CoreSight ROM Table Entry 0"]
    pub entry: ENTRY,
    #[doc = "0x1004 - CoreSight ROM Table Entry 1"]
    pub entry1: ENTRY1,
    #[doc = "0x1008 - CoreSight ROM Table End"]
    pub end: END,
    _reserved11: [u8; 4032usize],
    #[doc = "0x1fcc - CoreSight ROM Table Memory Type"]
    pub memtype: MEMTYPE,
    #[doc = "0x1fd0 - Peripheral Identification 4"]
    pub pid4: PID4,
    _reserved13: [u8; 12usize],
    #[doc = "0x1fe0 - Peripheral Identification 0"]
    pub pid0: PID0,
    #[doc = "0x1fe4 - Peripheral Identification 1"]
    pub pid1: PID1,
    #[doc = "0x1fe8 - Peripheral Identification 2"]
    pub pid2: PID2,
    #[doc = "0x1fec - Peripheral Identification 3"]
    pub pid3: PID3,
    #[doc = "0x1ff0 - Component Identification 0"]
    pub cid0: CID0,
    #[doc = "0x1ff4 - Component Identification 1"]
    pub cid1: CID1,
    #[doc = "0x1ff8 - Component Identification 2"]
    pub cid2: CID2,
    #[doc = "0x1ffc - Component Identification 3"]
    pub cid3: CID3,
}
#[doc = "Control"]
pub struct CTRL {
    register: ::vcell::VolatileCell<u8>,
}
#[doc = "Control"]
pub mod ctrl;
#[doc = "Status A"]
pub struct STATUSA {
    register: ::vcell::VolatileCell<u8>,
}
#[doc = "Status A"]
pub mod statusa;
#[doc = "Status B"]
pub struct STATUSB {
    register: ::vcell::VolatileCell<u8>,
}
#[doc = "Status B"]
pub mod statusb;
#[doc = "Address"]
pub struct ADDR {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Address"]
pub mod addr;
#[doc = "Length"]
pub struct LENGTH {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Length"]
pub mod length;
#[doc = "Data"]
pub struct DATA {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Data"]
pub mod data;
#[doc = "Debug Communication Channel n"]
pub struct DCC {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Debug Communication Channel n"]
pub mod dcc;
#[doc = "Device Identification"]
pub struct DID {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Device Identification"]
pub mod did;
#[doc = "CoreSight ROM Table Entry 0"]
pub struct ENTRY {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "CoreSight ROM Table Entry 0"]
pub mod entry;
#[doc = "CoreSight ROM Table Entry 1"]
pub struct ENTRY1 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "CoreSight ROM Table Entry 1"]
pub mod entry1;
#[doc = "CoreSight ROM Table End"]
pub struct END {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "CoreSight ROM Table End"]
pub mod end;
#[doc = "CoreSight ROM Table Memory Type"]
pub struct MEMTYPE {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "CoreSight ROM Table Memory Type"]
pub mod memtype;
#[doc = "Peripheral Identification 4"]
pub struct PID4 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Identification 4"]
pub mod pid4;
#[doc = "Peripheral Identification 0"]
pub struct PID0 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Identification 0"]
pub mod pid0;
#[doc = "Peripheral Identification 1"]
pub struct PID1 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Identification 1"]
pub mod pid1;
#[doc = "Peripheral Identification 2"]
pub struct PID2 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Identification 2"]
pub mod pid2;
#[doc = "Peripheral Identification 3"]
pub struct PID3 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Peripheral Identification 3"]
pub mod pid3;
#[doc = "Component Identification 0"]
pub struct CID0 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Component Identification 0"]
pub mod cid0;
#[doc = "Component Identification 1"]
pub struct CID1 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Component Identification 1"]
pub mod cid1;
#[doc = "Component Identification 2"]
pub struct CID2 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Component Identification 2"]
pub mod cid2;
#[doc = "Component Identification 3"]
pub struct CID3 {
    register: ::vcell::VolatileCell<u32>,
}
#[doc = "Component Identification 3"]
pub mod cid3;