atsam4sd32b_pac/twi0/
imr.rs

1#[doc = "Register `IMR` reader"]
2pub struct R(crate::R<IMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `TXCOMP` reader - Transmission Completed Interrupt Mask"]
17pub type TXCOMP_R = crate::BitReader<bool>;
18#[doc = "Field `RXRDY` reader - Receive Holding Register Ready Interrupt Mask"]
19pub type RXRDY_R = crate::BitReader<bool>;
20#[doc = "Field `TXRDY` reader - Transmit Holding Register Ready Interrupt Mask"]
21pub type TXRDY_R = crate::BitReader<bool>;
22#[doc = "Field `SVACC` reader - Slave Access Interrupt Mask"]
23pub type SVACC_R = crate::BitReader<bool>;
24#[doc = "Field `GACC` reader - General Call Access Interrupt Mask"]
25pub type GACC_R = crate::BitReader<bool>;
26#[doc = "Field `OVRE` reader - Overrun Error Interrupt Mask"]
27pub type OVRE_R = crate::BitReader<bool>;
28#[doc = "Field `NACK` reader - Not Acknowledge Interrupt Mask"]
29pub type NACK_R = crate::BitReader<bool>;
30#[doc = "Field `ARBLST` reader - Arbitration Lost Interrupt Mask"]
31pub type ARBLST_R = crate::BitReader<bool>;
32#[doc = "Field `SCL_WS` reader - Clock Wait State Interrupt Mask"]
33pub type SCL_WS_R = crate::BitReader<bool>;
34#[doc = "Field `EOSACC` reader - End Of Slave Access Interrupt Mask"]
35pub type EOSACC_R = crate::BitReader<bool>;
36#[doc = "Field `ENDRX` reader - End of Receive Buffer Interrupt Mask"]
37pub type ENDRX_R = crate::BitReader<bool>;
38#[doc = "Field `ENDTX` reader - End of Transmit Buffer Interrupt Mask"]
39pub type ENDTX_R = crate::BitReader<bool>;
40#[doc = "Field `RXBUFF` reader - Receive Buffer Full Interrupt Mask"]
41pub type RXBUFF_R = crate::BitReader<bool>;
42#[doc = "Field `TXBUFE` reader - Transmit Buffer Empty Interrupt Mask"]
43pub type TXBUFE_R = crate::BitReader<bool>;
44impl R {
45    #[doc = "Bit 0 - Transmission Completed Interrupt Mask"]
46    #[inline(always)]
47    pub fn txcomp(&self) -> TXCOMP_R {
48        TXCOMP_R::new((self.bits & 1) != 0)
49    }
50    #[doc = "Bit 1 - Receive Holding Register Ready Interrupt Mask"]
51    #[inline(always)]
52    pub fn rxrdy(&self) -> RXRDY_R {
53        RXRDY_R::new(((self.bits >> 1) & 1) != 0)
54    }
55    #[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Mask"]
56    #[inline(always)]
57    pub fn txrdy(&self) -> TXRDY_R {
58        TXRDY_R::new(((self.bits >> 2) & 1) != 0)
59    }
60    #[doc = "Bit 4 - Slave Access Interrupt Mask"]
61    #[inline(always)]
62    pub fn svacc(&self) -> SVACC_R {
63        SVACC_R::new(((self.bits >> 4) & 1) != 0)
64    }
65    #[doc = "Bit 5 - General Call Access Interrupt Mask"]
66    #[inline(always)]
67    pub fn gacc(&self) -> GACC_R {
68        GACC_R::new(((self.bits >> 5) & 1) != 0)
69    }
70    #[doc = "Bit 6 - Overrun Error Interrupt Mask"]
71    #[inline(always)]
72    pub fn ovre(&self) -> OVRE_R {
73        OVRE_R::new(((self.bits >> 6) & 1) != 0)
74    }
75    #[doc = "Bit 8 - Not Acknowledge Interrupt Mask"]
76    #[inline(always)]
77    pub fn nack(&self) -> NACK_R {
78        NACK_R::new(((self.bits >> 8) & 1) != 0)
79    }
80    #[doc = "Bit 9 - Arbitration Lost Interrupt Mask"]
81    #[inline(always)]
82    pub fn arblst(&self) -> ARBLST_R {
83        ARBLST_R::new(((self.bits >> 9) & 1) != 0)
84    }
85    #[doc = "Bit 10 - Clock Wait State Interrupt Mask"]
86    #[inline(always)]
87    pub fn scl_ws(&self) -> SCL_WS_R {
88        SCL_WS_R::new(((self.bits >> 10) & 1) != 0)
89    }
90    #[doc = "Bit 11 - End Of Slave Access Interrupt Mask"]
91    #[inline(always)]
92    pub fn eosacc(&self) -> EOSACC_R {
93        EOSACC_R::new(((self.bits >> 11) & 1) != 0)
94    }
95    #[doc = "Bit 12 - End of Receive Buffer Interrupt Mask"]
96    #[inline(always)]
97    pub fn endrx(&self) -> ENDRX_R {
98        ENDRX_R::new(((self.bits >> 12) & 1) != 0)
99    }
100    #[doc = "Bit 13 - End of Transmit Buffer Interrupt Mask"]
101    #[inline(always)]
102    pub fn endtx(&self) -> ENDTX_R {
103        ENDTX_R::new(((self.bits >> 13) & 1) != 0)
104    }
105    #[doc = "Bit 14 - Receive Buffer Full Interrupt Mask"]
106    #[inline(always)]
107    pub fn rxbuff(&self) -> RXBUFF_R {
108        RXBUFF_R::new(((self.bits >> 14) & 1) != 0)
109    }
110    #[doc = "Bit 15 - Transmit Buffer Empty Interrupt Mask"]
111    #[inline(always)]
112    pub fn txbufe(&self) -> TXBUFE_R {
113        TXBUFE_R::new(((self.bits >> 15) & 1) != 0)
114    }
115}
116#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"]
117pub struct IMR_SPEC;
118impl crate::RegisterSpec for IMR_SPEC {
119    type Ux = u32;
120}
121#[doc = "`read()` method returns [imr::R](R) reader structure"]
122impl crate::Readable for IMR_SPEC {
123    type Reader = R;
124}
125#[doc = "`reset()` method sets IMR to value 0"]
126impl crate::Resettable for IMR_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
atsam4sd32b_pac/twi0/imr.rs

atsam4sd32b_pac/twi0/
imr.rs
