atsam4s8c_pac/dacc/
cher.rs

1#[doc = "Register `CHER` writer"]
2pub struct W(crate::W<CHER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0` writer - Channel 0 Enable"]
23pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHER_SPEC, bool, O>;
24#[doc = "Field `CH1` writer - Channel 1 Enable"]
25pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHER_SPEC, bool, O>;
26impl W {
27    #[doc = "Bit 0 - Channel 0 Enable"]
28    #[inline(always)]
29    #[must_use]
30    pub fn ch0(&mut self) -> CH0_W<0> {
31        CH0_W::new(self)
32    }
33    #[doc = "Bit 1 - Channel 1 Enable"]
34    #[inline(always)]
35    #[must_use]
36    pub fn ch1(&mut self) -> CH1_W<1> {
37        CH1_W::new(self)
38    }
39    #[doc = "Writes raw bits to the register."]
40    #[inline(always)]
41    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
42        self.0.bits(bits);
43        self
44    }
45}
46#[doc = "Channel Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cher](index.html) module"]
47pub struct CHER_SPEC;
48impl crate::RegisterSpec for CHER_SPEC {
49    type Ux = u32;
50}
51#[doc = "`write(|w| ..)` method takes [cher::W](W) writer structure"]
52impl crate::Writable for CHER_SPEC {
53    type Writer = W;
54    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
55    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
56}
atsam4s8c_pac/dacc/cher.rs

atsam4s8c_pac/dacc/
cher.rs
