atsam4s8b_pac/pmc/
pmc_mckr.rs

1#[doc = "Register `PMC_MCKR` reader"]
2pub struct R(crate::R<PMC_MCKR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PMC_MCKR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PMC_MCKR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PMC_MCKR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PMC_MCKR` writer"]
17pub struct W(crate::W<PMC_MCKR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PMC_MCKR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PMC_MCKR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PMC_MCKR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CSS` reader - Master Clock Source Selection"]
38pub type CSS_R = crate::FieldReader<u8, CSS_A>;
39#[doc = "Master Clock Source Selection\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CSS_A {
43    #[doc = "0: Slow Clock is selected"]
44    SLOW_CLK = 0,
45    #[doc = "1: Main Clock is selected"]
46    MAIN_CLK = 1,
47    #[doc = "2: PLLA Clock is selected"]
48    PLLA_CLK = 2,
49    #[doc = "3: PLLBClock is selected"]
50    PLLB_CLK = 3,
51}
52impl From<CSS_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CSS_A) -> Self {
55        variant as _
56    }
57}
58impl CSS_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> CSS_A {
62        match self.bits {
63            0 => CSS_A::SLOW_CLK,
64            1 => CSS_A::MAIN_CLK,
65            2 => CSS_A::PLLA_CLK,
66            3 => CSS_A::PLLB_CLK,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `SLOW_CLK`"]
71    #[inline(always)]
72    pub fn is_slow_clk(&self) -> bool {
73        *self == CSS_A::SLOW_CLK
74    }
75    #[doc = "Checks if the value of the field is `MAIN_CLK`"]
76    #[inline(always)]
77    pub fn is_main_clk(&self) -> bool {
78        *self == CSS_A::MAIN_CLK
79    }
80    #[doc = "Checks if the value of the field is `PLLA_CLK`"]
81    #[inline(always)]
82    pub fn is_plla_clk(&self) -> bool {
83        *self == CSS_A::PLLA_CLK
84    }
85    #[doc = "Checks if the value of the field is `PLLB_CLK`"]
86    #[inline(always)]
87    pub fn is_pllb_clk(&self) -> bool {
88        *self == CSS_A::PLLB_CLK
89    }
90}
91#[doc = "Field `CSS` writer - Master Clock Source Selection"]
92pub type CSS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, PMC_MCKR_SPEC, u8, CSS_A, 2, O>;
93impl<'a, const O: u8> CSS_W<'a, O> {
94    #[doc = "Slow Clock is selected"]
95    #[inline(always)]
96    pub fn slow_clk(self) -> &'a mut W {
97        self.variant(CSS_A::SLOW_CLK)
98    }
99    #[doc = "Main Clock is selected"]
100    #[inline(always)]
101    pub fn main_clk(self) -> &'a mut W {
102        self.variant(CSS_A::MAIN_CLK)
103    }
104    #[doc = "PLLA Clock is selected"]
105    #[inline(always)]
106    pub fn plla_clk(self) -> &'a mut W {
107        self.variant(CSS_A::PLLA_CLK)
108    }
109    #[doc = "PLLBClock is selected"]
110    #[inline(always)]
111    pub fn pllb_clk(self) -> &'a mut W {
112        self.variant(CSS_A::PLLB_CLK)
113    }
114}
115#[doc = "Field `PRES` reader - Processor Clock Prescaler"]
116pub type PRES_R = crate::FieldReader<u8, PRES_A>;
117#[doc = "Processor Clock Prescaler\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119#[repr(u8)]
120pub enum PRES_A {
121    #[doc = "0: Selected clock"]
122    CLK_1 = 0,
123    #[doc = "1: Selected clock divided by 2"]
124    CLK_2 = 1,
125    #[doc = "2: Selected clock divided by 4"]
126    CLK_4 = 2,
127    #[doc = "3: Selected clock divided by 8"]
128    CLK_8 = 3,
129    #[doc = "4: Selected clock divided by 16"]
130    CLK_16 = 4,
131    #[doc = "5: Selected clock divided by 32"]
132    CLK_32 = 5,
133    #[doc = "6: Selected clock divided by 64"]
134    CLK_64 = 6,
135    #[doc = "7: Selected clock divided by 3"]
136    CLK_3 = 7,
137}
138impl From<PRES_A> for u8 {
139    #[inline(always)]
140    fn from(variant: PRES_A) -> Self {
141        variant as _
142    }
143}
144impl PRES_R {
145    #[doc = "Get enumerated values variant"]
146    #[inline(always)]
147    pub fn variant(&self) -> PRES_A {
148        match self.bits {
149            0 => PRES_A::CLK_1,
150            1 => PRES_A::CLK_2,
151            2 => PRES_A::CLK_4,
152            3 => PRES_A::CLK_8,
153            4 => PRES_A::CLK_16,
154            5 => PRES_A::CLK_32,
155            6 => PRES_A::CLK_64,
156            7 => PRES_A::CLK_3,
157            _ => unreachable!(),
158        }
159    }
160    #[doc = "Checks if the value of the field is `CLK_1`"]
161    #[inline(always)]
162    pub fn is_clk_1(&self) -> bool {
163        *self == PRES_A::CLK_1
164    }
165    #[doc = "Checks if the value of the field is `CLK_2`"]
166    #[inline(always)]
167    pub fn is_clk_2(&self) -> bool {
168        *self == PRES_A::CLK_2
169    }
170    #[doc = "Checks if the value of the field is `CLK_4`"]
171    #[inline(always)]
172    pub fn is_clk_4(&self) -> bool {
173        *self == PRES_A::CLK_4
174    }
175    #[doc = "Checks if the value of the field is `CLK_8`"]
176    #[inline(always)]
177    pub fn is_clk_8(&self) -> bool {
178        *self == PRES_A::CLK_8
179    }
180    #[doc = "Checks if the value of the field is `CLK_16`"]
181    #[inline(always)]
182    pub fn is_clk_16(&self) -> bool {
183        *self == PRES_A::CLK_16
184    }
185    #[doc = "Checks if the value of the field is `CLK_32`"]
186    #[inline(always)]
187    pub fn is_clk_32(&self) -> bool {
188        *self == PRES_A::CLK_32
189    }
190    #[doc = "Checks if the value of the field is `CLK_64`"]
191    #[inline(always)]
192    pub fn is_clk_64(&self) -> bool {
193        *self == PRES_A::CLK_64
194    }
195    #[doc = "Checks if the value of the field is `CLK_3`"]
196    #[inline(always)]
197    pub fn is_clk_3(&self) -> bool {
198        *self == PRES_A::CLK_3
199    }
200}
201#[doc = "Field `PRES` writer - Processor Clock Prescaler"]
202pub type PRES_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, PMC_MCKR_SPEC, u8, PRES_A, 3, O>;
203impl<'a, const O: u8> PRES_W<'a, O> {
204    #[doc = "Selected clock"]
205    #[inline(always)]
206    pub fn clk_1(self) -> &'a mut W {
207        self.variant(PRES_A::CLK_1)
208    }
209    #[doc = "Selected clock divided by 2"]
210    #[inline(always)]
211    pub fn clk_2(self) -> &'a mut W {
212        self.variant(PRES_A::CLK_2)
213    }
214    #[doc = "Selected clock divided by 4"]
215    #[inline(always)]
216    pub fn clk_4(self) -> &'a mut W {
217        self.variant(PRES_A::CLK_4)
218    }
219    #[doc = "Selected clock divided by 8"]
220    #[inline(always)]
221    pub fn clk_8(self) -> &'a mut W {
222        self.variant(PRES_A::CLK_8)
223    }
224    #[doc = "Selected clock divided by 16"]
225    #[inline(always)]
226    pub fn clk_16(self) -> &'a mut W {
227        self.variant(PRES_A::CLK_16)
228    }
229    #[doc = "Selected clock divided by 32"]
230    #[inline(always)]
231    pub fn clk_32(self) -> &'a mut W {
232        self.variant(PRES_A::CLK_32)
233    }
234    #[doc = "Selected clock divided by 64"]
235    #[inline(always)]
236    pub fn clk_64(self) -> &'a mut W {
237        self.variant(PRES_A::CLK_64)
238    }
239    #[doc = "Selected clock divided by 3"]
240    #[inline(always)]
241    pub fn clk_3(self) -> &'a mut W {
242        self.variant(PRES_A::CLK_3)
243    }
244}
245#[doc = "Field `PLLADIV2` reader - PLLA Divisor by 2"]
246pub type PLLADIV2_R = crate::BitReader<bool>;
247#[doc = "Field `PLLADIV2` writer - PLLA Divisor by 2"]
248pub type PLLADIV2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMC_MCKR_SPEC, bool, O>;
249#[doc = "Field `PLLBDIV2` reader - PLLB Divisor by 2"]
250pub type PLLBDIV2_R = crate::BitReader<bool>;
251#[doc = "Field `PLLBDIV2` writer - PLLB Divisor by 2"]
252pub type PLLBDIV2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PMC_MCKR_SPEC, bool, O>;
253impl R {
254    #[doc = "Bits 0:1 - Master Clock Source Selection"]
255    #[inline(always)]
256    pub fn css(&self) -> CSS_R {
257        CSS_R::new((self.bits & 3) as u8)
258    }
259    #[doc = "Bits 4:6 - Processor Clock Prescaler"]
260    #[inline(always)]
261    pub fn pres(&self) -> PRES_R {
262        PRES_R::new(((self.bits >> 4) & 7) as u8)
263    }
264    #[doc = "Bit 12 - PLLA Divisor by 2"]
265    #[inline(always)]
266    pub fn plladiv2(&self) -> PLLADIV2_R {
267        PLLADIV2_R::new(((self.bits >> 12) & 1) != 0)
268    }
269    #[doc = "Bit 13 - PLLB Divisor by 2"]
270    #[inline(always)]
271    pub fn pllbdiv2(&self) -> PLLBDIV2_R {
272        PLLBDIV2_R::new(((self.bits >> 13) & 1) != 0)
273    }
274}
275impl W {
276    #[doc = "Bits 0:1 - Master Clock Source Selection"]
277    #[inline(always)]
278    #[must_use]
279    pub fn css(&mut self) -> CSS_W<0> {
280        CSS_W::new(self)
281    }
282    #[doc = "Bits 4:6 - Processor Clock Prescaler"]
283    #[inline(always)]
284    #[must_use]
285    pub fn pres(&mut self) -> PRES_W<4> {
286        PRES_W::new(self)
287    }
288    #[doc = "Bit 12 - PLLA Divisor by 2"]
289    #[inline(always)]
290    #[must_use]
291    pub fn plladiv2(&mut self) -> PLLADIV2_W<12> {
292        PLLADIV2_W::new(self)
293    }
294    #[doc = "Bit 13 - PLLB Divisor by 2"]
295    #[inline(always)]
296    #[must_use]
297    pub fn pllbdiv2(&mut self) -> PLLBDIV2_W<13> {
298        PLLBDIV2_W::new(self)
299    }
300    #[doc = "Writes raw bits to the register."]
301    #[inline(always)]
302    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
303        self.0.bits(bits);
304        self
305    }
306}
307#[doc = "Master Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmc_mckr](index.html) module"]
308pub struct PMC_MCKR_SPEC;
309impl crate::RegisterSpec for PMC_MCKR_SPEC {
310    type Ux = u32;
311}
312#[doc = "`read()` method returns [pmc_mckr::R](R) reader structure"]
313impl crate::Readable for PMC_MCKR_SPEC {
314    type Reader = R;
315}
316#[doc = "`write(|w| ..)` method takes [pmc_mckr::W](W) writer structure"]
317impl crate::Writable for PMC_MCKR_SPEC {
318    type Writer = W;
319    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
320    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
321}
322#[doc = "`reset()` method sets PMC_MCKR to value 0x01"]
323impl crate::Resettable for PMC_MCKR_SPEC {
324    const RESET_VALUE: Self::Ux = 0x01;
325}
atsam4s8b_pac/pmc/pmc_mckr.rs

atsam4s8b_pac/pmc/
pmc_mckr.rs
