1#[doc = "Register `MR` reader"]
2pub struct R(crate::R<MR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `MR` writer"]
17pub struct W(crate::W<MR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `DIVA` reader - CLKA, CLKB Divide Factor"]
38pub type DIVA_R = crate::FieldReader<u8, DIVA_A>;
39#[doc = "CLKA, CLKB Divide Factor\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum DIVA_A {
43 #[doc = "0: CLKA, CLKB clock is turned off"]
44 CLK_OFF = 0,
45 #[doc = "1: CLKA, CLKB clock is clock selected by PREA, PREB"]
46 CLK_DIV1 = 1,
47}
48impl From<DIVA_A> for u8 {
49 #[inline(always)]
50 fn from(variant: DIVA_A) -> Self {
51 variant as _
52 }
53}
54impl DIVA_R {
55 #[doc = "Get enumerated values variant"]
56 #[inline(always)]
57 pub fn variant(&self) -> Option<DIVA_A> {
58 match self.bits {
59 0 => Some(DIVA_A::CLK_OFF),
60 1 => Some(DIVA_A::CLK_DIV1),
61 _ => None,
62 }
63 }
64 #[doc = "Checks if the value of the field is `CLK_OFF`"]
65 #[inline(always)]
66 pub fn is_clk_off(&self) -> bool {
67 *self == DIVA_A::CLK_OFF
68 }
69 #[doc = "Checks if the value of the field is `CLK_DIV1`"]
70 #[inline(always)]
71 pub fn is_clk_div1(&self) -> bool {
72 *self == DIVA_A::CLK_DIV1
73 }
74}
75#[doc = "Field `DIVA` writer - CLKA, CLKB Divide Factor"]
76pub type DIVA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, DIVA_A, 8, O>;
77impl<'a, const O: u8> DIVA_W<'a, O> {
78 #[doc = "CLKA, CLKB clock is turned off"]
79 #[inline(always)]
80 pub fn clk_off(self) -> &'a mut W {
81 self.variant(DIVA_A::CLK_OFF)
82 }
83 #[doc = "CLKA, CLKB clock is clock selected by PREA, PREB"]
84 #[inline(always)]
85 pub fn clk_div1(self) -> &'a mut W {
86 self.variant(DIVA_A::CLK_DIV1)
87 }
88}
89#[doc = "Field `PREA` reader - "]
90pub type PREA_R = crate::FieldReader<u8, PREA_A>;
91#[doc = "\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq, Eq)]
93#[repr(u8)]
94pub enum PREA_A {
95 #[doc = "0: Master Clock"]
96 MCK = 0,
97 #[doc = "1: Master Clock divided by 2"]
98 MCKDIV2 = 1,
99 #[doc = "2: Master Clock divided by 4"]
100 MCKDIV4 = 2,
101 #[doc = "3: Master Clock divided by 8"]
102 MCKDIV8 = 3,
103 #[doc = "4: Master Clock divided by 16"]
104 MCKDIV16 = 4,
105 #[doc = "5: Master Clock divided by 32"]
106 MCKDIV32 = 5,
107 #[doc = "6: Master Clock divided by 64"]
108 MCKDIV64 = 6,
109 #[doc = "7: Master Clock divided by 128"]
110 MCKDIV128 = 7,
111 #[doc = "8: Master Clock divided by 256"]
112 MCKDIV256 = 8,
113 #[doc = "9: Master Clock divided by 512"]
114 MCKDIV512 = 9,
115 #[doc = "10: Master Clock divided by 1024"]
116 MCKDIV1024 = 10,
117}
118impl From<PREA_A> for u8 {
119 #[inline(always)]
120 fn from(variant: PREA_A) -> Self {
121 variant as _
122 }
123}
124impl PREA_R {
125 #[doc = "Get enumerated values variant"]
126 #[inline(always)]
127 pub fn variant(&self) -> Option<PREA_A> {
128 match self.bits {
129 0 => Some(PREA_A::MCK),
130 1 => Some(PREA_A::MCKDIV2),
131 2 => Some(PREA_A::MCKDIV4),
132 3 => Some(PREA_A::MCKDIV8),
133 4 => Some(PREA_A::MCKDIV16),
134 5 => Some(PREA_A::MCKDIV32),
135 6 => Some(PREA_A::MCKDIV64),
136 7 => Some(PREA_A::MCKDIV128),
137 8 => Some(PREA_A::MCKDIV256),
138 9 => Some(PREA_A::MCKDIV512),
139 10 => Some(PREA_A::MCKDIV1024),
140 _ => None,
141 }
142 }
143 #[doc = "Checks if the value of the field is `MCK`"]
144 #[inline(always)]
145 pub fn is_mck(&self) -> bool {
146 *self == PREA_A::MCK
147 }
148 #[doc = "Checks if the value of the field is `MCKDIV2`"]
149 #[inline(always)]
150 pub fn is_mckdiv2(&self) -> bool {
151 *self == PREA_A::MCKDIV2
152 }
153 #[doc = "Checks if the value of the field is `MCKDIV4`"]
154 #[inline(always)]
155 pub fn is_mckdiv4(&self) -> bool {
156 *self == PREA_A::MCKDIV4
157 }
158 #[doc = "Checks if the value of the field is `MCKDIV8`"]
159 #[inline(always)]
160 pub fn is_mckdiv8(&self) -> bool {
161 *self == PREA_A::MCKDIV8
162 }
163 #[doc = "Checks if the value of the field is `MCKDIV16`"]
164 #[inline(always)]
165 pub fn is_mckdiv16(&self) -> bool {
166 *self == PREA_A::MCKDIV16
167 }
168 #[doc = "Checks if the value of the field is `MCKDIV32`"]
169 #[inline(always)]
170 pub fn is_mckdiv32(&self) -> bool {
171 *self == PREA_A::MCKDIV32
172 }
173 #[doc = "Checks if the value of the field is `MCKDIV64`"]
174 #[inline(always)]
175 pub fn is_mckdiv64(&self) -> bool {
176 *self == PREA_A::MCKDIV64
177 }
178 #[doc = "Checks if the value of the field is `MCKDIV128`"]
179 #[inline(always)]
180 pub fn is_mckdiv128(&self) -> bool {
181 *self == PREA_A::MCKDIV128
182 }
183 #[doc = "Checks if the value of the field is `MCKDIV256`"]
184 #[inline(always)]
185 pub fn is_mckdiv256(&self) -> bool {
186 *self == PREA_A::MCKDIV256
187 }
188 #[doc = "Checks if the value of the field is `MCKDIV512`"]
189 #[inline(always)]
190 pub fn is_mckdiv512(&self) -> bool {
191 *self == PREA_A::MCKDIV512
192 }
193 #[doc = "Checks if the value of the field is `MCKDIV1024`"]
194 #[inline(always)]
195 pub fn is_mckdiv1024(&self) -> bool {
196 *self == PREA_A::MCKDIV1024
197 }
198}
199#[doc = "Field `PREA` writer - "]
200pub type PREA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, PREA_A, 4, O>;
201impl<'a, const O: u8> PREA_W<'a, O> {
202 #[doc = "Master Clock"]
203 #[inline(always)]
204 pub fn mck(self) -> &'a mut W {
205 self.variant(PREA_A::MCK)
206 }
207 #[doc = "Master Clock divided by 2"]
208 #[inline(always)]
209 pub fn mckdiv2(self) -> &'a mut W {
210 self.variant(PREA_A::MCKDIV2)
211 }
212 #[doc = "Master Clock divided by 4"]
213 #[inline(always)]
214 pub fn mckdiv4(self) -> &'a mut W {
215 self.variant(PREA_A::MCKDIV4)
216 }
217 #[doc = "Master Clock divided by 8"]
218 #[inline(always)]
219 pub fn mckdiv8(self) -> &'a mut W {
220 self.variant(PREA_A::MCKDIV8)
221 }
222 #[doc = "Master Clock divided by 16"]
223 #[inline(always)]
224 pub fn mckdiv16(self) -> &'a mut W {
225 self.variant(PREA_A::MCKDIV16)
226 }
227 #[doc = "Master Clock divided by 32"]
228 #[inline(always)]
229 pub fn mckdiv32(self) -> &'a mut W {
230 self.variant(PREA_A::MCKDIV32)
231 }
232 #[doc = "Master Clock divided by 64"]
233 #[inline(always)]
234 pub fn mckdiv64(self) -> &'a mut W {
235 self.variant(PREA_A::MCKDIV64)
236 }
237 #[doc = "Master Clock divided by 128"]
238 #[inline(always)]
239 pub fn mckdiv128(self) -> &'a mut W {
240 self.variant(PREA_A::MCKDIV128)
241 }
242 #[doc = "Master Clock divided by 256"]
243 #[inline(always)]
244 pub fn mckdiv256(self) -> &'a mut W {
245 self.variant(PREA_A::MCKDIV256)
246 }
247 #[doc = "Master Clock divided by 512"]
248 #[inline(always)]
249 pub fn mckdiv512(self) -> &'a mut W {
250 self.variant(PREA_A::MCKDIV512)
251 }
252 #[doc = "Master Clock divided by 1024"]
253 #[inline(always)]
254 pub fn mckdiv1024(self) -> &'a mut W {
255 self.variant(PREA_A::MCKDIV1024)
256 }
257}
258#[doc = "Field `DIVB` reader - CLKA, CLKB Divide Factor"]
259pub type DIVB_R = crate::FieldReader<u8, DIVB_A>;
260#[doc = "CLKA, CLKB Divide Factor\n\nValue on reset: 0"]
261#[derive(Clone, Copy, Debug, PartialEq, Eq)]
262#[repr(u8)]
263pub enum DIVB_A {
264 #[doc = "0: CLKA, CLKB clock is turned off"]
265 CLK_OFF = 0,
266 #[doc = "1: CLKA, CLKB clock is clock selected by PREA, PREB"]
267 CLK_DIV1 = 1,
268}
269impl From<DIVB_A> for u8 {
270 #[inline(always)]
271 fn from(variant: DIVB_A) -> Self {
272 variant as _
273 }
274}
275impl DIVB_R {
276 #[doc = "Get enumerated values variant"]
277 #[inline(always)]
278 pub fn variant(&self) -> Option<DIVB_A> {
279 match self.bits {
280 0 => Some(DIVB_A::CLK_OFF),
281 1 => Some(DIVB_A::CLK_DIV1),
282 _ => None,
283 }
284 }
285 #[doc = "Checks if the value of the field is `CLK_OFF`"]
286 #[inline(always)]
287 pub fn is_clk_off(&self) -> bool {
288 *self == DIVB_A::CLK_OFF
289 }
290 #[doc = "Checks if the value of the field is `CLK_DIV1`"]
291 #[inline(always)]
292 pub fn is_clk_div1(&self) -> bool {
293 *self == DIVB_A::CLK_DIV1
294 }
295}
296#[doc = "Field `DIVB` writer - CLKA, CLKB Divide Factor"]
297pub type DIVB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, DIVB_A, 8, O>;
298impl<'a, const O: u8> DIVB_W<'a, O> {
299 #[doc = "CLKA, CLKB clock is turned off"]
300 #[inline(always)]
301 pub fn clk_off(self) -> &'a mut W {
302 self.variant(DIVB_A::CLK_OFF)
303 }
304 #[doc = "CLKA, CLKB clock is clock selected by PREA, PREB"]
305 #[inline(always)]
306 pub fn clk_div1(self) -> &'a mut W {
307 self.variant(DIVB_A::CLK_DIV1)
308 }
309}
310#[doc = "Field `PREB` reader - "]
311pub type PREB_R = crate::FieldReader<u8, PREB_A>;
312#[doc = "\n\nValue on reset: 0"]
313#[derive(Clone, Copy, Debug, PartialEq, Eq)]
314#[repr(u8)]
315pub enum PREB_A {
316 #[doc = "0: Master Clock"]
317 MCK = 0,
318 #[doc = "1: Master Clock divided by 2"]
319 MCKDIV2 = 1,
320 #[doc = "2: Master Clock divided by 4"]
321 MCKDIV4 = 2,
322 #[doc = "3: Master Clock divided by 8"]
323 MCKDIV8 = 3,
324 #[doc = "4: Master Clock divided by 16"]
325 MCKDIV16 = 4,
326 #[doc = "5: Master Clock divided by 32"]
327 MCKDIV32 = 5,
328 #[doc = "6: Master Clock divided by 64"]
329 MCKDIV64 = 6,
330 #[doc = "7: Master Clock divided by 128"]
331 MCKDIV128 = 7,
332 #[doc = "8: Master Clock divided by 256"]
333 MCKDIV256 = 8,
334 #[doc = "9: Master Clock divided by 512"]
335 MCKDIV512 = 9,
336 #[doc = "10: Master Clock divided by 1024"]
337 MCKDIV1024 = 10,
338}
339impl From<PREB_A> for u8 {
340 #[inline(always)]
341 fn from(variant: PREB_A) -> Self {
342 variant as _
343 }
344}
345impl PREB_R {
346 #[doc = "Get enumerated values variant"]
347 #[inline(always)]
348 pub fn variant(&self) -> Option<PREB_A> {
349 match self.bits {
350 0 => Some(PREB_A::MCK),
351 1 => Some(PREB_A::MCKDIV2),
352 2 => Some(PREB_A::MCKDIV4),
353 3 => Some(PREB_A::MCKDIV8),
354 4 => Some(PREB_A::MCKDIV16),
355 5 => Some(PREB_A::MCKDIV32),
356 6 => Some(PREB_A::MCKDIV64),
357 7 => Some(PREB_A::MCKDIV128),
358 8 => Some(PREB_A::MCKDIV256),
359 9 => Some(PREB_A::MCKDIV512),
360 10 => Some(PREB_A::MCKDIV1024),
361 _ => None,
362 }
363 }
364 #[doc = "Checks if the value of the field is `MCK`"]
365 #[inline(always)]
366 pub fn is_mck(&self) -> bool {
367 *self == PREB_A::MCK
368 }
369 #[doc = "Checks if the value of the field is `MCKDIV2`"]
370 #[inline(always)]
371 pub fn is_mckdiv2(&self) -> bool {
372 *self == PREB_A::MCKDIV2
373 }
374 #[doc = "Checks if the value of the field is `MCKDIV4`"]
375 #[inline(always)]
376 pub fn is_mckdiv4(&self) -> bool {
377 *self == PREB_A::MCKDIV4
378 }
379 #[doc = "Checks if the value of the field is `MCKDIV8`"]
380 #[inline(always)]
381 pub fn is_mckdiv8(&self) -> bool {
382 *self == PREB_A::MCKDIV8
383 }
384 #[doc = "Checks if the value of the field is `MCKDIV16`"]
385 #[inline(always)]
386 pub fn is_mckdiv16(&self) -> bool {
387 *self == PREB_A::MCKDIV16
388 }
389 #[doc = "Checks if the value of the field is `MCKDIV32`"]
390 #[inline(always)]
391 pub fn is_mckdiv32(&self) -> bool {
392 *self == PREB_A::MCKDIV32
393 }
394 #[doc = "Checks if the value of the field is `MCKDIV64`"]
395 #[inline(always)]
396 pub fn is_mckdiv64(&self) -> bool {
397 *self == PREB_A::MCKDIV64
398 }
399 #[doc = "Checks if the value of the field is `MCKDIV128`"]
400 #[inline(always)]
401 pub fn is_mckdiv128(&self) -> bool {
402 *self == PREB_A::MCKDIV128
403 }
404 #[doc = "Checks if the value of the field is `MCKDIV256`"]
405 #[inline(always)]
406 pub fn is_mckdiv256(&self) -> bool {
407 *self == PREB_A::MCKDIV256
408 }
409 #[doc = "Checks if the value of the field is `MCKDIV512`"]
410 #[inline(always)]
411 pub fn is_mckdiv512(&self) -> bool {
412 *self == PREB_A::MCKDIV512
413 }
414 #[doc = "Checks if the value of the field is `MCKDIV1024`"]
415 #[inline(always)]
416 pub fn is_mckdiv1024(&self) -> bool {
417 *self == PREB_A::MCKDIV1024
418 }
419}
420#[doc = "Field `PREB` writer - "]
421pub type PREB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u8, PREB_A, 4, O>;
422impl<'a, const O: u8> PREB_W<'a, O> {
423 #[doc = "Master Clock"]
424 #[inline(always)]
425 pub fn mck(self) -> &'a mut W {
426 self.variant(PREB_A::MCK)
427 }
428 #[doc = "Master Clock divided by 2"]
429 #[inline(always)]
430 pub fn mckdiv2(self) -> &'a mut W {
431 self.variant(PREB_A::MCKDIV2)
432 }
433 #[doc = "Master Clock divided by 4"]
434 #[inline(always)]
435 pub fn mckdiv4(self) -> &'a mut W {
436 self.variant(PREB_A::MCKDIV4)
437 }
438 #[doc = "Master Clock divided by 8"]
439 #[inline(always)]
440 pub fn mckdiv8(self) -> &'a mut W {
441 self.variant(PREB_A::MCKDIV8)
442 }
443 #[doc = "Master Clock divided by 16"]
444 #[inline(always)]
445 pub fn mckdiv16(self) -> &'a mut W {
446 self.variant(PREB_A::MCKDIV16)
447 }
448 #[doc = "Master Clock divided by 32"]
449 #[inline(always)]
450 pub fn mckdiv32(self) -> &'a mut W {
451 self.variant(PREB_A::MCKDIV32)
452 }
453 #[doc = "Master Clock divided by 64"]
454 #[inline(always)]
455 pub fn mckdiv64(self) -> &'a mut W {
456 self.variant(PREB_A::MCKDIV64)
457 }
458 #[doc = "Master Clock divided by 128"]
459 #[inline(always)]
460 pub fn mckdiv128(self) -> &'a mut W {
461 self.variant(PREB_A::MCKDIV128)
462 }
463 #[doc = "Master Clock divided by 256"]
464 #[inline(always)]
465 pub fn mckdiv256(self) -> &'a mut W {
466 self.variant(PREB_A::MCKDIV256)
467 }
468 #[doc = "Master Clock divided by 512"]
469 #[inline(always)]
470 pub fn mckdiv512(self) -> &'a mut W {
471 self.variant(PREB_A::MCKDIV512)
472 }
473 #[doc = "Master Clock divided by 1024"]
474 #[inline(always)]
475 pub fn mckdiv1024(self) -> &'a mut W {
476 self.variant(PREB_A::MCKDIV1024)
477 }
478}
479impl R {
480 #[doc = "Bits 0:7 - CLKA, CLKB Divide Factor"]
481 #[inline(always)]
482 pub fn diva(&self) -> DIVA_R {
483 DIVA_R::new((self.bits & 0xff) as u8)
484 }
485 #[doc = "Bits 8:11"]
486 #[inline(always)]
487 pub fn prea(&self) -> PREA_R {
488 PREA_R::new(((self.bits >> 8) & 0x0f) as u8)
489 }
490 #[doc = "Bits 16:23 - CLKA, CLKB Divide Factor"]
491 #[inline(always)]
492 pub fn divb(&self) -> DIVB_R {
493 DIVB_R::new(((self.bits >> 16) & 0xff) as u8)
494 }
495 #[doc = "Bits 24:27"]
496 #[inline(always)]
497 pub fn preb(&self) -> PREB_R {
498 PREB_R::new(((self.bits >> 24) & 0x0f) as u8)
499 }
500}
501impl W {
502 #[doc = "Bits 0:7 - CLKA, CLKB Divide Factor"]
503 #[inline(always)]
504 #[must_use]
505 pub fn diva(&mut self) -> DIVA_W<0> {
506 DIVA_W::new(self)
507 }
508 #[doc = "Bits 8:11"]
509 #[inline(always)]
510 #[must_use]
511 pub fn prea(&mut self) -> PREA_W<8> {
512 PREA_W::new(self)
513 }
514 #[doc = "Bits 16:23 - CLKA, CLKB Divide Factor"]
515 #[inline(always)]
516 #[must_use]
517 pub fn divb(&mut self) -> DIVB_W<16> {
518 DIVB_W::new(self)
519 }
520 #[doc = "Bits 24:27"]
521 #[inline(always)]
522 #[must_use]
523 pub fn preb(&mut self) -> PREB_W<24> {
524 PREB_W::new(self)
525 }
526 #[doc = "Writes raw bits to the register."]
527 #[inline(always)]
528 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
529 self.0.bits(bits);
530 self
531 }
532}
533#[doc = "PWM Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"]
534pub struct MR_SPEC;
535impl crate::RegisterSpec for MR_SPEC {
536 type Ux = u32;
537}
538#[doc = "`read()` method returns [mr::R](R) reader structure"]
539impl crate::Readable for MR_SPEC {
540 type Reader = R;
541}
542#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"]
543impl crate::Writable for MR_SPEC {
544 type Writer = W;
545 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
546 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
547}
548#[doc = "`reset()` method sets MR to value 0"]
549impl crate::Resettable for MR_SPEC {
550 const RESET_VALUE: Self::Ux = 0;
551}