atsam4n16b_pac/pwm/
ccnt0.rs

1#[doc = "Register `CCNT0` reader"]
2pub struct R(crate::R<CCNT0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCNT0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCNT0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCNT0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `CNT` reader - Channel Counter Register"]
17pub type CNT_R = crate::FieldReader<u32, u32>;
18impl R {
19    #[doc = "Bits 0:31 - Channel Counter Register"]
20    #[inline(always)]
21    pub fn cnt(&self) -> CNT_R {
22        CNT_R::new(self.bits)
23    }
24}
25#[doc = "PWM Channel Counter Register (ch_num = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccnt0](index.html) module"]
26pub struct CCNT0_SPEC;
27impl crate::RegisterSpec for CCNT0_SPEC {
28    type Ux = u32;
29}
30#[doc = "`read()` method returns [ccnt0::R](R) reader structure"]
31impl crate::Readable for CCNT0_SPEC {
32    type Reader = R;
33}
34#[doc = "`reset()` method sets CCNT0 to value 0"]
35impl crate::Resettable for CCNT0_SPEC {
36    const RESET_VALUE: Self::Ux = 0;
37}
atsam4n16b_pac/pwm/ccnt0.rs

atsam4n16b_pac/pwm/
ccnt0.rs
