atsam4ls8a_pac/usbc/
udinteclr.rs

1#[doc = "Register `UDINTECLR` writer"]
2pub struct W(crate::W<UDINTECLR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<UDINTECLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<UDINTECLR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<UDINTECLR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `SUSPEC` writer - SUSP Interrupt Enable Clear"]
23pub type SUSPEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
24#[doc = "Field `MSOFEC` writer - MSOF Interrupt Enable Clear"]
25pub type MSOFEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
26#[doc = "Field `SOFEC` writer - SOF Interrupt Enable Clear"]
27pub type SOFEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
28#[doc = "Field `EORSTEC` writer - EORST Interrupt Enable Clear"]
29pub type EORSTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
30#[doc = "Field `WAKEUPEC` writer - WAKEUP Interrupt Enable Clear"]
31pub type WAKEUPEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
32#[doc = "Field `EORSMEC` writer - EORSM Interrupt Enable Clear"]
33pub type EORSMEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
34#[doc = "Field `UPRSMEC` writer - UPRSM Interrupt Enable Clear"]
35pub type UPRSMEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
36#[doc = "Field `EP0INTEC` writer - EP0INT Interrupt Enable Clear"]
37pub type EP0INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
38#[doc = "Field `EP1INTEC` writer - EP1INT Interrupt Enable Clear"]
39pub type EP1INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
40#[doc = "Field `EP2INTEC` writer - EP2INT Interrupt Enable Clear"]
41pub type EP2INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
42#[doc = "Field `EP3INTEC` writer - EP3INT Interrupt Enable Clear"]
43pub type EP3INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
44#[doc = "Field `EP4INTEC` writer - EP4INT Interrupt Enable Clear"]
45pub type EP4INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
46#[doc = "Field `EP5INTEC` writer - EP5INT Interrupt Enable Clear"]
47pub type EP5INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
48#[doc = "Field `EP6INTEC` writer - EP6INT Interrupt Enable Clear"]
49pub type EP6INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
50#[doc = "Field `EP7INTEC` writer - EP7INT Interrupt Enable Clear"]
51pub type EP7INTEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, UDINTECLR_SPEC, bool, O>;
52impl W {
53    #[doc = "Bit 0 - SUSP Interrupt Enable Clear"]
54    #[inline(always)]
55    #[must_use]
56    pub fn suspec(&mut self) -> SUSPEC_W<0> {
57        SUSPEC_W::new(self)
58    }
59    #[doc = "Bit 1 - MSOF Interrupt Enable Clear"]
60    #[inline(always)]
61    #[must_use]
62    pub fn msofec(&mut self) -> MSOFEC_W<1> {
63        MSOFEC_W::new(self)
64    }
65    #[doc = "Bit 2 - SOF Interrupt Enable Clear"]
66    #[inline(always)]
67    #[must_use]
68    pub fn sofec(&mut self) -> SOFEC_W<2> {
69        SOFEC_W::new(self)
70    }
71    #[doc = "Bit 3 - EORST Interrupt Enable Clear"]
72    #[inline(always)]
73    #[must_use]
74    pub fn eorstec(&mut self) -> EORSTEC_W<3> {
75        EORSTEC_W::new(self)
76    }
77    #[doc = "Bit 4 - WAKEUP Interrupt Enable Clear"]
78    #[inline(always)]
79    #[must_use]
80    pub fn wakeupec(&mut self) -> WAKEUPEC_W<4> {
81        WAKEUPEC_W::new(self)
82    }
83    #[doc = "Bit 5 - EORSM Interrupt Enable Clear"]
84    #[inline(always)]
85    #[must_use]
86    pub fn eorsmec(&mut self) -> EORSMEC_W<5> {
87        EORSMEC_W::new(self)
88    }
89    #[doc = "Bit 6 - UPRSM Interrupt Enable Clear"]
90    #[inline(always)]
91    #[must_use]
92    pub fn uprsmec(&mut self) -> UPRSMEC_W<6> {
93        UPRSMEC_W::new(self)
94    }
95    #[doc = "Bit 12 - EP0INT Interrupt Enable Clear"]
96    #[inline(always)]
97    #[must_use]
98    pub fn ep0intec(&mut self) -> EP0INTEC_W<12> {
99        EP0INTEC_W::new(self)
100    }
101    #[doc = "Bit 13 - EP1INT Interrupt Enable Clear"]
102    #[inline(always)]
103    #[must_use]
104    pub fn ep1intec(&mut self) -> EP1INTEC_W<13> {
105        EP1INTEC_W::new(self)
106    }
107    #[doc = "Bit 14 - EP2INT Interrupt Enable Clear"]
108    #[inline(always)]
109    #[must_use]
110    pub fn ep2intec(&mut self) -> EP2INTEC_W<14> {
111        EP2INTEC_W::new(self)
112    }
113    #[doc = "Bit 15 - EP3INT Interrupt Enable Clear"]
114    #[inline(always)]
115    #[must_use]
116    pub fn ep3intec(&mut self) -> EP3INTEC_W<15> {
117        EP3INTEC_W::new(self)
118    }
119    #[doc = "Bit 16 - EP4INT Interrupt Enable Clear"]
120    #[inline(always)]
121    #[must_use]
122    pub fn ep4intec(&mut self) -> EP4INTEC_W<16> {
123        EP4INTEC_W::new(self)
124    }
125    #[doc = "Bit 17 - EP5INT Interrupt Enable Clear"]
126    #[inline(always)]
127    #[must_use]
128    pub fn ep5intec(&mut self) -> EP5INTEC_W<17> {
129        EP5INTEC_W::new(self)
130    }
131    #[doc = "Bit 18 - EP6INT Interrupt Enable Clear"]
132    #[inline(always)]
133    #[must_use]
134    pub fn ep6intec(&mut self) -> EP6INTEC_W<18> {
135        EP6INTEC_W::new(self)
136    }
137    #[doc = "Bit 19 - EP7INT Interrupt Enable Clear"]
138    #[inline(always)]
139    #[must_use]
140    pub fn ep7intec(&mut self) -> EP7INTEC_W<19> {
141        EP7INTEC_W::new(self)
142    }
143    #[doc = "Writes raw bits to the register."]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.0.bits(bits);
147        self
148    }
149}
150#[doc = "Device Global Interrupt Enable Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [udinteclr](index.html) module"]
151pub struct UDINTECLR_SPEC;
152impl crate::RegisterSpec for UDINTECLR_SPEC {
153    type Ux = u32;
154}
155#[doc = "`write(|w| ..)` method takes [udinteclr::W](W) writer structure"]
156impl crate::Writable for UDINTECLR_SPEC {
157    type Writer = W;
158    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
159    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
160}
161#[doc = "`reset()` method sets UDINTECLR to value 0"]
162impl crate::Resettable for UDINTECLR_SPEC {
163    const RESET_VALUE: Self::Ux = 0;
164}
atsam4ls8a_pac/usbc/udinteclr.rs

atsam4ls8a_pac/usbc/
udinteclr.rs
