atsam4ls8a_pac/usbc/
upsta2.rs

1#[doc = "Register `UPSTA2` reader"]
2pub struct R(crate::R<UPSTA2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UPSTA2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UPSTA2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UPSTA2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXINI` reader - Received IN Data Interrupt"]
17pub type RXINI_R = crate::BitReader<bool>;
18#[doc = "Field `TXOUTI` reader - Transmitted OUT Data Interrupt"]
19pub type TXOUTI_R = crate::BitReader<bool>;
20#[doc = "Field `TXSTPI` reader - Transmitted SETUP Interrupt"]
21pub type TXSTPI_R = crate::BitReader<bool>;
22#[doc = "Field `PERRI` reader - Pipe Error Interrupt"]
23pub type PERRI_R = crate::BitReader<bool>;
24#[doc = "Field `NAKEDI` reader - NAKed Interrupt"]
25pub type NAKEDI_R = crate::BitReader<bool>;
26#[doc = "Field `ERRORFI` reader - Errorflow Interrupt"]
27pub type ERRORFI_R = crate::BitReader<bool>;
28#[doc = "Field `RXSTALLDI` reader - Received STALLed Interrupt"]
29pub type RXSTALLDI_R = crate::BitReader<bool>;
30#[doc = "Field `DTSEQ` reader - Data Toggle Sequence"]
31pub type DTSEQ_R = crate::FieldReader<u8, u8>;
32#[doc = "Field `RAMACERI` reader - Ram Access Error Interrupt"]
33pub type RAMACERI_R = crate::BitReader<bool>;
34#[doc = "Field `NBUSYBK` reader - Number of Busy Bank"]
35pub type NBUSYBK_R = crate::FieldReader<u8, u8>;
36#[doc = "Field `CURRBK` reader - Current Bank"]
37pub type CURRBK_R = crate::FieldReader<u8, u8>;
38impl R {
39    #[doc = "Bit 0 - Received IN Data Interrupt"]
40    #[inline(always)]
41    pub fn rxini(&self) -> RXINI_R {
42        RXINI_R::new((self.bits & 1) != 0)
43    }
44    #[doc = "Bit 1 - Transmitted OUT Data Interrupt"]
45    #[inline(always)]
46    pub fn txouti(&self) -> TXOUTI_R {
47        TXOUTI_R::new(((self.bits >> 1) & 1) != 0)
48    }
49    #[doc = "Bit 2 - Transmitted SETUP Interrupt"]
50    #[inline(always)]
51    pub fn txstpi(&self) -> TXSTPI_R {
52        TXSTPI_R::new(((self.bits >> 2) & 1) != 0)
53    }
54    #[doc = "Bit 3 - Pipe Error Interrupt"]
55    #[inline(always)]
56    pub fn perri(&self) -> PERRI_R {
57        PERRI_R::new(((self.bits >> 3) & 1) != 0)
58    }
59    #[doc = "Bit 4 - NAKed Interrupt"]
60    #[inline(always)]
61    pub fn nakedi(&self) -> NAKEDI_R {
62        NAKEDI_R::new(((self.bits >> 4) & 1) != 0)
63    }
64    #[doc = "Bit 5 - Errorflow Interrupt"]
65    #[inline(always)]
66    pub fn errorfi(&self) -> ERRORFI_R {
67        ERRORFI_R::new(((self.bits >> 5) & 1) != 0)
68    }
69    #[doc = "Bit 6 - Received STALLed Interrupt"]
70    #[inline(always)]
71    pub fn rxstalldi(&self) -> RXSTALLDI_R {
72        RXSTALLDI_R::new(((self.bits >> 6) & 1) != 0)
73    }
74    #[doc = "Bits 8:9 - Data Toggle Sequence"]
75    #[inline(always)]
76    pub fn dtseq(&self) -> DTSEQ_R {
77        DTSEQ_R::new(((self.bits >> 8) & 3) as u8)
78    }
79    #[doc = "Bit 10 - Ram Access Error Interrupt"]
80    #[inline(always)]
81    pub fn ramaceri(&self) -> RAMACERI_R {
82        RAMACERI_R::new(((self.bits >> 10) & 1) != 0)
83    }
84    #[doc = "Bits 12:13 - Number of Busy Bank"]
85    #[inline(always)]
86    pub fn nbusybk(&self) -> NBUSYBK_R {
87        NBUSYBK_R::new(((self.bits >> 12) & 3) as u8)
88    }
89    #[doc = "Bits 14:15 - Current Bank"]
90    #[inline(always)]
91    pub fn currbk(&self) -> CURRBK_R {
92        CURRBK_R::new(((self.bits >> 14) & 3) as u8)
93    }
94}
95#[doc = "Pipe Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [upsta2](index.html) module"]
96pub struct UPSTA2_SPEC;
97impl crate::RegisterSpec for UPSTA2_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [upsta2::R](R) reader structure"]
101impl crate::Readable for UPSTA2_SPEC {
102    type Reader = R;
103}
104#[doc = "`reset()` method sets UPSTA2 to value 0"]
105impl crate::Resettable for UPSTA2_SPEC {
106    const RESET_VALUE: Self::Ux = 0;
107}
atsam4ls8a_pac/usbc/upsta2.rs

atsam4ls8a_pac/usbc/
upsta2.rs
