1#[doc = "Register `CR` reader"]
2pub struct R(crate::R<CR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CR` writer"]
17pub struct W(crate::W<CR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SEN` reader - Slave Enable"]
38pub type SEN_R = crate::BitReader<bool>;
39#[doc = "Field `SEN` writer - Slave Enable"]
40pub type SEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
41#[doc = "Field `SMEN` reader - SMBus Mode Enable"]
42pub type SMEN_R = crate::BitReader<bool>;
43#[doc = "Field `SMEN` writer - SMBus Mode Enable"]
44pub type SMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
45#[doc = "Field `SMATCH` reader - Slave Address Match"]
46pub type SMATCH_R = crate::BitReader<bool>;
47#[doc = "Field `SMATCH` writer - Slave Address Match"]
48pub type SMATCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
49#[doc = "Field `GCMATCH` reader - General Call Address Match"]
50pub type GCMATCH_R = crate::BitReader<bool>;
51#[doc = "Field `GCMATCH` writer - General Call Address Match"]
52pub type GCMATCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
53#[doc = "Field `STREN` reader - Clock Stretch Enable"]
54pub type STREN_R = crate::BitReader<bool>;
55#[doc = "Field `STREN` writer - Clock Stretch Enable"]
56pub type STREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
57#[doc = "Field `SWRST` reader - Software Reset"]
58pub type SWRST_R = crate::BitReader<bool>;
59#[doc = "Field `SWRST` writer - Software Reset"]
60pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
61#[doc = "Field `SMBALERT` reader - SMBus Alert"]
62pub type SMBALERT_R = crate::BitReader<bool>;
63#[doc = "Field `SMBALERT` writer - SMBus Alert"]
64pub type SMBALERT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
65#[doc = "Field `SMDA` reader - SMBus Default Address"]
66pub type SMDA_R = crate::BitReader<bool>;
67#[doc = "Field `SMDA` writer - SMBus Default Address"]
68pub type SMDA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
69#[doc = "Field `SMHH` reader - SMBus Host Header"]
70pub type SMHH_R = crate::BitReader<bool>;
71#[doc = "Field `SMHH` writer - SMBus Host Header"]
72pub type SMHH_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
73#[doc = "Field `PECEN` reader - Packet Error Checking Enable"]
74pub type PECEN_R = crate::BitReader<bool>;
75#[doc = "Field `PECEN` writer - Packet Error Checking Enable"]
76pub type PECEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
77#[doc = "Field `ACK` reader - Slave Receiver Data Phase ACK Value"]
78pub type ACK_R = crate::BitReader<bool>;
79#[doc = "Field `ACK` writer - Slave Receiver Data Phase ACK Value"]
80pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
81#[doc = "Field `CUP` reader - NBYTES Count Up"]
82pub type CUP_R = crate::BitReader<bool>;
83#[doc = "Field `CUP` writer - NBYTES Count Up"]
84pub type CUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
85#[doc = "Field `SOAM` reader - Stretch Clock on Address Match"]
86pub type SOAM_R = crate::BitReader<bool>;
87#[doc = "Field `SOAM` writer - Stretch Clock on Address Match"]
88pub type SOAM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
89#[doc = "Field `SODR` reader - Stretch Clock on Data Byte Reception"]
90pub type SODR_R = crate::BitReader<bool>;
91#[doc = "Field `SODR` writer - Stretch Clock on Data Byte Reception"]
92pub type SODR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
93#[doc = "Field `ADR` reader - Slave Address"]
94pub type ADR_R = crate::FieldReader<u16, u16>;
95#[doc = "Field `ADR` writer - Slave Address"]
96pub type ADR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u16, u16, 10, O>;
97#[doc = "Field `TENBIT` reader - Ten Bit Address Match"]
98pub type TENBIT_R = crate::BitReader<bool>;
99#[doc = "Field `TENBIT` writer - Ten Bit Address Match"]
100pub type TENBIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
101#[doc = "Field `BRIDGE` reader - Bridge Control Enable"]
102pub type BRIDGE_R = crate::BitReader<bool>;
103#[doc = "Field `BRIDGE` writer - Bridge Control Enable"]
104pub type BRIDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, bool, O>;
105impl R {
106 #[doc = "Bit 0 - Slave Enable"]
107 #[inline(always)]
108 pub fn sen(&self) -> SEN_R {
109 SEN_R::new((self.bits & 1) != 0)
110 }
111 #[doc = "Bit 1 - SMBus Mode Enable"]
112 #[inline(always)]
113 pub fn smen(&self) -> SMEN_R {
114 SMEN_R::new(((self.bits >> 1) & 1) != 0)
115 }
116 #[doc = "Bit 2 - Slave Address Match"]
117 #[inline(always)]
118 pub fn smatch(&self) -> SMATCH_R {
119 SMATCH_R::new(((self.bits >> 2) & 1) != 0)
120 }
121 #[doc = "Bit 3 - General Call Address Match"]
122 #[inline(always)]
123 pub fn gcmatch(&self) -> GCMATCH_R {
124 GCMATCH_R::new(((self.bits >> 3) & 1) != 0)
125 }
126 #[doc = "Bit 4 - Clock Stretch Enable"]
127 #[inline(always)]
128 pub fn stren(&self) -> STREN_R {
129 STREN_R::new(((self.bits >> 4) & 1) != 0)
130 }
131 #[doc = "Bit 7 - Software Reset"]
132 #[inline(always)]
133 pub fn swrst(&self) -> SWRST_R {
134 SWRST_R::new(((self.bits >> 7) & 1) != 0)
135 }
136 #[doc = "Bit 8 - SMBus Alert"]
137 #[inline(always)]
138 pub fn smbalert(&self) -> SMBALERT_R {
139 SMBALERT_R::new(((self.bits >> 8) & 1) != 0)
140 }
141 #[doc = "Bit 9 - SMBus Default Address"]
142 #[inline(always)]
143 pub fn smda(&self) -> SMDA_R {
144 SMDA_R::new(((self.bits >> 9) & 1) != 0)
145 }
146 #[doc = "Bit 10 - SMBus Host Header"]
147 #[inline(always)]
148 pub fn smhh(&self) -> SMHH_R {
149 SMHH_R::new(((self.bits >> 10) & 1) != 0)
150 }
151 #[doc = "Bit 11 - Packet Error Checking Enable"]
152 #[inline(always)]
153 pub fn pecen(&self) -> PECEN_R {
154 PECEN_R::new(((self.bits >> 11) & 1) != 0)
155 }
156 #[doc = "Bit 12 - Slave Receiver Data Phase ACK Value"]
157 #[inline(always)]
158 pub fn ack(&self) -> ACK_R {
159 ACK_R::new(((self.bits >> 12) & 1) != 0)
160 }
161 #[doc = "Bit 13 - NBYTES Count Up"]
162 #[inline(always)]
163 pub fn cup(&self) -> CUP_R {
164 CUP_R::new(((self.bits >> 13) & 1) != 0)
165 }
166 #[doc = "Bit 14 - Stretch Clock on Address Match"]
167 #[inline(always)]
168 pub fn soam(&self) -> SOAM_R {
169 SOAM_R::new(((self.bits >> 14) & 1) != 0)
170 }
171 #[doc = "Bit 15 - Stretch Clock on Data Byte Reception"]
172 #[inline(always)]
173 pub fn sodr(&self) -> SODR_R {
174 SODR_R::new(((self.bits >> 15) & 1) != 0)
175 }
176 #[doc = "Bits 16:25 - Slave Address"]
177 #[inline(always)]
178 pub fn adr(&self) -> ADR_R {
179 ADR_R::new(((self.bits >> 16) & 0x03ff) as u16)
180 }
181 #[doc = "Bit 26 - Ten Bit Address Match"]
182 #[inline(always)]
183 pub fn tenbit(&self) -> TENBIT_R {
184 TENBIT_R::new(((self.bits >> 26) & 1) != 0)
185 }
186 #[doc = "Bit 27 - Bridge Control Enable"]
187 #[inline(always)]
188 pub fn bridge(&self) -> BRIDGE_R {
189 BRIDGE_R::new(((self.bits >> 27) & 1) != 0)
190 }
191}
192impl W {
193 #[doc = "Bit 0 - Slave Enable"]
194 #[inline(always)]
195 #[must_use]
196 pub fn sen(&mut self) -> SEN_W<0> {
197 SEN_W::new(self)
198 }
199 #[doc = "Bit 1 - SMBus Mode Enable"]
200 #[inline(always)]
201 #[must_use]
202 pub fn smen(&mut self) -> SMEN_W<1> {
203 SMEN_W::new(self)
204 }
205 #[doc = "Bit 2 - Slave Address Match"]
206 #[inline(always)]
207 #[must_use]
208 pub fn smatch(&mut self) -> SMATCH_W<2> {
209 SMATCH_W::new(self)
210 }
211 #[doc = "Bit 3 - General Call Address Match"]
212 #[inline(always)]
213 #[must_use]
214 pub fn gcmatch(&mut self) -> GCMATCH_W<3> {
215 GCMATCH_W::new(self)
216 }
217 #[doc = "Bit 4 - Clock Stretch Enable"]
218 #[inline(always)]
219 #[must_use]
220 pub fn stren(&mut self) -> STREN_W<4> {
221 STREN_W::new(self)
222 }
223 #[doc = "Bit 7 - Software Reset"]
224 #[inline(always)]
225 #[must_use]
226 pub fn swrst(&mut self) -> SWRST_W<7> {
227 SWRST_W::new(self)
228 }
229 #[doc = "Bit 8 - SMBus Alert"]
230 #[inline(always)]
231 #[must_use]
232 pub fn smbalert(&mut self) -> SMBALERT_W<8> {
233 SMBALERT_W::new(self)
234 }
235 #[doc = "Bit 9 - SMBus Default Address"]
236 #[inline(always)]
237 #[must_use]
238 pub fn smda(&mut self) -> SMDA_W<9> {
239 SMDA_W::new(self)
240 }
241 #[doc = "Bit 10 - SMBus Host Header"]
242 #[inline(always)]
243 #[must_use]
244 pub fn smhh(&mut self) -> SMHH_W<10> {
245 SMHH_W::new(self)
246 }
247 #[doc = "Bit 11 - Packet Error Checking Enable"]
248 #[inline(always)]
249 #[must_use]
250 pub fn pecen(&mut self) -> PECEN_W<11> {
251 PECEN_W::new(self)
252 }
253 #[doc = "Bit 12 - Slave Receiver Data Phase ACK Value"]
254 #[inline(always)]
255 #[must_use]
256 pub fn ack(&mut self) -> ACK_W<12> {
257 ACK_W::new(self)
258 }
259 #[doc = "Bit 13 - NBYTES Count Up"]
260 #[inline(always)]
261 #[must_use]
262 pub fn cup(&mut self) -> CUP_W<13> {
263 CUP_W::new(self)
264 }
265 #[doc = "Bit 14 - Stretch Clock on Address Match"]
266 #[inline(always)]
267 #[must_use]
268 pub fn soam(&mut self) -> SOAM_W<14> {
269 SOAM_W::new(self)
270 }
271 #[doc = "Bit 15 - Stretch Clock on Data Byte Reception"]
272 #[inline(always)]
273 #[must_use]
274 pub fn sodr(&mut self) -> SODR_W<15> {
275 SODR_W::new(self)
276 }
277 #[doc = "Bits 16:25 - Slave Address"]
278 #[inline(always)]
279 #[must_use]
280 pub fn adr(&mut self) -> ADR_W<16> {
281 ADR_W::new(self)
282 }
283 #[doc = "Bit 26 - Ten Bit Address Match"]
284 #[inline(always)]
285 #[must_use]
286 pub fn tenbit(&mut self) -> TENBIT_W<26> {
287 TENBIT_W::new(self)
288 }
289 #[doc = "Bit 27 - Bridge Control Enable"]
290 #[inline(always)]
291 #[must_use]
292 pub fn bridge(&mut self) -> BRIDGE_W<27> {
293 BRIDGE_W::new(self)
294 }
295 #[doc = "Writes raw bits to the register."]
296 #[inline(always)]
297 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
298 self.0.bits(bits);
299 self
300 }
301}
302#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"]
303pub struct CR_SPEC;
304impl crate::RegisterSpec for CR_SPEC {
305 type Ux = u32;
306}
307#[doc = "`read()` method returns [cr::R](R) reader structure"]
308impl crate::Readable for CR_SPEC {
309 type Reader = R;
310}
311#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"]
312impl crate::Writable for CR_SPEC {
313 type Writer = W;
314 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
315 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
316}
317#[doc = "`reset()` method sets CR to value 0"]
318impl crate::Resettable for CR_SPEC {
319 const RESET_VALUE: Self::Ux = 0;
320}