atsam4ls2c_pac/ast/
idr.rs

1#[doc = "Register `IDR` writer"]
2pub struct W(crate::W<IDR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IDR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IDR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Overflow\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum OVFSELECT_AW {
25    #[doc = "0: No effect"]
26    _0 = 0,
27    #[doc = "1: Disable Interrupt."]
28    _1 = 1,
29}
30impl From<OVFSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: OVFSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `OVF` writer - Overflow"]
37pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, OVFSELECT_AW, O>;
38impl<'a, const O: u8> OVF_W<'a, O> {
39    #[doc = "No effect"]
40    #[inline(always)]
41    pub fn _0(self) -> &'a mut W {
42        self.variant(OVFSELECT_AW::_0)
43    }
44    #[doc = "Disable Interrupt."]
45    #[inline(always)]
46    pub fn _1(self) -> &'a mut W {
47        self.variant(OVFSELECT_AW::_1)
48    }
49}
50#[doc = "Alarm 0\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum ALARM0SELECT_AW {
53    #[doc = "0: No effect"]
54    _0 = 0,
55    #[doc = "1: Disable interrupt"]
56    _1 = 1,
57}
58impl From<ALARM0SELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: ALARM0SELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `ALARM0` writer - Alarm 0"]
65pub type ALARM0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, ALARM0SELECT_AW, O>;
66impl<'a, const O: u8> ALARM0_W<'a, O> {
67    #[doc = "No effect"]
68    #[inline(always)]
69    pub fn _0(self) -> &'a mut W {
70        self.variant(ALARM0SELECT_AW::_0)
71    }
72    #[doc = "Disable interrupt"]
73    #[inline(always)]
74    pub fn _1(self) -> &'a mut W {
75        self.variant(ALARM0SELECT_AW::_1)
76    }
77}
78#[doc = "Alarm 1\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum ALARM1SELECT_AW {
81    #[doc = "0: No effect"]
82    _0 = 0,
83    #[doc = "1: Disable interrupt"]
84    _1 = 1,
85}
86impl From<ALARM1SELECT_AW> for bool {
87    #[inline(always)]
88    fn from(variant: ALARM1SELECT_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `ALARM1` writer - Alarm 1"]
93pub type ALARM1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, ALARM1SELECT_AW, O>;
94impl<'a, const O: u8> ALARM1_W<'a, O> {
95    #[doc = "No effect"]
96    #[inline(always)]
97    pub fn _0(self) -> &'a mut W {
98        self.variant(ALARM1SELECT_AW::_0)
99    }
100    #[doc = "Disable interrupt"]
101    #[inline(always)]
102    pub fn _1(self) -> &'a mut W {
103        self.variant(ALARM1SELECT_AW::_1)
104    }
105}
106#[doc = "Periodic 0\n\nValue on reset: 0"]
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum PER0SELECT_AW {
109    #[doc = "0: No effet"]
110    _0 = 0,
111    #[doc = "1: Disalbe interrupt"]
112    _1 = 1,
113}
114impl From<PER0SELECT_AW> for bool {
115    #[inline(always)]
116    fn from(variant: PER0SELECT_AW) -> Self {
117        variant as u8 != 0
118    }
119}
120#[doc = "Field `PER0` writer - Periodic 0"]
121pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, PER0SELECT_AW, O>;
122impl<'a, const O: u8> PER0_W<'a, O> {
123    #[doc = "No effet"]
124    #[inline(always)]
125    pub fn _0(self) -> &'a mut W {
126        self.variant(PER0SELECT_AW::_0)
127    }
128    #[doc = "Disalbe interrupt"]
129    #[inline(always)]
130    pub fn _1(self) -> &'a mut W {
131        self.variant(PER0SELECT_AW::_1)
132    }
133}
134#[doc = "Periodic 1\n\nValue on reset: 0"]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum PER1SELECT_AW {
137    #[doc = "0: No effect"]
138    _0 = 0,
139    #[doc = "1: Disable interrupt"]
140    _1 = 1,
141}
142impl From<PER1SELECT_AW> for bool {
143    #[inline(always)]
144    fn from(variant: PER1SELECT_AW) -> Self {
145        variant as u8 != 0
146    }
147}
148#[doc = "Field `PER1` writer - Periodic 1"]
149pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, PER1SELECT_AW, O>;
150impl<'a, const O: u8> PER1_W<'a, O> {
151    #[doc = "No effect"]
152    #[inline(always)]
153    pub fn _0(self) -> &'a mut W {
154        self.variant(PER1SELECT_AW::_0)
155    }
156    #[doc = "Disable interrupt"]
157    #[inline(always)]
158    pub fn _1(self) -> &'a mut W {
159        self.variant(PER1SELECT_AW::_1)
160    }
161}
162#[doc = "AST Ready\n\nValue on reset: 0"]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum READYSELECT_AW {
165    #[doc = "0: No effect"]
166    _0 = 0,
167    #[doc = "1: Disable interrupt"]
168    _1 = 1,
169}
170impl From<READYSELECT_AW> for bool {
171    #[inline(always)]
172    fn from(variant: READYSELECT_AW) -> Self {
173        variant as u8 != 0
174    }
175}
176#[doc = "Field `READY` writer - AST Ready"]
177pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, READYSELECT_AW, O>;
178impl<'a, const O: u8> READY_W<'a, O> {
179    #[doc = "No effect"]
180    #[inline(always)]
181    pub fn _0(self) -> &'a mut W {
182        self.variant(READYSELECT_AW::_0)
183    }
184    #[doc = "Disable interrupt"]
185    #[inline(always)]
186    pub fn _1(self) -> &'a mut W {
187        self.variant(READYSELECT_AW::_1)
188    }
189}
190#[doc = "Clock Ready\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum CLKRDYSELECT_AW {
193    #[doc = "0: No effect"]
194    _0 = 0,
195    #[doc = "1: Disable interrupt"]
196    _1 = 1,
197}
198impl From<CLKRDYSELECT_AW> for bool {
199    #[inline(always)]
200    fn from(variant: CLKRDYSELECT_AW) -> Self {
201        variant as u8 != 0
202    }
203}
204#[doc = "Field `CLKRDY` writer - Clock Ready"]
205pub type CLKRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IDR_SPEC, CLKRDYSELECT_AW, O>;
206impl<'a, const O: u8> CLKRDY_W<'a, O> {
207    #[doc = "No effect"]
208    #[inline(always)]
209    pub fn _0(self) -> &'a mut W {
210        self.variant(CLKRDYSELECT_AW::_0)
211    }
212    #[doc = "Disable interrupt"]
213    #[inline(always)]
214    pub fn _1(self) -> &'a mut W {
215        self.variant(CLKRDYSELECT_AW::_1)
216    }
217}
218impl W {
219    #[doc = "Bit 0 - Overflow"]
220    #[inline(always)]
221    #[must_use]
222    pub fn ovf(&mut self) -> OVF_W<0> {
223        OVF_W::new(self)
224    }
225    #[doc = "Bit 8 - Alarm 0"]
226    #[inline(always)]
227    #[must_use]
228    pub fn alarm0(&mut self) -> ALARM0_W<8> {
229        ALARM0_W::new(self)
230    }
231    #[doc = "Bit 9 - Alarm 1"]
232    #[inline(always)]
233    #[must_use]
234    pub fn alarm1(&mut self) -> ALARM1_W<9> {
235        ALARM1_W::new(self)
236    }
237    #[doc = "Bit 16 - Periodic 0"]
238    #[inline(always)]
239    #[must_use]
240    pub fn per0(&mut self) -> PER0_W<16> {
241        PER0_W::new(self)
242    }
243    #[doc = "Bit 17 - Periodic 1"]
244    #[inline(always)]
245    #[must_use]
246    pub fn per1(&mut self) -> PER1_W<17> {
247        PER1_W::new(self)
248    }
249    #[doc = "Bit 25 - AST Ready"]
250    #[inline(always)]
251    #[must_use]
252    pub fn ready(&mut self) -> READY_W<25> {
253        READY_W::new(self)
254    }
255    #[doc = "Bit 29 - Clock Ready"]
256    #[inline(always)]
257    #[must_use]
258    pub fn clkrdy(&mut self) -> CLKRDY_W<29> {
259        CLKRDY_W::new(self)
260    }
261    #[doc = "Writes raw bits to the register."]
262    #[inline(always)]
263    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
264        self.0.bits(bits);
265        self
266    }
267}
268#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"]
269pub struct IDR_SPEC;
270impl crate::RegisterSpec for IDR_SPEC {
271    type Ux = u32;
272}
273#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"]
274impl crate::Writable for IDR_SPEC {
275    type Writer = W;
276    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
277    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
278}
279#[doc = "`reset()` method sets IDR to value 0"]
280impl crate::Resettable for IDR_SPEC {
281    const RESET_VALUE: Self::Ux = 0;
282}
atsam4ls2c_pac/ast/idr.rs

atsam4ls2c_pac/ast/
idr.rs
