atsam4ls2c_pac/adcife/
seqcfg.rs1#[doc = "Register `SEQCFG` reader"]
2pub struct R(crate::R<SEQCFG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SEQCFG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SEQCFG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SEQCFG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `SEQCFG` writer"]
17pub struct W(crate::W<SEQCFG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SEQCFG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SEQCFG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SEQCFG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `HWLA` reader - Half word left adjust"]
38pub type HWLA_R = crate::BitReader<bool>;
39#[doc = "Field `HWLA` writer - Half word left adjust"]
40pub type HWLA_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEQCFG_SPEC, bool, O>;
41#[doc = "Field `BIPOLAR` reader - Bipolar Mode"]
42pub type BIPOLAR_R = crate::BitReader<bool>;
43#[doc = "Field `BIPOLAR` writer - Bipolar Mode"]
44pub type BIPOLAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEQCFG_SPEC, bool, O>;
45#[doc = "Field `GAIN` reader - Gain factor"]
46pub type GAIN_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `GAIN` writer - Gain factor"]
48pub type GAIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCFG_SPEC, u8, u8, 3, O>;
49#[doc = "Field `GCOMP` reader - Gain Compensation"]
50pub type GCOMP_R = crate::BitReader<bool>;
51#[doc = "Field `GCOMP` writer - Gain Compensation"]
52pub type GCOMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEQCFG_SPEC, bool, O>;
53#[doc = "Field `TRGSEL` reader - Trigger selection"]
54pub type TRGSEL_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `TRGSEL` writer - Trigger selection"]
56pub type TRGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCFG_SPEC, u8, u8, 3, O>;
57#[doc = "Field `RES` reader - Resolution"]
58pub type RES_R = crate::BitReader<bool>;
59#[doc = "Field `RES` writer - Resolution"]
60pub type RES_W<'a, const O: u8> = crate::BitWriter<'a, u32, SEQCFG_SPEC, bool, O>;
61#[doc = "Field `INTERNAL` reader - Internal Voltage Source Selection"]
62pub type INTERNAL_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `INTERNAL` writer - Internal Voltage Source Selection"]
64pub type INTERNAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCFG_SPEC, u8, u8, 2, O>;
65#[doc = "Field `MUXPOS` reader - MUX selection on Positive ADC input channel"]
66pub type MUXPOS_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `MUXPOS` writer - MUX selection on Positive ADC input channel"]
68pub type MUXPOS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCFG_SPEC, u8, u8, 4, O>;
69#[doc = "Field `MUXNEG` reader - MUX selection on Negative ADC input channel"]
70pub type MUXNEG_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `MUXNEG` writer - MUX selection on Negative ADC input channel"]
72pub type MUXNEG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCFG_SPEC, u8, u8, 3, O>;
73#[doc = "Field `ZOOMRANGE` reader - Zoom shift/unipolar reference source selection"]
74pub type ZOOMRANGE_R = crate::FieldReader<u8, u8>;
75#[doc = "Field `ZOOMRANGE` writer - Zoom shift/unipolar reference source selection"]
76pub type ZOOMRANGE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCFG_SPEC, u8, u8, 3, O>;
77impl R {
78 #[doc = "Bit 0 - Half word left adjust"]
79 #[inline(always)]
80 pub fn hwla(&self) -> HWLA_R {
81 HWLA_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 2 - Bipolar Mode"]
84 #[inline(always)]
85 pub fn bipolar(&self) -> BIPOLAR_R {
86 BIPOLAR_R::new(((self.bits >> 2) & 1) != 0)
87 }
88 #[doc = "Bits 4:6 - Gain factor"]
89 #[inline(always)]
90 pub fn gain(&self) -> GAIN_R {
91 GAIN_R::new(((self.bits >> 4) & 7) as u8)
92 }
93 #[doc = "Bit 7 - Gain Compensation"]
94 #[inline(always)]
95 pub fn gcomp(&self) -> GCOMP_R {
96 GCOMP_R::new(((self.bits >> 7) & 1) != 0)
97 }
98 #[doc = "Bits 8:10 - Trigger selection"]
99 #[inline(always)]
100 pub fn trgsel(&self) -> TRGSEL_R {
101 TRGSEL_R::new(((self.bits >> 8) & 7) as u8)
102 }
103 #[doc = "Bit 12 - Resolution"]
104 #[inline(always)]
105 pub fn res(&self) -> RES_R {
106 RES_R::new(((self.bits >> 12) & 1) != 0)
107 }
108 #[doc = "Bits 14:15 - Internal Voltage Source Selection"]
109 #[inline(always)]
110 pub fn internal(&self) -> INTERNAL_R {
111 INTERNAL_R::new(((self.bits >> 14) & 3) as u8)
112 }
113 #[doc = "Bits 16:19 - MUX selection on Positive ADC input channel"]
114 #[inline(always)]
115 pub fn muxpos(&self) -> MUXPOS_R {
116 MUXPOS_R::new(((self.bits >> 16) & 0x0f) as u8)
117 }
118 #[doc = "Bits 20:22 - MUX selection on Negative ADC input channel"]
119 #[inline(always)]
120 pub fn muxneg(&self) -> MUXNEG_R {
121 MUXNEG_R::new(((self.bits >> 20) & 7) as u8)
122 }
123 #[doc = "Bits 28:30 - Zoom shift/unipolar reference source selection"]
124 #[inline(always)]
125 pub fn zoomrange(&self) -> ZOOMRANGE_R {
126 ZOOMRANGE_R::new(((self.bits >> 28) & 7) as u8)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Half word left adjust"]
131 #[inline(always)]
132 #[must_use]
133 pub fn hwla(&mut self) -> HWLA_W<0> {
134 HWLA_W::new(self)
135 }
136 #[doc = "Bit 2 - Bipolar Mode"]
137 #[inline(always)]
138 #[must_use]
139 pub fn bipolar(&mut self) -> BIPOLAR_W<2> {
140 BIPOLAR_W::new(self)
141 }
142 #[doc = "Bits 4:6 - Gain factor"]
143 #[inline(always)]
144 #[must_use]
145 pub fn gain(&mut self) -> GAIN_W<4> {
146 GAIN_W::new(self)
147 }
148 #[doc = "Bit 7 - Gain Compensation"]
149 #[inline(always)]
150 #[must_use]
151 pub fn gcomp(&mut self) -> GCOMP_W<7> {
152 GCOMP_W::new(self)
153 }
154 #[doc = "Bits 8:10 - Trigger selection"]
155 #[inline(always)]
156 #[must_use]
157 pub fn trgsel(&mut self) -> TRGSEL_W<8> {
158 TRGSEL_W::new(self)
159 }
160 #[doc = "Bit 12 - Resolution"]
161 #[inline(always)]
162 #[must_use]
163 pub fn res(&mut self) -> RES_W<12> {
164 RES_W::new(self)
165 }
166 #[doc = "Bits 14:15 - Internal Voltage Source Selection"]
167 #[inline(always)]
168 #[must_use]
169 pub fn internal(&mut self) -> INTERNAL_W<14> {
170 INTERNAL_W::new(self)
171 }
172 #[doc = "Bits 16:19 - MUX selection on Positive ADC input channel"]
173 #[inline(always)]
174 #[must_use]
175 pub fn muxpos(&mut self) -> MUXPOS_W<16> {
176 MUXPOS_W::new(self)
177 }
178 #[doc = "Bits 20:22 - MUX selection on Negative ADC input channel"]
179 #[inline(always)]
180 #[must_use]
181 pub fn muxneg(&mut self) -> MUXNEG_W<20> {
182 MUXNEG_W::new(self)
183 }
184 #[doc = "Bits 28:30 - Zoom shift/unipolar reference source selection"]
185 #[inline(always)]
186 #[must_use]
187 pub fn zoomrange(&mut self) -> ZOOMRANGE_W<28> {
188 ZOOMRANGE_W::new(self)
189 }
190 #[doc = "Writes raw bits to the register."]
191 #[inline(always)]
192 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
193 self.0.bits(bits);
194 self
195 }
196}
197#[doc = "Sequencer Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqcfg](index.html) module"]
198pub struct SEQCFG_SPEC;
199impl crate::RegisterSpec for SEQCFG_SPEC {
200 type Ux = u32;
201}
202#[doc = "`read()` method returns [seqcfg::R](R) reader structure"]
203impl crate::Readable for SEQCFG_SPEC {
204 type Reader = R;
205}
206#[doc = "`write(|w| ..)` method takes [seqcfg::W](W) writer structure"]
207impl crate::Writable for SEQCFG_SPEC {
208 type Writer = W;
209 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
211}
212#[doc = "`reset()` method sets SEQCFG to value 0"]
213impl crate::Resettable for SEQCFG_SPEC {
214 const RESET_VALUE: Self::Ux = 0;
215}