atsam4ls2c_pac/usbc/
upcon7.rs

1#[doc = "Register `UPCON7` reader"]
2pub struct R(crate::R<UPCON7_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UPCON7_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UPCON7_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UPCON7_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `RXINE` reader - RXIN Interrupt Enable"]
17pub type RXINE_R = crate::BitReader<bool>;
18#[doc = "Field `TXOUTE` reader - TXOUT Interrupt Enable"]
19pub type TXOUTE_R = crate::BitReader<bool>;
20#[doc = "Field `TXSTPE` reader - TXSTP Interrupt Enable"]
21pub type TXSTPE_R = crate::BitReader<bool>;
22#[doc = "Field `PERRE` reader - PERR Interrupt Enable"]
23pub type PERRE_R = crate::BitReader<bool>;
24#[doc = "Field `NAKEDE` reader - NAKED Interrupt Enable"]
25pub type NAKEDE_R = crate::BitReader<bool>;
26#[doc = "Field `ERRORFIE` reader - ERRORFI Interrupt Enable"]
27pub type ERRORFIE_R = crate::BitReader<bool>;
28#[doc = "Field `RXSTALLDE` reader - RXTALLD Interrupt Enable"]
29pub type RXSTALLDE_R = crate::BitReader<bool>;
30#[doc = "Field `RAMACERE` reader - RAMACER Interrupt Enable"]
31pub type RAMACERE_R = crate::BitReader<bool>;
32#[doc = "Field `NBUSYBKE` reader - NBUSYBKInterrupt Enable"]
33pub type NBUSYBKE_R = crate::BitReader<bool>;
34#[doc = "Field `FIFOCON` reader - FIFO Control"]
35pub type FIFOCON_R = crate::BitReader<bool>;
36#[doc = "Field `PFREEZE` reader - Pipe Freeze"]
37pub type PFREEZE_R = crate::BitReader<bool>;
38#[doc = "Field `INITDTGL` reader - Data Toggle Initialization"]
39pub type INITDTGL_R = crate::BitReader<bool>;
40#[doc = "Field `INITBK` reader - Bank Initialization"]
41pub type INITBK_R = crate::BitReader<bool>;
42impl R {
43    #[doc = "Bit 0 - RXIN Interrupt Enable"]
44    #[inline(always)]
45    pub fn rxine(&self) -> RXINE_R {
46        RXINE_R::new((self.bits & 1) != 0)
47    }
48    #[doc = "Bit 1 - TXOUT Interrupt Enable"]
49    #[inline(always)]
50    pub fn txoute(&self) -> TXOUTE_R {
51        TXOUTE_R::new(((self.bits >> 1) & 1) != 0)
52    }
53    #[doc = "Bit 2 - TXSTP Interrupt Enable"]
54    #[inline(always)]
55    pub fn txstpe(&self) -> TXSTPE_R {
56        TXSTPE_R::new(((self.bits >> 2) & 1) != 0)
57    }
58    #[doc = "Bit 3 - PERR Interrupt Enable"]
59    #[inline(always)]
60    pub fn perre(&self) -> PERRE_R {
61        PERRE_R::new(((self.bits >> 3) & 1) != 0)
62    }
63    #[doc = "Bit 4 - NAKED Interrupt Enable"]
64    #[inline(always)]
65    pub fn nakede(&self) -> NAKEDE_R {
66        NAKEDE_R::new(((self.bits >> 4) & 1) != 0)
67    }
68    #[doc = "Bit 5 - ERRORFI Interrupt Enable"]
69    #[inline(always)]
70    pub fn errorfie(&self) -> ERRORFIE_R {
71        ERRORFIE_R::new(((self.bits >> 5) & 1) != 0)
72    }
73    #[doc = "Bit 6 - RXTALLD Interrupt Enable"]
74    #[inline(always)]
75    pub fn rxstallde(&self) -> RXSTALLDE_R {
76        RXSTALLDE_R::new(((self.bits >> 6) & 1) != 0)
77    }
78    #[doc = "Bit 10 - RAMACER Interrupt Enable"]
79    #[inline(always)]
80    pub fn ramacere(&self) -> RAMACERE_R {
81        RAMACERE_R::new(((self.bits >> 10) & 1) != 0)
82    }
83    #[doc = "Bit 12 - NBUSYBKInterrupt Enable"]
84    #[inline(always)]
85    pub fn nbusybke(&self) -> NBUSYBKE_R {
86        NBUSYBKE_R::new(((self.bits >> 12) & 1) != 0)
87    }
88    #[doc = "Bit 14 - FIFO Control"]
89    #[inline(always)]
90    pub fn fifocon(&self) -> FIFOCON_R {
91        FIFOCON_R::new(((self.bits >> 14) & 1) != 0)
92    }
93    #[doc = "Bit 17 - Pipe Freeze"]
94    #[inline(always)]
95    pub fn pfreeze(&self) -> PFREEZE_R {
96        PFREEZE_R::new(((self.bits >> 17) & 1) != 0)
97    }
98    #[doc = "Bit 18 - Data Toggle Initialization"]
99    #[inline(always)]
100    pub fn initdtgl(&self) -> INITDTGL_R {
101        INITDTGL_R::new(((self.bits >> 18) & 1) != 0)
102    }
103    #[doc = "Bit 19 - Bank Initialization"]
104    #[inline(always)]
105    pub fn initbk(&self) -> INITBK_R {
106        INITBK_R::new(((self.bits >> 19) & 1) != 0)
107    }
108}
109#[doc = "Pipe Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [upcon7](index.html) module"]
110pub struct UPCON7_SPEC;
111impl crate::RegisterSpec for UPCON7_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [upcon7::R](R) reader structure"]
115impl crate::Readable for UPCON7_SPEC {
116    type Reader = R;
117}
118#[doc = "`reset()` method sets UPCON7 to value 0"]
119impl crate::Resettable for UPCON7_SPEC {
120    const RESET_VALUE: Self::Ux = 0;
121}
atsam4ls2c_pac/usbc/upcon7.rs

atsam4ls2c_pac/usbc/
upcon7.rs
