atsam4ls2b_pac/bpm/
bpr.rs

1#[doc = "Register `BPR` reader"]
2pub struct R(crate::R<BPR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<BPR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<BPR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<BPR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `BPR` writer"]
17pub struct W(crate::W<BPR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<BPR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<BPR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<BPR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RUNPSPB` reader - Run Mode Power Scaling Preset Bypass"]
38pub type RUNPSPB_R = crate::BitReader<bool>;
39#[doc = "Field `RUNPSPB` writer - Run Mode Power Scaling Preset Bypass"]
40pub type RUNPSPB_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
41#[doc = "Field `PSMPSPB` reader - Power Save Mode Power Scaling Preset Bypass"]
42pub type PSMPSPB_R = crate::BitReader<bool>;
43#[doc = "Field `PSMPSPB` writer - Power Save Mode Power Scaling Preset Bypass"]
44pub type PSMPSPB_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
45#[doc = "Field `SEQSTN` reader - Sequencial Startup from ULP (Active Low)"]
46pub type SEQSTN_R = crate::BitReader<bool>;
47#[doc = "Field `SEQSTN` writer - Sequencial Startup from ULP (Active Low)"]
48pub type SEQSTN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
49#[doc = "Field `PSBTD` reader - Power Scaling Bias Timing Disable"]
50pub type PSBTD_R = crate::BitReader<bool>;
51#[doc = "Field `PSBTD` writer - Power Scaling Bias Timing Disable"]
52pub type PSBTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
53#[doc = "Field `PSHFD` reader - Power Scaling Halt Flash Until VREGOK Disable"]
54pub type PSHFD_R = crate::BitReader<bool>;
55#[doc = "Field `PSHFD` writer - Power Scaling Halt Flash Until VREGOK Disable"]
56pub type PSHFD_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
57#[doc = "Field `DLYRSTD` reader - Delaying Reset Disable"]
58pub type DLYRSTD_R = crate::BitReader<bool>;
59#[doc = "Field `DLYRSTD` writer - Delaying Reset Disable"]
60pub type DLYRSTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
61#[doc = "Field `BIASSEN` reader - Bias Switch Enable"]
62pub type BIASSEN_R = crate::BitReader<bool>;
63#[doc = "Field `BIASSEN` writer - Bias Switch Enable"]
64pub type BIASSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
65#[doc = "Field `LATSEN` reader - Latdel Switch Enable"]
66pub type LATSEN_R = crate::BitReader<bool>;
67#[doc = "Field `LATSEN` writer - Latdel Switch Enable"]
68pub type LATSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
69#[doc = "Field `BOD18CONT` reader - BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes"]
70pub type BOD18CONT_R = crate::BitReader<bool>;
71#[doc = "Field `BOD18CONT` writer - BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes"]
72pub type BOD18CONT_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
73#[doc = "Field `POBS` reader - Pico Uart Observability"]
74pub type POBS_R = crate::BitReader<bool>;
75#[doc = "Field `POBS` writer - Pico Uart Observability"]
76pub type POBS_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
77#[doc = "Field `FFFW` reader - Force Flash Fast Wakeup"]
78pub type FFFW_R = crate::BitReader<bool>;
79#[doc = "Field `FFFW` writer - Force Flash Fast Wakeup"]
80pub type FFFW_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
81#[doc = "Field `FBRDYEN` reader - Flash Bias Ready Enable"]
82pub type FBRDYEN_R = crate::BitReader<bool>;
83#[doc = "Field `FBRDYEN` writer - Flash Bias Ready Enable"]
84pub type FBRDYEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
85#[doc = "Field `FVREFSEN` reader - Flash Vref Switch Enable"]
86pub type FVREFSEN_R = crate::BitReader<bool>;
87#[doc = "Field `FVREFSEN` writer - Flash Vref Switch Enable"]
88pub type FVREFSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BPR_SPEC, bool, O>;
89impl R {
90    #[doc = "Bit 0 - Run Mode Power Scaling Preset Bypass"]
91    #[inline(always)]
92    pub fn runpspb(&self) -> RUNPSPB_R {
93        RUNPSPB_R::new((self.bits & 1) != 0)
94    }
95    #[doc = "Bit 1 - Power Save Mode Power Scaling Preset Bypass"]
96    #[inline(always)]
97    pub fn psmpspb(&self) -> PSMPSPB_R {
98        PSMPSPB_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    #[doc = "Bit 2 - Sequencial Startup from ULP (Active Low)"]
101    #[inline(always)]
102    pub fn seqstn(&self) -> SEQSTN_R {
103        SEQSTN_R::new(((self.bits >> 2) & 1) != 0)
104    }
105    #[doc = "Bit 3 - Power Scaling Bias Timing Disable"]
106    #[inline(always)]
107    pub fn psbtd(&self) -> PSBTD_R {
108        PSBTD_R::new(((self.bits >> 3) & 1) != 0)
109    }
110    #[doc = "Bit 4 - Power Scaling Halt Flash Until VREGOK Disable"]
111    #[inline(always)]
112    pub fn pshfd(&self) -> PSHFD_R {
113        PSHFD_R::new(((self.bits >> 4) & 1) != 0)
114    }
115    #[doc = "Bit 5 - Delaying Reset Disable"]
116    #[inline(always)]
117    pub fn dlyrstd(&self) -> DLYRSTD_R {
118        DLYRSTD_R::new(((self.bits >> 5) & 1) != 0)
119    }
120    #[doc = "Bit 6 - Bias Switch Enable"]
121    #[inline(always)]
122    pub fn biassen(&self) -> BIASSEN_R {
123        BIASSEN_R::new(((self.bits >> 6) & 1) != 0)
124    }
125    #[doc = "Bit 7 - Latdel Switch Enable"]
126    #[inline(always)]
127    pub fn latsen(&self) -> LATSEN_R {
128        LATSEN_R::new(((self.bits >> 7) & 1) != 0)
129    }
130    #[doc = "Bit 8 - BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes"]
131    #[inline(always)]
132    pub fn bod18cont(&self) -> BOD18CONT_R {
133        BOD18CONT_R::new(((self.bits >> 8) & 1) != 0)
134    }
135    #[doc = "Bit 9 - Pico Uart Observability"]
136    #[inline(always)]
137    pub fn pobs(&self) -> POBS_R {
138        POBS_R::new(((self.bits >> 9) & 1) != 0)
139    }
140    #[doc = "Bit 10 - Force Flash Fast Wakeup"]
141    #[inline(always)]
142    pub fn fffw(&self) -> FFFW_R {
143        FFFW_R::new(((self.bits >> 10) & 1) != 0)
144    }
145    #[doc = "Bit 11 - Flash Bias Ready Enable"]
146    #[inline(always)]
147    pub fn fbrdyen(&self) -> FBRDYEN_R {
148        FBRDYEN_R::new(((self.bits >> 11) & 1) != 0)
149    }
150    #[doc = "Bit 12 - Flash Vref Switch Enable"]
151    #[inline(always)]
152    pub fn fvrefsen(&self) -> FVREFSEN_R {
153        FVREFSEN_R::new(((self.bits >> 12) & 1) != 0)
154    }
155}
156impl W {
157    #[doc = "Bit 0 - Run Mode Power Scaling Preset Bypass"]
158    #[inline(always)]
159    #[must_use]
160    pub fn runpspb(&mut self) -> RUNPSPB_W<0> {
161        RUNPSPB_W::new(self)
162    }
163    #[doc = "Bit 1 - Power Save Mode Power Scaling Preset Bypass"]
164    #[inline(always)]
165    #[must_use]
166    pub fn psmpspb(&mut self) -> PSMPSPB_W<1> {
167        PSMPSPB_W::new(self)
168    }
169    #[doc = "Bit 2 - Sequencial Startup from ULP (Active Low)"]
170    #[inline(always)]
171    #[must_use]
172    pub fn seqstn(&mut self) -> SEQSTN_W<2> {
173        SEQSTN_W::new(self)
174    }
175    #[doc = "Bit 3 - Power Scaling Bias Timing Disable"]
176    #[inline(always)]
177    #[must_use]
178    pub fn psbtd(&mut self) -> PSBTD_W<3> {
179        PSBTD_W::new(self)
180    }
181    #[doc = "Bit 4 - Power Scaling Halt Flash Until VREGOK Disable"]
182    #[inline(always)]
183    #[must_use]
184    pub fn pshfd(&mut self) -> PSHFD_W<4> {
185        PSHFD_W::new(self)
186    }
187    #[doc = "Bit 5 - Delaying Reset Disable"]
188    #[inline(always)]
189    #[must_use]
190    pub fn dlyrstd(&mut self) -> DLYRSTD_W<5> {
191        DLYRSTD_W::new(self)
192    }
193    #[doc = "Bit 6 - Bias Switch Enable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn biassen(&mut self) -> BIASSEN_W<6> {
197        BIASSEN_W::new(self)
198    }
199    #[doc = "Bit 7 - Latdel Switch Enable"]
200    #[inline(always)]
201    #[must_use]
202    pub fn latsen(&mut self) -> LATSEN_W<7> {
203        LATSEN_W::new(self)
204    }
205    #[doc = "Bit 8 - BOD18 in continuous mode not disabled in WAIT/RET/BACKUP modes"]
206    #[inline(always)]
207    #[must_use]
208    pub fn bod18cont(&mut self) -> BOD18CONT_W<8> {
209        BOD18CONT_W::new(self)
210    }
211    #[doc = "Bit 9 - Pico Uart Observability"]
212    #[inline(always)]
213    #[must_use]
214    pub fn pobs(&mut self) -> POBS_W<9> {
215        POBS_W::new(self)
216    }
217    #[doc = "Bit 10 - Force Flash Fast Wakeup"]
218    #[inline(always)]
219    #[must_use]
220    pub fn fffw(&mut self) -> FFFW_W<10> {
221        FFFW_W::new(self)
222    }
223    #[doc = "Bit 11 - Flash Bias Ready Enable"]
224    #[inline(always)]
225    #[must_use]
226    pub fn fbrdyen(&mut self) -> FBRDYEN_W<11> {
227        FBRDYEN_W::new(self)
228    }
229    #[doc = "Bit 12 - Flash Vref Switch Enable"]
230    #[inline(always)]
231    #[must_use]
232    pub fn fvrefsen(&mut self) -> FVREFSEN_W<12> {
233        FVREFSEN_W::new(self)
234    }
235    #[doc = "Writes raw bits to the register."]
236    #[inline(always)]
237    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
238        self.0.bits(bits);
239        self
240    }
241}
242#[doc = "Bypass Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bpr](index.html) module"]
243pub struct BPR_SPEC;
244impl crate::RegisterSpec for BPR_SPEC {
245    type Ux = u32;
246}
247#[doc = "`read()` method returns [bpr::R](R) reader structure"]
248impl crate::Readable for BPR_SPEC {
249    type Reader = R;
250}
251#[doc = "`write(|w| ..)` method takes [bpr::W](W) writer structure"]
252impl crate::Writable for BPR_SPEC {
253    type Writer = W;
254    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
255    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
256}
257#[doc = "`reset()` method sets BPR to value 0"]
258impl crate::Resettable for BPR_SPEC {
259    const RESET_VALUE: Self::Ux = 0;
260}
atsam4ls2b_pac/bpm/bpr.rs

atsam4ls2b_pac/bpm/
bpr.rs
