atsam4ls2a_pac/hflashc/
fcr.rs

1#[doc = "Register `FCR` reader"]
2pub struct R(crate::R<FCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FCR` writer"]
17pub struct W(crate::W<FCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FRDY` reader - Flash Ready Interrupt Enable"]
38pub type FRDY_R = crate::BitReader<FRDYSELECT_A>;
39#[doc = "Flash Ready Interrupt Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum FRDYSELECT_A {
42    #[doc = "0: Flash Ready does not generate an interrupt"]
43    _0 = 0,
44    #[doc = "1: Flash Ready generates an interrupt"]
45    _1 = 1,
46}
47impl From<FRDYSELECT_A> for bool {
48    #[inline(always)]
49    fn from(variant: FRDYSELECT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl FRDY_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> FRDYSELECT_A {
57        match self.bits {
58            false => FRDYSELECT_A::_0,
59            true => FRDYSELECT_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == FRDYSELECT_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == FRDYSELECT_A::_1
71    }
72}
73#[doc = "Field `FRDY` writer - Flash Ready Interrupt Enable"]
74pub type FRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCR_SPEC, FRDYSELECT_A, O>;
75impl<'a, const O: u8> FRDY_W<'a, O> {
76    #[doc = "Flash Ready does not generate an interrupt"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(FRDYSELECT_A::_0)
80    }
81    #[doc = "Flash Ready generates an interrupt"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(FRDYSELECT_A::_1)
85    }
86}
87#[doc = "Field `LOCKE` reader - Lock Error Interrupt Enable"]
88pub type LOCKE_R = crate::BitReader<LOCKESELECT_A>;
89#[doc = "Lock Error Interrupt Enable\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum LOCKESELECT_A {
92    #[doc = "0: Lock Error does not generate an interrupt"]
93    _0 = 0,
94    #[doc = "1: Lock Error generates an interrupt"]
95    _1 = 1,
96}
97impl From<LOCKESELECT_A> for bool {
98    #[inline(always)]
99    fn from(variant: LOCKESELECT_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl LOCKE_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> LOCKESELECT_A {
107        match self.bits {
108            false => LOCKESELECT_A::_0,
109            true => LOCKESELECT_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == LOCKESELECT_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == LOCKESELECT_A::_1
121    }
122}
123#[doc = "Field `LOCKE` writer - Lock Error Interrupt Enable"]
124pub type LOCKE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCR_SPEC, LOCKESELECT_A, O>;
125impl<'a, const O: u8> LOCKE_W<'a, O> {
126    #[doc = "Lock Error does not generate an interrupt"]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(LOCKESELECT_A::_0)
130    }
131    #[doc = "Lock Error generates an interrupt"]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(LOCKESELECT_A::_1)
135    }
136}
137#[doc = "Field `PROGE` reader - Programming Error Interrupt Enable"]
138pub type PROGE_R = crate::BitReader<PROGESELECT_A>;
139#[doc = "Programming Error Interrupt Enable\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum PROGESELECT_A {
142    #[doc = "0: Programming Error does not generate an interrupt"]
143    _0 = 0,
144    #[doc = "1: Programming Error generates an interrupt"]
145    _1 = 1,
146}
147impl From<PROGESELECT_A> for bool {
148    #[inline(always)]
149    fn from(variant: PROGESELECT_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl PROGE_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> PROGESELECT_A {
157        match self.bits {
158            false => PROGESELECT_A::_0,
159            true => PROGESELECT_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == PROGESELECT_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == PROGESELECT_A::_1
171    }
172}
173#[doc = "Field `PROGE` writer - Programming Error Interrupt Enable"]
174pub type PROGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCR_SPEC, PROGESELECT_A, O>;
175impl<'a, const O: u8> PROGE_W<'a, O> {
176    #[doc = "Programming Error does not generate an interrupt"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(PROGESELECT_A::_0)
180    }
181    #[doc = "Programming Error generates an interrupt"]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(PROGESELECT_A::_1)
185    }
186}
187#[doc = "Field `FWS` reader - Flash Wait State"]
188pub type FWS_R = crate::BitReader<FWSSELECT_A>;
189#[doc = "Flash Wait State\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum FWSSELECT_A {
192    #[doc = "0: The flash is read with 0 wait states"]
193    _0 = 0,
194    #[doc = "1: The flash is read with 1 wait states"]
195    _1 = 1,
196}
197impl From<FWSSELECT_A> for bool {
198    #[inline(always)]
199    fn from(variant: FWSSELECT_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl FWS_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> FWSSELECT_A {
207        match self.bits {
208            false => FWSSELECT_A::_0,
209            true => FWSSELECT_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == FWSSELECT_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == FWSSELECT_A::_1
221    }
222}
223#[doc = "Field `FWS` writer - Flash Wait State"]
224pub type FWS_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCR_SPEC, FWSSELECT_A, O>;
225impl<'a, const O: u8> FWS_W<'a, O> {
226    #[doc = "The flash is read with 0 wait states"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(FWSSELECT_A::_0)
230    }
231    #[doc = "The flash is read with 1 wait states"]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(FWSSELECT_A::_1)
235    }
236}
237#[doc = "Field `WS1OPT` reader - Wait State 1 Optimization"]
238pub type WS1OPT_R = crate::BitReader<bool>;
239#[doc = "Field `WS1OPT` writer - Wait State 1 Optimization"]
240pub type WS1OPT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCR_SPEC, bool, O>;
241impl R {
242    #[doc = "Bit 0 - Flash Ready Interrupt Enable"]
243    #[inline(always)]
244    pub fn frdy(&self) -> FRDY_R {
245        FRDY_R::new((self.bits & 1) != 0)
246    }
247    #[doc = "Bit 2 - Lock Error Interrupt Enable"]
248    #[inline(always)]
249    pub fn locke(&self) -> LOCKE_R {
250        LOCKE_R::new(((self.bits >> 2) & 1) != 0)
251    }
252    #[doc = "Bit 3 - Programming Error Interrupt Enable"]
253    #[inline(always)]
254    pub fn proge(&self) -> PROGE_R {
255        PROGE_R::new(((self.bits >> 3) & 1) != 0)
256    }
257    #[doc = "Bit 6 - Flash Wait State"]
258    #[inline(always)]
259    pub fn fws(&self) -> FWS_R {
260        FWS_R::new(((self.bits >> 6) & 1) != 0)
261    }
262    #[doc = "Bit 7 - Wait State 1 Optimization"]
263    #[inline(always)]
264    pub fn ws1opt(&self) -> WS1OPT_R {
265        WS1OPT_R::new(((self.bits >> 7) & 1) != 0)
266    }
267}
268impl W {
269    #[doc = "Bit 0 - Flash Ready Interrupt Enable"]
270    #[inline(always)]
271    #[must_use]
272    pub fn frdy(&mut self) -> FRDY_W<0> {
273        FRDY_W::new(self)
274    }
275    #[doc = "Bit 2 - Lock Error Interrupt Enable"]
276    #[inline(always)]
277    #[must_use]
278    pub fn locke(&mut self) -> LOCKE_W<2> {
279        LOCKE_W::new(self)
280    }
281    #[doc = "Bit 3 - Programming Error Interrupt Enable"]
282    #[inline(always)]
283    #[must_use]
284    pub fn proge(&mut self) -> PROGE_W<3> {
285        PROGE_W::new(self)
286    }
287    #[doc = "Bit 6 - Flash Wait State"]
288    #[inline(always)]
289    #[must_use]
290    pub fn fws(&mut self) -> FWS_W<6> {
291        FWS_W::new(self)
292    }
293    #[doc = "Bit 7 - Wait State 1 Optimization"]
294    #[inline(always)]
295    #[must_use]
296    pub fn ws1opt(&mut self) -> WS1OPT_W<7> {
297        WS1OPT_W::new(self)
298    }
299    #[doc = "Writes raw bits to the register."]
300    #[inline(always)]
301    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
302        self.0.bits(bits);
303        self
304    }
305}
306#[doc = "Flash Controller Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcr](index.html) module"]
307pub struct FCR_SPEC;
308impl crate::RegisterSpec for FCR_SPEC {
309    type Ux = u32;
310}
311#[doc = "`read()` method returns [fcr::R](R) reader structure"]
312impl crate::Readable for FCR_SPEC {
313    type Reader = R;
314}
315#[doc = "`write(|w| ..)` method takes [fcr::W](W) writer structure"]
316impl crate::Writable for FCR_SPEC {
317    type Writer = W;
318    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
320}
321#[doc = "`reset()` method sets FCR to value 0"]
322impl crate::Resettable for FCR_SPEC {
323    const RESET_VALUE: Self::Ux = 0;
324}
atsam4ls2a_pac/hflashc/fcr.rs

atsam4ls2a_pac/hflashc/
fcr.rs
