atsam4lc8b_pac/spi/
csr.rs

1#[doc = "Register `CSR%s` reader"]
2pub struct R(crate::R<CSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CSR%s` writer"]
17pub struct W(crate::W<CSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CPOL` reader - Clock Polarity"]
38pub type CPOL_R = crate::BitReader<CPOLSELECT_A>;
39#[doc = "Clock Polarity\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum CPOLSELECT_A {
42    #[doc = "0: The inactive state value of SPCK is logic level zero."]
43    _0 = 0,
44    #[doc = "1: The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices."]
45    _1 = 1,
46}
47impl From<CPOLSELECT_A> for bool {
48    #[inline(always)]
49    fn from(variant: CPOLSELECT_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl CPOL_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> CPOLSELECT_A {
57        match self.bits {
58            false => CPOLSELECT_A::_0,
59            true => CPOLSELECT_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == CPOLSELECT_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == CPOLSELECT_A::_1
71    }
72}
73#[doc = "Field `CPOL` writer - Clock Polarity"]
74pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, CPOLSELECT_A, O>;
75impl<'a, const O: u8> CPOL_W<'a, O> {
76    #[doc = "The inactive state value of SPCK is logic level zero."]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(CPOLSELECT_A::_0)
80    }
81    #[doc = "The inactive state value of SPCK is logic level one.CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce therequired clock/data relationship between master and slave devices."]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(CPOLSELECT_A::_1)
85    }
86}
87#[doc = "Field `NCPHA` reader - Clock Phase"]
88pub type NCPHA_R = crate::BitReader<NCPHASELECT_A>;
89#[doc = "Clock Phase\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum NCPHASELECT_A {
92    #[doc = "0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK."]
93    _0 = 0,
94    #[doc = "1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices."]
95    _1 = 1,
96}
97impl From<NCPHASELECT_A> for bool {
98    #[inline(always)]
99    fn from(variant: NCPHASELECT_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl NCPHA_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> NCPHASELECT_A {
107        match self.bits {
108            false => NCPHASELECT_A::_0,
109            true => NCPHASELECT_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == NCPHASELECT_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == NCPHASELECT_A::_1
121    }
122}
123#[doc = "Field `NCPHA` writer - Clock Phase"]
124pub type NCPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, NCPHASELECT_A, O>;
125impl<'a, const O: u8> NCPHA_W<'a, O> {
126    #[doc = "Data is changed on the leading edge of SPCK and captured on the following edge of SPCK."]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(NCPHASELECT_A::_0)
130    }
131    #[doc = "Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA isused with CPOL to produce the required clock/data relationship between master and slave devices."]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(NCPHASELECT_A::_1)
135    }
136}
137#[doc = "Field `CSNAAT` reader - Chip Select Not Active After Transfer"]
138pub type CSNAAT_R = crate::BitReader<bool>;
139#[doc = "Field `CSNAAT` writer - Chip Select Not Active After Transfer"]
140pub type CSNAAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, bool, O>;
141#[doc = "Field `CSAAT` reader - Chip Select Active After Transfer"]
142pub type CSAAT_R = crate::BitReader<CSAATSELECT_A>;
143#[doc = "Chip Select Active After Transfer\n\nValue on reset: 0"]
144#[derive(Clone, Copy, Debug, PartialEq, Eq)]
145pub enum CSAATSELECT_A {
146    #[doc = "0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved."]
147    _0 = 0,
148    #[doc = "1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select."]
149    _1 = 1,
150}
151impl From<CSAATSELECT_A> for bool {
152    #[inline(always)]
153    fn from(variant: CSAATSELECT_A) -> Self {
154        variant as u8 != 0
155    }
156}
157impl CSAAT_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub fn variant(&self) -> CSAATSELECT_A {
161        match self.bits {
162            false => CSAATSELECT_A::_0,
163            true => CSAATSELECT_A::_1,
164        }
165    }
166    #[doc = "Checks if the value of the field is `_0`"]
167    #[inline(always)]
168    pub fn is_0(&self) -> bool {
169        *self == CSAATSELECT_A::_0
170    }
171    #[doc = "Checks if the value of the field is `_1`"]
172    #[inline(always)]
173    pub fn is_1(&self) -> bool {
174        *self == CSAATSELECT_A::_1
175    }
176}
177#[doc = "Field `CSAAT` writer - Chip Select Active After Transfer"]
178pub type CSAAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSR_SPEC, CSAATSELECT_A, O>;
179impl<'a, const O: u8> CSAAT_W<'a, O> {
180    #[doc = "The Peripheral Chip Select Line rises as soon as the last transfer is achieved."]
181    #[inline(always)]
182    pub fn _0(self) -> &'a mut W {
183        self.variant(CSAATSELECT_A::_0)
184    }
185    #[doc = "The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer isrequested on a different chip select."]
186    #[inline(always)]
187    pub fn _1(self) -> &'a mut W {
188        self.variant(CSAATSELECT_A::_1)
189    }
190}
191#[doc = "Field `BITS` reader - Bits Per Transfer"]
192pub type BITS_R = crate::FieldReader<u8, BITSSELECT_A>;
193#[doc = "Bits Per Transfer\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195#[repr(u8)]
196pub enum BITSSELECT_A {
197    #[doc = "0: 8 bits per transfer"]
198    _8_BPT = 0,
199    #[doc = "1: 9 bits per transfer"]
200    _9_BPT = 1,
201    #[doc = "2: 10 bits per transfer"]
202    _10_BPT = 2,
203    #[doc = "3: 11 bits per transfer"]
204    _11_BPT = 3,
205    #[doc = "4: 12 bits per transfer"]
206    _12_BPT = 4,
207    #[doc = "5: 13 bits per transfer"]
208    _13_BPT = 5,
209    #[doc = "6: 14 bits per transfer"]
210    _14_BPT = 6,
211    #[doc = "7: 15 bits per transfer"]
212    _15_BPT = 7,
213    #[doc = "8: 16 bits per transfer"]
214    _16_BPT = 8,
215}
216impl From<BITSSELECT_A> for u8 {
217    #[inline(always)]
218    fn from(variant: BITSSELECT_A) -> Self {
219        variant as _
220    }
221}
222impl BITS_R {
223    #[doc = "Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> Option<BITSSELECT_A> {
226        match self.bits {
227            0 => Some(BITSSELECT_A::_8_BPT),
228            1 => Some(BITSSELECT_A::_9_BPT),
229            2 => Some(BITSSELECT_A::_10_BPT),
230            3 => Some(BITSSELECT_A::_11_BPT),
231            4 => Some(BITSSELECT_A::_12_BPT),
232            5 => Some(BITSSELECT_A::_13_BPT),
233            6 => Some(BITSSELECT_A::_14_BPT),
234            7 => Some(BITSSELECT_A::_15_BPT),
235            8 => Some(BITSSELECT_A::_16_BPT),
236            _ => None,
237        }
238    }
239    #[doc = "Checks if the value of the field is `_8_BPT`"]
240    #[inline(always)]
241    pub fn is_8_bpt(&self) -> bool {
242        *self == BITSSELECT_A::_8_BPT
243    }
244    #[doc = "Checks if the value of the field is `_9_BPT`"]
245    #[inline(always)]
246    pub fn is_9_bpt(&self) -> bool {
247        *self == BITSSELECT_A::_9_BPT
248    }
249    #[doc = "Checks if the value of the field is `_10_BPT`"]
250    #[inline(always)]
251    pub fn is_10_bpt(&self) -> bool {
252        *self == BITSSELECT_A::_10_BPT
253    }
254    #[doc = "Checks if the value of the field is `_11_BPT`"]
255    #[inline(always)]
256    pub fn is_11_bpt(&self) -> bool {
257        *self == BITSSELECT_A::_11_BPT
258    }
259    #[doc = "Checks if the value of the field is `_12_BPT`"]
260    #[inline(always)]
261    pub fn is_12_bpt(&self) -> bool {
262        *self == BITSSELECT_A::_12_BPT
263    }
264    #[doc = "Checks if the value of the field is `_13_BPT`"]
265    #[inline(always)]
266    pub fn is_13_bpt(&self) -> bool {
267        *self == BITSSELECT_A::_13_BPT
268    }
269    #[doc = "Checks if the value of the field is `_14_BPT`"]
270    #[inline(always)]
271    pub fn is_14_bpt(&self) -> bool {
272        *self == BITSSELECT_A::_14_BPT
273    }
274    #[doc = "Checks if the value of the field is `_15_BPT`"]
275    #[inline(always)]
276    pub fn is_15_bpt(&self) -> bool {
277        *self == BITSSELECT_A::_15_BPT
278    }
279    #[doc = "Checks if the value of the field is `_16_BPT`"]
280    #[inline(always)]
281    pub fn is_16_bpt(&self) -> bool {
282        *self == BITSSELECT_A::_16_BPT
283    }
284}
285#[doc = "Field `BITS` writer - Bits Per Transfer"]
286pub type BITS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, BITSSELECT_A, 4, O>;
287impl<'a, const O: u8> BITS_W<'a, O> {
288    #[doc = "8 bits per transfer"]
289    #[inline(always)]
290    pub fn _8_bpt(self) -> &'a mut W {
291        self.variant(BITSSELECT_A::_8_BPT)
292    }
293    #[doc = "9 bits per transfer"]
294    #[inline(always)]
295    pub fn _9_bpt(self) -> &'a mut W {
296        self.variant(BITSSELECT_A::_9_BPT)
297    }
298    #[doc = "10 bits per transfer"]
299    #[inline(always)]
300    pub fn _10_bpt(self) -> &'a mut W {
301        self.variant(BITSSELECT_A::_10_BPT)
302    }
303    #[doc = "11 bits per transfer"]
304    #[inline(always)]
305    pub fn _11_bpt(self) -> &'a mut W {
306        self.variant(BITSSELECT_A::_11_BPT)
307    }
308    #[doc = "12 bits per transfer"]
309    #[inline(always)]
310    pub fn _12_bpt(self) -> &'a mut W {
311        self.variant(BITSSELECT_A::_12_BPT)
312    }
313    #[doc = "13 bits per transfer"]
314    #[inline(always)]
315    pub fn _13_bpt(self) -> &'a mut W {
316        self.variant(BITSSELECT_A::_13_BPT)
317    }
318    #[doc = "14 bits per transfer"]
319    #[inline(always)]
320    pub fn _14_bpt(self) -> &'a mut W {
321        self.variant(BITSSELECT_A::_14_BPT)
322    }
323    #[doc = "15 bits per transfer"]
324    #[inline(always)]
325    pub fn _15_bpt(self) -> &'a mut W {
326        self.variant(BITSSELECT_A::_15_BPT)
327    }
328    #[doc = "16 bits per transfer"]
329    #[inline(always)]
330    pub fn _16_bpt(self) -> &'a mut W {
331        self.variant(BITSSELECT_A::_16_BPT)
332    }
333}
334#[doc = "Field `SCBR` reader - Serial Clock Baud Rate"]
335pub type SCBR_R = crate::FieldReader<u8, u8>;
336#[doc = "Field `SCBR` writer - Serial Clock Baud Rate"]
337pub type SCBR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 8, O>;
338#[doc = "Field `DLYBS` reader - Delay Before SPCK"]
339pub type DLYBS_R = crate::FieldReader<u8, u8>;
340#[doc = "Field `DLYBS` writer - Delay Before SPCK"]
341pub type DLYBS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 8, O>;
342#[doc = "Field `DLYBCT` reader - Delay Between Consecutive Transfers"]
343pub type DLYBCT_R = crate::FieldReader<u8, u8>;
344#[doc = "Field `DLYBCT` writer - Delay Between Consecutive Transfers"]
345pub type DLYBCT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSR_SPEC, u8, u8, 8, O>;
346impl R {
347    #[doc = "Bit 0 - Clock Polarity"]
348    #[inline(always)]
349    pub fn cpol(&self) -> CPOL_R {
350        CPOL_R::new((self.bits & 1) != 0)
351    }
352    #[doc = "Bit 1 - Clock Phase"]
353    #[inline(always)]
354    pub fn ncpha(&self) -> NCPHA_R {
355        NCPHA_R::new(((self.bits >> 1) & 1) != 0)
356    }
357    #[doc = "Bit 2 - Chip Select Not Active After Transfer"]
358    #[inline(always)]
359    pub fn csnaat(&self) -> CSNAAT_R {
360        CSNAAT_R::new(((self.bits >> 2) & 1) != 0)
361    }
362    #[doc = "Bit 3 - Chip Select Active After Transfer"]
363    #[inline(always)]
364    pub fn csaat(&self) -> CSAAT_R {
365        CSAAT_R::new(((self.bits >> 3) & 1) != 0)
366    }
367    #[doc = "Bits 4:7 - Bits Per Transfer"]
368    #[inline(always)]
369    pub fn bits_(&self) -> BITS_R {
370        BITS_R::new(((self.bits >> 4) & 0x0f) as u8)
371    }
372    #[doc = "Bits 8:15 - Serial Clock Baud Rate"]
373    #[inline(always)]
374    pub fn scbr(&self) -> SCBR_R {
375        SCBR_R::new(((self.bits >> 8) & 0xff) as u8)
376    }
377    #[doc = "Bits 16:23 - Delay Before SPCK"]
378    #[inline(always)]
379    pub fn dlybs(&self) -> DLYBS_R {
380        DLYBS_R::new(((self.bits >> 16) & 0xff) as u8)
381    }
382    #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"]
383    #[inline(always)]
384    pub fn dlybct(&self) -> DLYBCT_R {
385        DLYBCT_R::new(((self.bits >> 24) & 0xff) as u8)
386    }
387}
388impl W {
389    #[doc = "Bit 0 - Clock Polarity"]
390    #[inline(always)]
391    #[must_use]
392    pub fn cpol(&mut self) -> CPOL_W<0> {
393        CPOL_W::new(self)
394    }
395    #[doc = "Bit 1 - Clock Phase"]
396    #[inline(always)]
397    #[must_use]
398    pub fn ncpha(&mut self) -> NCPHA_W<1> {
399        NCPHA_W::new(self)
400    }
401    #[doc = "Bit 2 - Chip Select Not Active After Transfer"]
402    #[inline(always)]
403    #[must_use]
404    pub fn csnaat(&mut self) -> CSNAAT_W<2> {
405        CSNAAT_W::new(self)
406    }
407    #[doc = "Bit 3 - Chip Select Active After Transfer"]
408    #[inline(always)]
409    #[must_use]
410    pub fn csaat(&mut self) -> CSAAT_W<3> {
411        CSAAT_W::new(self)
412    }
413    #[doc = "Bits 4:7 - Bits Per Transfer"]
414    #[inline(always)]
415    #[must_use]
416    pub fn bits_(&mut self) -> BITS_W<4> {
417        BITS_W::new(self)
418    }
419    #[doc = "Bits 8:15 - Serial Clock Baud Rate"]
420    #[inline(always)]
421    #[must_use]
422    pub fn scbr(&mut self) -> SCBR_W<8> {
423        SCBR_W::new(self)
424    }
425    #[doc = "Bits 16:23 - Delay Before SPCK"]
426    #[inline(always)]
427    #[must_use]
428    pub fn dlybs(&mut self) -> DLYBS_W<16> {
429        DLYBS_W::new(self)
430    }
431    #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"]
432    #[inline(always)]
433    #[must_use]
434    pub fn dlybct(&mut self) -> DLYBCT_W<24> {
435        DLYBCT_W::new(self)
436    }
437    #[doc = "Writes raw bits to the register."]
438    #[inline(always)]
439    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
440        self.0.bits(bits);
441        self
442    }
443}
444#[doc = "Chip Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"]
445pub struct CSR_SPEC;
446impl crate::RegisterSpec for CSR_SPEC {
447    type Ux = u32;
448}
449#[doc = "`read()` method returns [csr::R](R) reader structure"]
450impl crate::Readable for CSR_SPEC {
451    type Reader = R;
452}
453#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"]
454impl crate::Writable for CSR_SPEC {
455    type Writer = W;
456    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
457    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
458}
459#[doc = "`reset()` method sets CSR%s to value 0"]
460impl crate::Resettable for CSR_SPEC {
461    const RESET_VALUE: Self::Ux = 0;
462}
atsam4lc8b_pac/spi/csr.rs

atsam4lc8b_pac/spi/
csr.rs
