atsam4lc4b_pac/lcdca/
tim.rs

1#[doc = "Register `TIM` reader"]
2pub struct R(crate::R<TIM_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TIM_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TIM_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TIM_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `TIM` writer"]
17pub struct W(crate::W<TIM_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<TIM_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<TIM_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<TIM_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PRESC` reader - LCD Prescaler Select"]
38pub type PRESC_R = crate::BitReader<bool>;
39#[doc = "Field `PRESC` writer - LCD Prescaler Select"]
40pub type PRESC_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIM_SPEC, bool, O>;
41#[doc = "Field `CLKDIV` reader - LCD Clock Division"]
42pub type CLKDIV_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `CLKDIV` writer - LCD Clock Division"]
44pub type CLKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIM_SPEC, u8, u8, 3, O>;
45#[doc = "Field `FC0` reader - Frame Counter 0"]
46pub type FC0_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `FC0` writer - Frame Counter 0"]
48pub type FC0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIM_SPEC, u8, u8, 5, O>;
49#[doc = "Field `FC0PB` reader - Frame Counter 0 Prescaler Bypass"]
50pub type FC0PB_R = crate::BitReader<bool>;
51#[doc = "Field `FC0PB` writer - Frame Counter 0 Prescaler Bypass"]
52pub type FC0PB_W<'a, const O: u8> = crate::BitWriter<'a, u32, TIM_SPEC, bool, O>;
53#[doc = "Field `FC1` reader - Frame Counter 1"]
54pub type FC1_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `FC1` writer - Frame Counter 1"]
56pub type FC1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIM_SPEC, u8, u8, 5, O>;
57#[doc = "Field `FC2` reader - Frame Counter 2"]
58pub type FC2_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `FC2` writer - Frame Counter 2"]
60pub type FC2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TIM_SPEC, u8, u8, 5, O>;
61impl R {
62    #[doc = "Bit 0 - LCD Prescaler Select"]
63    #[inline(always)]
64    pub fn presc(&self) -> PRESC_R {
65        PRESC_R::new((self.bits & 1) != 0)
66    }
67    #[doc = "Bits 1:3 - LCD Clock Division"]
68    #[inline(always)]
69    pub fn clkdiv(&self) -> CLKDIV_R {
70        CLKDIV_R::new(((self.bits >> 1) & 7) as u8)
71    }
72    #[doc = "Bits 8:12 - Frame Counter 0"]
73    #[inline(always)]
74    pub fn fc0(&self) -> FC0_R {
75        FC0_R::new(((self.bits >> 8) & 0x1f) as u8)
76    }
77    #[doc = "Bit 13 - Frame Counter 0 Prescaler Bypass"]
78    #[inline(always)]
79    pub fn fc0pb(&self) -> FC0PB_R {
80        FC0PB_R::new(((self.bits >> 13) & 1) != 0)
81    }
82    #[doc = "Bits 16:20 - Frame Counter 1"]
83    #[inline(always)]
84    pub fn fc1(&self) -> FC1_R {
85        FC1_R::new(((self.bits >> 16) & 0x1f) as u8)
86    }
87    #[doc = "Bits 24:28 - Frame Counter 2"]
88    #[inline(always)]
89    pub fn fc2(&self) -> FC2_R {
90        FC2_R::new(((self.bits >> 24) & 0x1f) as u8)
91    }
92}
93impl W {
94    #[doc = "Bit 0 - LCD Prescaler Select"]
95    #[inline(always)]
96    #[must_use]
97    pub fn presc(&mut self) -> PRESC_W<0> {
98        PRESC_W::new(self)
99    }
100    #[doc = "Bits 1:3 - LCD Clock Division"]
101    #[inline(always)]
102    #[must_use]
103    pub fn clkdiv(&mut self) -> CLKDIV_W<1> {
104        CLKDIV_W::new(self)
105    }
106    #[doc = "Bits 8:12 - Frame Counter 0"]
107    #[inline(always)]
108    #[must_use]
109    pub fn fc0(&mut self) -> FC0_W<8> {
110        FC0_W::new(self)
111    }
112    #[doc = "Bit 13 - Frame Counter 0 Prescaler Bypass"]
113    #[inline(always)]
114    #[must_use]
115    pub fn fc0pb(&mut self) -> FC0PB_W<13> {
116        FC0PB_W::new(self)
117    }
118    #[doc = "Bits 16:20 - Frame Counter 1"]
119    #[inline(always)]
120    #[must_use]
121    pub fn fc1(&mut self) -> FC1_W<16> {
122        FC1_W::new(self)
123    }
124    #[doc = "Bits 24:28 - Frame Counter 2"]
125    #[inline(always)]
126    #[must_use]
127    pub fn fc2(&mut self) -> FC2_W<24> {
128        FC2_W::new(self)
129    }
130    #[doc = "Writes raw bits to the register."]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.0.bits(bits);
134        self
135    }
136}
137#[doc = "Timing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tim](index.html) module"]
138pub struct TIM_SPEC;
139impl crate::RegisterSpec for TIM_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [tim::R](R) reader structure"]
143impl crate::Readable for TIM_SPEC {
144    type Reader = R;
145}
146#[doc = "`write(|w| ..)` method takes [tim::W](W) writer structure"]
147impl crate::Writable for TIM_SPEC {
148    type Writer = W;
149    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151}
152#[doc = "`reset()` method sets TIM to value 0"]
153impl crate::Resettable for TIM_SPEC {
154    const RESET_VALUE: Self::Ux = 0;
155}
atsam4lc4b_pac/lcdca/tim.rs

atsam4lc4b_pac/lcdca/
tim.rs
