atsam4lc2b_pac/spi/
ier.rs

1#[doc = "Register `IER` writer"]
2pub struct W(crate::W<IER_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IER_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IER_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Receive Data Register Full Interrupt Enable\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum RDRFSELECT_AW {
25    #[doc = "0: No effect."]
26    _0 = 0,
27    #[doc = "1: Enables the corresponding interrupt."]
28    _1 = 1,
29}
30impl From<RDRFSELECT_AW> for bool {
31    #[inline(always)]
32    fn from(variant: RDRFSELECT_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Enable"]
37pub type RDRF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, RDRFSELECT_AW, O>;
38impl<'a, const O: u8> RDRF_W<'a, O> {
39    #[doc = "No effect."]
40    #[inline(always)]
41    pub fn _0(self) -> &'a mut W {
42        self.variant(RDRFSELECT_AW::_0)
43    }
44    #[doc = "Enables the corresponding interrupt."]
45    #[inline(always)]
46    pub fn _1(self) -> &'a mut W {
47        self.variant(RDRFSELECT_AW::_1)
48    }
49}
50#[doc = "Transmit Data Register Empty Interrupt Enable\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq, Eq)]
52pub enum TDRESELECT_AW {
53    #[doc = "0: No effect."]
54    _0 = 0,
55    #[doc = "1: Enables the corresponding interrupt."]
56    _1 = 1,
57}
58impl From<TDRESELECT_AW> for bool {
59    #[inline(always)]
60    fn from(variant: TDRESELECT_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `TDRE` writer - Transmit Data Register Empty Interrupt Enable"]
65pub type TDRE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, TDRESELECT_AW, O>;
66impl<'a, const O: u8> TDRE_W<'a, O> {
67    #[doc = "No effect."]
68    #[inline(always)]
69    pub fn _0(self) -> &'a mut W {
70        self.variant(TDRESELECT_AW::_0)
71    }
72    #[doc = "Enables the corresponding interrupt."]
73    #[inline(always)]
74    pub fn _1(self) -> &'a mut W {
75        self.variant(TDRESELECT_AW::_1)
76    }
77}
78#[doc = "Mode Fault Error Interrupt Enable\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum MODFSELECT_AW {
81    #[doc = "0: No effect."]
82    _0 = 0,
83    #[doc = "1: Enables the corresponding interrupt."]
84    _1 = 1,
85}
86impl From<MODFSELECT_AW> for bool {
87    #[inline(always)]
88    fn from(variant: MODFSELECT_AW) -> Self {
89        variant as u8 != 0
90    }
91}
92#[doc = "Field `MODF` writer - Mode Fault Error Interrupt Enable"]
93pub type MODF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, MODFSELECT_AW, O>;
94impl<'a, const O: u8> MODF_W<'a, O> {
95    #[doc = "No effect."]
96    #[inline(always)]
97    pub fn _0(self) -> &'a mut W {
98        self.variant(MODFSELECT_AW::_0)
99    }
100    #[doc = "Enables the corresponding interrupt."]
101    #[inline(always)]
102    pub fn _1(self) -> &'a mut W {
103        self.variant(MODFSELECT_AW::_1)
104    }
105}
106#[doc = "Overrun Error Interrupt Enable\n\nValue on reset: 0"]
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum OVRESSELECT_AW {
109    #[doc = "0: No effect."]
110    _0 = 0,
111    #[doc = "1: Enables the corresponding interrupt."]
112    _1 = 1,
113}
114impl From<OVRESSELECT_AW> for bool {
115    #[inline(always)]
116    fn from(variant: OVRESSELECT_AW) -> Self {
117        variant as u8 != 0
118    }
119}
120#[doc = "Field `OVRES` writer - Overrun Error Interrupt Enable"]
121pub type OVRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, OVRESSELECT_AW, O>;
122impl<'a, const O: u8> OVRES_W<'a, O> {
123    #[doc = "No effect."]
124    #[inline(always)]
125    pub fn _0(self) -> &'a mut W {
126        self.variant(OVRESSELECT_AW::_0)
127    }
128    #[doc = "Enables the corresponding interrupt."]
129    #[inline(always)]
130    pub fn _1(self) -> &'a mut W {
131        self.variant(OVRESSELECT_AW::_1)
132    }
133}
134#[doc = "End of Receive Buffer Interrupt Enable\n\nValue on reset: 0"]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum ENDRXSELECT_AW {
137    #[doc = "0: No effect."]
138    _0 = 0,
139    #[doc = "1: Enables the corresponding interrupt."]
140    _1 = 1,
141}
142impl From<ENDRXSELECT_AW> for bool {
143    #[inline(always)]
144    fn from(variant: ENDRXSELECT_AW) -> Self {
145        variant as u8 != 0
146    }
147}
148#[doc = "Field `ENDRX` writer - End of Receive Buffer Interrupt Enable"]
149pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, ENDRXSELECT_AW, O>;
150impl<'a, const O: u8> ENDRX_W<'a, O> {
151    #[doc = "No effect."]
152    #[inline(always)]
153    pub fn _0(self) -> &'a mut W {
154        self.variant(ENDRXSELECT_AW::_0)
155    }
156    #[doc = "Enables the corresponding interrupt."]
157    #[inline(always)]
158    pub fn _1(self) -> &'a mut W {
159        self.variant(ENDRXSELECT_AW::_1)
160    }
161}
162#[doc = "End of Transmit Buffer Interrupt Enable\n\nValue on reset: 0"]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum ENDTXSELECT_AW {
165    #[doc = "0: No effect."]
166    _0 = 0,
167    #[doc = "1: Enables the corresponding interrupt."]
168    _1 = 1,
169}
170impl From<ENDTXSELECT_AW> for bool {
171    #[inline(always)]
172    fn from(variant: ENDTXSELECT_AW) -> Self {
173        variant as u8 != 0
174    }
175}
176#[doc = "Field `ENDTX` writer - End of Transmit Buffer Interrupt Enable"]
177pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, ENDTXSELECT_AW, O>;
178impl<'a, const O: u8> ENDTX_W<'a, O> {
179    #[doc = "No effect."]
180    #[inline(always)]
181    pub fn _0(self) -> &'a mut W {
182        self.variant(ENDTXSELECT_AW::_0)
183    }
184    #[doc = "Enables the corresponding interrupt."]
185    #[inline(always)]
186    pub fn _1(self) -> &'a mut W {
187        self.variant(ENDTXSELECT_AW::_1)
188    }
189}
190#[doc = "Receive Buffer Full Interrupt Enable\n\nValue on reset: 0"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum RXBUFFSELECT_AW {
193    #[doc = "0: No effect."]
194    _0 = 0,
195    #[doc = "1: Enables the corresponding interrupt."]
196    _1 = 1,
197}
198impl From<RXBUFFSELECT_AW> for bool {
199    #[inline(always)]
200    fn from(variant: RXBUFFSELECT_AW) -> Self {
201        variant as u8 != 0
202    }
203}
204#[doc = "Field `RXBUFF` writer - Receive Buffer Full Interrupt Enable"]
205pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, RXBUFFSELECT_AW, O>;
206impl<'a, const O: u8> RXBUFF_W<'a, O> {
207    #[doc = "No effect."]
208    #[inline(always)]
209    pub fn _0(self) -> &'a mut W {
210        self.variant(RXBUFFSELECT_AW::_0)
211    }
212    #[doc = "Enables the corresponding interrupt."]
213    #[inline(always)]
214    pub fn _1(self) -> &'a mut W {
215        self.variant(RXBUFFSELECT_AW::_1)
216    }
217}
218#[doc = "Transmit Buffer Empty Interrupt Enable\n\nValue on reset: 0"]
219#[derive(Clone, Copy, Debug, PartialEq, Eq)]
220pub enum TXBUFESELECT_AW {
221    #[doc = "0: No effect."]
222    _0 = 0,
223    #[doc = "1: Enables the corresponding interrupt."]
224    _1 = 1,
225}
226impl From<TXBUFESELECT_AW> for bool {
227    #[inline(always)]
228    fn from(variant: TXBUFESELECT_AW) -> Self {
229        variant as u8 != 0
230    }
231}
232#[doc = "Field `TXBUFE` writer - Transmit Buffer Empty Interrupt Enable"]
233pub type TXBUFE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, TXBUFESELECT_AW, O>;
234impl<'a, const O: u8> TXBUFE_W<'a, O> {
235    #[doc = "No effect."]
236    #[inline(always)]
237    pub fn _0(self) -> &'a mut W {
238        self.variant(TXBUFESELECT_AW::_0)
239    }
240    #[doc = "Enables the corresponding interrupt."]
241    #[inline(always)]
242    pub fn _1(self) -> &'a mut W {
243        self.variant(TXBUFESELECT_AW::_1)
244    }
245}
246#[doc = "NSS Rising Interrupt Enable\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248pub enum NSSRSELECT_AW {
249    #[doc = "0: No effect."]
250    _0 = 0,
251    #[doc = "1: Enables the corresponding interrupt."]
252    _1 = 1,
253}
254impl From<NSSRSELECT_AW> for bool {
255    #[inline(always)]
256    fn from(variant: NSSRSELECT_AW) -> Self {
257        variant as u8 != 0
258    }
259}
260#[doc = "Field `NSSR` writer - NSS Rising Interrupt Enable"]
261pub type NSSR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, NSSRSELECT_AW, O>;
262impl<'a, const O: u8> NSSR_W<'a, O> {
263    #[doc = "No effect."]
264    #[inline(always)]
265    pub fn _0(self) -> &'a mut W {
266        self.variant(NSSRSELECT_AW::_0)
267    }
268    #[doc = "Enables the corresponding interrupt."]
269    #[inline(always)]
270    pub fn _1(self) -> &'a mut W {
271        self.variant(NSSRSELECT_AW::_1)
272    }
273}
274#[doc = "Transmission Registers Empty Enable\n\nValue on reset: 0"]
275#[derive(Clone, Copy, Debug, PartialEq, Eq)]
276pub enum TXEMPTYSELECT_AW {
277    #[doc = "0: No effect."]
278    _0 = 0,
279    #[doc = "1: Enables the corresponding interrupt."]
280    _1 = 1,
281}
282impl From<TXEMPTYSELECT_AW> for bool {
283    #[inline(always)]
284    fn from(variant: TXEMPTYSELECT_AW) -> Self {
285        variant as u8 != 0
286    }
287}
288#[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Enable"]
289pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, TXEMPTYSELECT_AW, O>;
290impl<'a, const O: u8> TXEMPTY_W<'a, O> {
291    #[doc = "No effect."]
292    #[inline(always)]
293    pub fn _0(self) -> &'a mut W {
294        self.variant(TXEMPTYSELECT_AW::_0)
295    }
296    #[doc = "Enables the corresponding interrupt."]
297    #[inline(always)]
298    pub fn _1(self) -> &'a mut W {
299        self.variant(TXEMPTYSELECT_AW::_1)
300    }
301}
302#[doc = "Field `UNDES` writer - Underrun Error Interrupt Enable"]
303pub type UNDES_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, bool, O>;
304impl W {
305    #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"]
306    #[inline(always)]
307    #[must_use]
308    pub fn rdrf(&mut self) -> RDRF_W<0> {
309        RDRF_W::new(self)
310    }
311    #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Enable"]
312    #[inline(always)]
313    #[must_use]
314    pub fn tdre(&mut self) -> TDRE_W<1> {
315        TDRE_W::new(self)
316    }
317    #[doc = "Bit 2 - Mode Fault Error Interrupt Enable"]
318    #[inline(always)]
319    #[must_use]
320    pub fn modf(&mut self) -> MODF_W<2> {
321        MODF_W::new(self)
322    }
323    #[doc = "Bit 3 - Overrun Error Interrupt Enable"]
324    #[inline(always)]
325    #[must_use]
326    pub fn ovres(&mut self) -> OVRES_W<3> {
327        OVRES_W::new(self)
328    }
329    #[doc = "Bit 4 - End of Receive Buffer Interrupt Enable"]
330    #[inline(always)]
331    #[must_use]
332    pub fn endrx(&mut self) -> ENDRX_W<4> {
333        ENDRX_W::new(self)
334    }
335    #[doc = "Bit 5 - End of Transmit Buffer Interrupt Enable"]
336    #[inline(always)]
337    #[must_use]
338    pub fn endtx(&mut self) -> ENDTX_W<5> {
339        ENDTX_W::new(self)
340    }
341    #[doc = "Bit 6 - Receive Buffer Full Interrupt Enable"]
342    #[inline(always)]
343    #[must_use]
344    pub fn rxbuff(&mut self) -> RXBUFF_W<6> {
345        RXBUFF_W::new(self)
346    }
347    #[doc = "Bit 7 - Transmit Buffer Empty Interrupt Enable"]
348    #[inline(always)]
349    #[must_use]
350    pub fn txbufe(&mut self) -> TXBUFE_W<7> {
351        TXBUFE_W::new(self)
352    }
353    #[doc = "Bit 8 - NSS Rising Interrupt Enable"]
354    #[inline(always)]
355    #[must_use]
356    pub fn nssr(&mut self) -> NSSR_W<8> {
357        NSSR_W::new(self)
358    }
359    #[doc = "Bit 9 - Transmission Registers Empty Enable"]
360    #[inline(always)]
361    #[must_use]
362    pub fn txempty(&mut self) -> TXEMPTY_W<9> {
363        TXEMPTY_W::new(self)
364    }
365    #[doc = "Bit 10 - Underrun Error Interrupt Enable"]
366    #[inline(always)]
367    #[must_use]
368    pub fn undes(&mut self) -> UNDES_W<10> {
369        UNDES_W::new(self)
370    }
371    #[doc = "Writes raw bits to the register."]
372    #[inline(always)]
373    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
374        self.0.bits(bits);
375        self
376    }
377}
378#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"]
379pub struct IER_SPEC;
380impl crate::RegisterSpec for IER_SPEC {
381    type Ux = u32;
382}
383#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"]
384impl crate::Writable for IER_SPEC {
385    type Writer = W;
386    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
387    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
388}
389#[doc = "`reset()` method sets IER to value 0"]
390impl crate::Resettable for IER_SPEC {
391    const RESET_VALUE: Self::Ux = 0;
392}
atsam4lc2b_pac/spi/ier.rs

atsam4lc2b_pac/spi/
ier.rs
