atsam4lc2b_pac/ast/
sr.rs

1#[doc = "Register `SR` reader"]
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `OVF` reader - Overflow"]
17pub type OVF_R = crate::BitReader<bool>;
18#[doc = "Field `ALARM0` reader - Alarm 0"]
19pub type ALARM0_R = crate::BitReader<bool>;
20#[doc = "Field `ALARM1` reader - Alarm 1"]
21pub type ALARM1_R = crate::BitReader<bool>;
22#[doc = "Field `PER0` reader - Periodic 0"]
23pub type PER0_R = crate::BitReader<bool>;
24#[doc = "Field `PER1` reader - Periodic 1"]
25pub type PER1_R = crate::BitReader<bool>;
26#[doc = "Field `BUSY` reader - AST Busy"]
27pub type BUSY_R = crate::BitReader<BUSYSELECT_A>;
28#[doc = "AST Busy\n\nValue on reset: 0"]
29#[derive(Clone, Copy, Debug, PartialEq, Eq)]
30pub enum BUSYSELECT_A {
31    #[doc = "0: The AST accepts writes to CV, WER, DTR, SCR, AR, PIR and CR"]
32    _0 = 0,
33    #[doc = "1: The AST is busy and will discard writes to CV, WER, DTR, SCR, AR, PIR and CR"]
34    _1 = 1,
35}
36impl From<BUSYSELECT_A> for bool {
37    #[inline(always)]
38    fn from(variant: BUSYSELECT_A) -> Self {
39        variant as u8 != 0
40    }
41}
42impl BUSY_R {
43    #[doc = "Get enumerated values variant"]
44    #[inline(always)]
45    pub fn variant(&self) -> BUSYSELECT_A {
46        match self.bits {
47            false => BUSYSELECT_A::_0,
48            true => BUSYSELECT_A::_1,
49        }
50    }
51    #[doc = "Checks if the value of the field is `_0`"]
52    #[inline(always)]
53    pub fn is_0(&self) -> bool {
54        *self == BUSYSELECT_A::_0
55    }
56    #[doc = "Checks if the value of the field is `_1`"]
57    #[inline(always)]
58    pub fn is_1(&self) -> bool {
59        *self == BUSYSELECT_A::_1
60    }
61}
62#[doc = "Field `READY` reader - AST Ready"]
63pub type READY_R = crate::BitReader<bool>;
64#[doc = "Field `CLKBUSY` reader - Clock Busy"]
65pub type CLKBUSY_R = crate::BitReader<CLKBUSYSELECT_A>;
66#[doc = "Clock Busy\n\nValue on reset: 0"]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68pub enum CLKBUSYSELECT_A {
69    #[doc = "0: The clock is ready and can be changed"]
70    _0 = 0,
71    #[doc = "1: CEN has been written and the clock is busy"]
72    _1 = 1,
73}
74impl From<CLKBUSYSELECT_A> for bool {
75    #[inline(always)]
76    fn from(variant: CLKBUSYSELECT_A) -> Self {
77        variant as u8 != 0
78    }
79}
80impl CLKBUSY_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub fn variant(&self) -> CLKBUSYSELECT_A {
84        match self.bits {
85            false => CLKBUSYSELECT_A::_0,
86            true => CLKBUSYSELECT_A::_1,
87        }
88    }
89    #[doc = "Checks if the value of the field is `_0`"]
90    #[inline(always)]
91    pub fn is_0(&self) -> bool {
92        *self == CLKBUSYSELECT_A::_0
93    }
94    #[doc = "Checks if the value of the field is `_1`"]
95    #[inline(always)]
96    pub fn is_1(&self) -> bool {
97        *self == CLKBUSYSELECT_A::_1
98    }
99}
100#[doc = "Field `CLKRDY` reader - Clock Ready"]
101pub type CLKRDY_R = crate::BitReader<bool>;
102impl R {
103    #[doc = "Bit 0 - Overflow"]
104    #[inline(always)]
105    pub fn ovf(&self) -> OVF_R {
106        OVF_R::new((self.bits & 1) != 0)
107    }
108    #[doc = "Bit 8 - Alarm 0"]
109    #[inline(always)]
110    pub fn alarm0(&self) -> ALARM0_R {
111        ALARM0_R::new(((self.bits >> 8) & 1) != 0)
112    }
113    #[doc = "Bit 9 - Alarm 1"]
114    #[inline(always)]
115    pub fn alarm1(&self) -> ALARM1_R {
116        ALARM1_R::new(((self.bits >> 9) & 1) != 0)
117    }
118    #[doc = "Bit 16 - Periodic 0"]
119    #[inline(always)]
120    pub fn per0(&self) -> PER0_R {
121        PER0_R::new(((self.bits >> 16) & 1) != 0)
122    }
123    #[doc = "Bit 17 - Periodic 1"]
124    #[inline(always)]
125    pub fn per1(&self) -> PER1_R {
126        PER1_R::new(((self.bits >> 17) & 1) != 0)
127    }
128    #[doc = "Bit 24 - AST Busy"]
129    #[inline(always)]
130    pub fn busy(&self) -> BUSY_R {
131        BUSY_R::new(((self.bits >> 24) & 1) != 0)
132    }
133    #[doc = "Bit 25 - AST Ready"]
134    #[inline(always)]
135    pub fn ready(&self) -> READY_R {
136        READY_R::new(((self.bits >> 25) & 1) != 0)
137    }
138    #[doc = "Bit 28 - Clock Busy"]
139    #[inline(always)]
140    pub fn clkbusy(&self) -> CLKBUSY_R {
141        CLKBUSY_R::new(((self.bits >> 28) & 1) != 0)
142    }
143    #[doc = "Bit 29 - Clock Ready"]
144    #[inline(always)]
145    pub fn clkrdy(&self) -> CLKRDY_R {
146        CLKRDY_R::new(((self.bits >> 29) & 1) != 0)
147    }
148}
149#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
150pub struct SR_SPEC;
151impl crate::RegisterSpec for SR_SPEC {
152    type Ux = u32;
153}
154#[doc = "`read()` method returns [sr::R](R) reader structure"]
155impl crate::Readable for SR_SPEC {
156    type Reader = R;
157}
158#[doc = "`reset()` method sets SR to value 0"]
159impl crate::Resettable for SR_SPEC {
160    const RESET_VALUE: Self::Ux = 0;
161}
atsam4lc2b_pac/ast/sr.rs

atsam4lc2b_pac/ast/
sr.rs
