atsam4e8e_pac/rswdt/
mr.rs

1#[doc = "Register `MR` reader"]
2pub struct R(crate::R<MR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MR` writer"]
17pub struct W(crate::W<MR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `WDV` reader - Watchdog Counter Value"]
38pub type WDV_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `WDV` writer - Watchdog Counter Value"]
40pub type WDV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u16, u16, 12, O>;
41#[doc = "Field `WDFIEN` reader - Watchdog Fault Interrupt Enable"]
42pub type WDFIEN_R = crate::BitReader<bool>;
43#[doc = "Field `WDFIEN` writer - Watchdog Fault Interrupt Enable"]
44pub type WDFIEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
45#[doc = "Field `WDRSTEN` reader - Watchdog Reset Enable"]
46pub type WDRSTEN_R = crate::BitReader<bool>;
47#[doc = "Field `WDRSTEN` writer - Watchdog Reset Enable"]
48pub type WDRSTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
49#[doc = "Field `WDRPROC` reader - Watchdog Reset Processor"]
50pub type WDRPROC_R = crate::BitReader<bool>;
51#[doc = "Field `WDRPROC` writer - Watchdog Reset Processor"]
52pub type WDRPROC_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
53#[doc = "Field `WDDIS` reader - Watchdog Disable"]
54pub type WDDIS_R = crate::BitReader<bool>;
55#[doc = "Field `WDDIS` writer - Watchdog Disable"]
56pub type WDDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
57#[doc = "Field `WDD` reader - Watchdog Delta Value"]
58pub type WDD_R = crate::FieldReader<u16, u16>;
59#[doc = "Field `WDD` writer - Watchdog Delta Value"]
60pub type WDD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MR_SPEC, u16, u16, 12, O>;
61#[doc = "Field `WDDBGHLT` reader - Watchdog Debug Halt"]
62pub type WDDBGHLT_R = crate::BitReader<bool>;
63#[doc = "Field `WDDBGHLT` writer - Watchdog Debug Halt"]
64pub type WDDBGHLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
65#[doc = "Field `WDIDLEHLT` reader - Watchdog Idle Halt"]
66pub type WDIDLEHLT_R = crate::BitReader<bool>;
67#[doc = "Field `WDIDLEHLT` writer - Watchdog Idle Halt"]
68pub type WDIDLEHLT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MR_SPEC, bool, O>;
69impl R {
70    #[doc = "Bits 0:11 - Watchdog Counter Value"]
71    #[inline(always)]
72    pub fn wdv(&self) -> WDV_R {
73        WDV_R::new((self.bits & 0x0fff) as u16)
74    }
75    #[doc = "Bit 12 - Watchdog Fault Interrupt Enable"]
76    #[inline(always)]
77    pub fn wdfien(&self) -> WDFIEN_R {
78        WDFIEN_R::new(((self.bits >> 12) & 1) != 0)
79    }
80    #[doc = "Bit 13 - Watchdog Reset Enable"]
81    #[inline(always)]
82    pub fn wdrsten(&self) -> WDRSTEN_R {
83        WDRSTEN_R::new(((self.bits >> 13) & 1) != 0)
84    }
85    #[doc = "Bit 14 - Watchdog Reset Processor"]
86    #[inline(always)]
87    pub fn wdrproc(&self) -> WDRPROC_R {
88        WDRPROC_R::new(((self.bits >> 14) & 1) != 0)
89    }
90    #[doc = "Bit 15 - Watchdog Disable"]
91    #[inline(always)]
92    pub fn wddis(&self) -> WDDIS_R {
93        WDDIS_R::new(((self.bits >> 15) & 1) != 0)
94    }
95    #[doc = "Bits 16:27 - Watchdog Delta Value"]
96    #[inline(always)]
97    pub fn wdd(&self) -> WDD_R {
98        WDD_R::new(((self.bits >> 16) & 0x0fff) as u16)
99    }
100    #[doc = "Bit 28 - Watchdog Debug Halt"]
101    #[inline(always)]
102    pub fn wddbghlt(&self) -> WDDBGHLT_R {
103        WDDBGHLT_R::new(((self.bits >> 28) & 1) != 0)
104    }
105    #[doc = "Bit 29 - Watchdog Idle Halt"]
106    #[inline(always)]
107    pub fn wdidlehlt(&self) -> WDIDLEHLT_R {
108        WDIDLEHLT_R::new(((self.bits >> 29) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bits 0:11 - Watchdog Counter Value"]
113    #[inline(always)]
114    #[must_use]
115    pub fn wdv(&mut self) -> WDV_W<0> {
116        WDV_W::new(self)
117    }
118    #[doc = "Bit 12 - Watchdog Fault Interrupt Enable"]
119    #[inline(always)]
120    #[must_use]
121    pub fn wdfien(&mut self) -> WDFIEN_W<12> {
122        WDFIEN_W::new(self)
123    }
124    #[doc = "Bit 13 - Watchdog Reset Enable"]
125    #[inline(always)]
126    #[must_use]
127    pub fn wdrsten(&mut self) -> WDRSTEN_W<13> {
128        WDRSTEN_W::new(self)
129    }
130    #[doc = "Bit 14 - Watchdog Reset Processor"]
131    #[inline(always)]
132    #[must_use]
133    pub fn wdrproc(&mut self) -> WDRPROC_W<14> {
134        WDRPROC_W::new(self)
135    }
136    #[doc = "Bit 15 - Watchdog Disable"]
137    #[inline(always)]
138    #[must_use]
139    pub fn wddis(&mut self) -> WDDIS_W<15> {
140        WDDIS_W::new(self)
141    }
142    #[doc = "Bits 16:27 - Watchdog Delta Value"]
143    #[inline(always)]
144    #[must_use]
145    pub fn wdd(&mut self) -> WDD_W<16> {
146        WDD_W::new(self)
147    }
148    #[doc = "Bit 28 - Watchdog Debug Halt"]
149    #[inline(always)]
150    #[must_use]
151    pub fn wddbghlt(&mut self) -> WDDBGHLT_W<28> {
152        WDDBGHLT_W::new(self)
153    }
154    #[doc = "Bit 29 - Watchdog Idle Halt"]
155    #[inline(always)]
156    #[must_use]
157    pub fn wdidlehlt(&mut self) -> WDIDLEHLT_W<29> {
158        WDIDLEHLT_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"]
168pub struct MR_SPEC;
169impl crate::RegisterSpec for MR_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [mr::R](R) reader structure"]
173impl crate::Readable for MR_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"]
177impl crate::Writable for MR_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets MR to value 0x3fff_afff"]
183impl crate::Resettable for MR_SPEC {
184    const RESET_VALUE: Self::Ux = 0x3fff_afff;
185}
atsam4e8e_pac/rswdt/mr.rs

atsam4e8e_pac/rswdt/
mr.rs
